Vias, Connectors, and Packages
Prerequisite Reading Assignment
Chapter 5
2
How are signal getting from one chip to another?
Vias, connectors,
and packages are all
important and
necessary parts of
the path.
The PWB traces
connect between
these.
Pentium 4
goes here
(socket)
Bridge
chip
Bridge chip
package
Introduction
Memory
Connector
2
Agenda
3
Vias
•Definition: what are they and why do we need
them?
•Electrical models of via parastics
Connectors
•Definition: what are they and why do we need
them?
•Electrical effects
•Inductance
•SLEM-style approximation
•Power and ground pins
•Design considerations (tradeoffs, rules of
thumb)
Introduction
3
4
Agenda, continued
Packages
•Definition: what they are and why we need
them
•Common types (e.g. flip-chip, bondwire) and
history
•Creating package models
•Effect of a package on signal integrity
•Design considerations
Introduction
4
5
Vias
Vertical connections between layers made by
drilling a small hole and filling it with conductive
material.
These exist connecting metal layers on Silicon chips, within
packages, and on printed circuit boards.
Vias
capacitor
chip
chip
Printed Circuit Board
Introduction
5
6
Via: vertical connection between layers
• Barrel: conductive cylinder filling the drilled hole
• Pad: connects the barrel to the component/plane/trace
• Antipad: clearance hole between via and no-connect metal layer
Trace connected to pad on layer 1.
Pad
Barrel
Via pad does not
contact plane; void is
the anti-pad
Introduction
6
7
A Via might:
• Connect metal planes of the same potential
(e.g., all ground planes conductively
attached)
• Carry a signal from a trace on one layer to
another (e.g., every data signal must get
from the silicon bump down to the
motherboard…and possibly through the
motherboard!)
• Connect components (such as a capacitor)
to a signal trace or a voltage plane.
Introduction
7
8
PCB via types
Through Hole Via
Blind Via
Buried Via
Step Via
Stacked Via
Introduction
8
SEM cross-sections
9
Plasma generated via
Laser generated via
Cond. ink filled via
Photo-defined via
Introduction
9
SEM Cross-sections
10
microvia
Plated-through hole
Introduction
10
11
Model of a Via
Vias are tiny structures, and unless
T_via delay > 1/10 [signal edge]
the via can be modeled as a lumped pi-model.
L_barrel
To pink t-line
C_pad
Introduction
To dark pink t-line
C_pad
11
Cascading elements
L_barrel
Trace
connection
C_pad
12
L_barrel
Trace
connection
C_pad
Introduction
C_pad
12
Via Capacitance
13
•Effect is to slow the edge
•Empirical formula for pad capacitance:
Cvia
1.41 r D1T

D2  D1
D1 Via pad diameter
D2 Via anti-pad diameter
T PCB thickness
Via Inductance
•Series L degrades signal integrity
•Empirical formula for barrel inductance:
Lvia
4h
 5.08h[ln
 1]
d
Via induced delay:
h via length
d barrel diameter
capacitive loading + added distance
Introduction
13
14
Example 1
Model parasitics of vias
Ladder Model LC’s are good to 1-2 GHz
GND
PWR
Z01
Z02
Introduction
Z01
14
15
Example 2
<200 MHz model parasitics of via stub
*via up to another signal layer
GND
PWR
Z01
L
Z02
Introduction
Z03
15
16
Example 3
More complicated case
GND
PWR
S01(f) Svia(f)
S02(f)
Introduction
16
17
Microstrip: 3 cases with equivalent line length
Introduction
17
Physical Line Length
 Center line distance of a trace
 Manhattan Distance
18
X-Y distance between start and end of
trace
Introduction
18
Estimating the effects of a distributed
capacitive loaded bus
19
t
cL
cL
Short stub ( t  0.5 trise
) connected uniformly
distributed can be modeled as T line with
effective line parameters
L
1
'
'
Z0 
Vp 
C  CL
L(C  CL )
L, C are unit-length parameters of the line,  is capacitance
distribution coefficient
  Number Length
Introduction
19
20
Time Domain Reflectometry
Fast rise
time step
Reference
50 ohm line 1ns Delay
Unknown line
Twice the
delay
Related to
unknown Z0
Corresponds
to 50 ohms
Introduction
20
21
TDR Method - Components
Inexpensive “home grown” TDR
probe
Oscilloscope
50 W air dielectric air
coax (best reference)
Pulse generator*
edge < 100ps
pulse width > 100ns
period > 200 ns
T or
Splitter
Calibration Parts
or
FET
PROBE
50 W calibration
quality terminator
Introduction
21
22
Scope setup
Zoom in on
this edge
Zoom in again on the part of the signal
useful scales are 50 ps/div to 2 ns /div
Highlighted line is area of interest
Introduction
22
23
Calibration Step 1
Place air dielectric coax reference
on cable and leave un-terminated
cable
from
TDR
coax reference
Trace w/out
probe
scale ~ 0.2 ns/div
Vref
1. Use one cursor and measure this line as Vref
Introduction
23
24
Calibration Step 2
Place probe on cable not connected to line
cable
from TDR
time = 0.
Place other cursor on the top of the first peak
Vinc
scale ~ 0.5 ns/div
Keep one horizontal cursor on
previously measured Vref
1. Measure delta voltage between cursors as Vinc
2. Place one vertical cursor just where the waveforms seem to rise
This will be used as a reference for time zero.
Introduction
24
Measurement
25
Place probe on the un-terminated line to be tested
make sure ground is connected respectively
cable
from
TDR
Line under test
Tpd/2
time = 0.
scale ~ 1to 3 ns/div
Vline
1. Use one horizontal cursor to measure Vline a level near time = 0.
2. Use the other vertical cursor to measure twice the propagation delay
Line under test Z0:
Z0
Zref 
Introduction
[ Vinc  ( Vref  Vline) ]
[ Vinc  ( Vref  Vline) ]
25
26
TDR Simple Formula Derivation
Reflection Coef. Definition 1

Vreflected
Vinc
Vreflected
Combine

Vline  Vref
Vline  Vref
Vinc
Reflection Coef. Definition 2

Z0  Zref
Z0  Zref
Equate
Z0  Zref
Z0  Zref
Vline  Vref
Vinc
Solve for Z0
Z0
Zref 
[ Vinc  ( Vref  Vline) ]
[ Vinc  ( Vref  Vline) ]
Introduction
26
27
Effect of structures on TDR
Introduction
27
28
Agenda
Vias
•Definition: what are they and why do we need them?
•Electrical models of via parastics
Connectors
•Definition: what are they and why do we need them?
•Electrical effects
•Inductance
•SLEM-style approximation
•Power and ground pins
•Design considerations (tradeoffs, rules of thumb)
Introduction
28
29
Why do we need connectors ?
Wouldn’t it be better if the silicon were connected directly to the board?
Technically: probably, but…
•Tiny pitch of I/O bumps on silicon: if you soldered it
directly to the motherboard, you wouldn’t be able to attach
traces to all those points…the mb traces aren’t fine enough.
•Need a package around the chip to protect it physically and
thermally.
•Interchangeability (e.g., memory sticks, CPU upgrades)
•OEM inventory control, and manufacturing flexibility.
•Cost
Introduction
29
30
Connectors
Electrically/Mechanically connect one PCB board or PKG to another
Vertically (new PCB perpendicular to mb)
Horizontal (new PCB parallel to mb)
Pentium® III and Pentium® II processor-based
NLX motherboard supporting 66-MHz and 100MHz System Buses
Introduction
30
31
Edge Connectors
PCI
ISA
SLOT1
DIMM
Introduction
APG
31
32
PGA Sockets
PGA370
Introduction
32
33
Connector “Parasitic” Parameters
(Need 2D/3D field solver or lab measurements to get good numbers)
•Series/mutual inductance have major effects
•This is the “wire” of the connector: the signal path
•1st order value can be estimated using empirical formulas
•Series L slows edge
•Complicated coupling  induced noise
•Shunt/mutual capacitance
•Slows the system edge rate
•Cap sometimes added to reduce impedance discontinuity at
connector
•Connector crosstalk
•Because of geometry, mutual L has larger effect than mutual C. For
first-order estimation, just consider L.
Introduction
33
34
Connector Effects
• Series Inductance
(round)
(square)
o
2
  2l  3 
l ln    [nH ]
  r  4
   4l  1 
L  o l ln    [nH ]
2   p  2 
L
r << l
r radius of round wire
l length
p perimeter of rectangular wire
•Approximation of mutual L between 2 connector pins

Lm  o
2
Lm 
o
2
2 
2
 

l
l
s
s






l ln  1     1     [nH ]
l
 s
 s  
l



  2l  
l ln    1[nH ]
  s 
s center-to-center spacing
l length
s<<l
Introduction
*solve in inches
34
35
Example: Pin Inductance
•Simple plug-n-chug  get an idea of realistic values
Calculate the series L of pin A and the mutual inductance
between the pin pairs (assuming equal currents).
A
p=.04” (40 mils)
l=.20” (200mils)
s=.050” (50 mils)
O=4 x 10-7 H/m
L=3.552nH
Lm=1.335nH
Introduction
35
36
Example of a 3x3 L matrix
54
58
15
r=3.4
30
245.9 47.53 14.34
L=
47.53 241.7 47.53
nH/m
14.34 47.53 246.0
Introduction
36
37
Inductive Coupling in Connector Pin Fields
1
1
2
2
3
3
Drivers
Receivers
Voltage induced on pin 2 due to current changes in 1, 2, and 3
dI 2
dI 1
dI 3
v2  L22
 L21
 L23
dt
dt
dt
Introduction
37
SLEM
38
Q: Using the SLEM method described earlier, what
approximate model describes the voltage induced
on victim line 2 in the cases of odd and even
switching?
A:
dI
v2  L22  L21  L23 
dt
dI
v2  L22  L21  L23 
dt
Introduction
All bits switching in phase
Bit 2 switching out of
phase with 1 and 3.
38
39
We left out something very important two pages ago.
Pwr pin
Drivers
+
__
Gnd pin
Receivers
Just like a circuit with a lightbulb, the
current through the signal pins must return
to the source through the ground/pwr pins.
Introduction
39
40
Q: Draw the current path (loop) for the case when the
driver switches low (I.e., pulls down through the n-device).
A:
PWR pin
RTT
+
__
Signal pin
GND pin
Introduction
40
41
Inductive noise
induced from changing current
through the ground pin:
V  Lgnd
dI
dt
What if 3 signals pins all share the same ground pin?
dI
V  Lgnd 3
dt
*Ignoring mutuals. The Lgnd in
these 2 formulas are not exactly
the same!
Also, since inductance is proportional to the area of the loop of
current, the farther a signal pin is from the ground pin, the greater
the inductance!
Bigger Loop, bigger L
Smaller Loop, smaller L
Introduction
41
42
Q: Keeping in mind the buffer structure from the previous question,
draw the current loops for each of the 3 drivers as they pull down.
Which pin has the most inductance to ground?
Pwr pin
1
1
2
2
3
3
Drivers
Gnd pin
Receivers
A: Biggest L: Signal 1
Introduction
42
43
Example: L and its effect
I1
V1
I
V2
1
2
3
2
I3
V3
Ig=(I1+I2+I3)
Vg
Write an algebraic
equation which
describes the noise
induced on the center
conductor relative to
ground.
Based on that result:
draw an equivalent
circuit with the ground
understood.
Gnd Pin
Write V2 and Vg as a SLdi/dt (4 terms each)
Calculate V2’ based on
•V2-Vg
•Ig=-(I1+I2+I3)
Get the equivalent circuit Lij’ by generalizing from the V2’ equation
Introduction
43
44
Example: continued
L’ij=Lij-Lig-Lgj+Lgg
L=200 mils
W=10 mils
50mils pitch
Lm_gnd=.61nH
L22=3.55nH
Lm_sig=1.33nH
Lm_gnd=.84nH
Gnd Pin
Here are the numbers for the example:
calculate the values for the equivalent circuit
Introduction
44
45
Solution to example
L=200 mils
W=10 mils
50mils pitch
Lm=3.43nH
L22=5.42nH
Lm=2.71nH
3.43nH
5.42nH
2.71nH
Gnd Pin
L’ij=Lij-Lig-Lgj+Lgg
•Can’t just add/subtract for even/odd: Currents more complicated
Introduction
45
46
Effects of series L on signal transmission
Zo
Zo
VL (t )
L
Zo
Z  sL  Z 0
sL
 0

Z 0  sL  Z 0 2Z 0  sL
T
2Z 0
1

2 Z 0  sL 1  s
Step Response: VL (s)  1 
1 1

2  1  s s 
Equivalent risetime:
Zo
s  j
  L 2Z
0


1
VL (t )  1  e t / U (t )
2
trise  2.2  L Z 0
* All risetimes are for 10% - 90%
Introduction
46

47
Obviously it matters
1. How many signals share each return pin.
• Different signaling types (e.g. GTL, CMOS) require
different returns. Must be aware.
2. Where the signal pins are relative to their nearest
return pin neighbors.
So why don’t we just put a return pin next to each pin?
On Pentium 4, there are 370 pins. If we had a ground pin
next to each data and address signal, that’d use up 200 pins!
Leaving only 170 to be divided up for power delivery, control
signals, clocks… So why don’t we just add more pins?
Costs too much, can’t make the pinout and connector
arbitrarily large.
Introduction
47
48
Q: Assuming that the return currents flow equally through both
power and ground pins, rank the following connector pin patterns
(each has 8 signals) from worst to best for performance and note
pros and cons about each option.
GSSSSSSSSP
•P and G pins far from signals: maximizes noise.
•Pin to pin signal crosstalk huge.
•Cheap…so small!
GSSPSSGSSPSSG
GSPSGSPSGSPSGSPSG
•P and G pin next to each signal.
•Signal pins shielded from each other.
•70% bigger than “worst” option.
•P and G pins closer to signals.
•Pin to pin signal crosstalk smaller.
•30% bigger than the “worst” option.
GPSGPSGPSGPSGPSGPSGPSGPSGP
•Power and ground pins next to every signal.
•Signal pins shielded from each other.
•P and G pins adjacent which reduces their L more.
Introduction
48
49
Timing effects for different signal:ground pin ratios
Signal
Ground
•Pins get assigned, but how?
2:1
1:1
Pushout/Pullin  Right-hand Rule
Introduction
4:1
49
50
Even Mode timing PUSH-OUT as sig:gnd pin ratio changes
driver
receiver
Single bit
Even mode 1:1 ratio
Even mode 2:1 ratio
Even mode 4:1 ratio
Introduction
50
51
Effect of different sig:gnd ratios with even/odd switching
•Right-hand-rule: even mode pushes out, odd mode pulls in
*Does not include transmission line coupling effect.
Introduction
51
52
Calculate effect of shunt C on risetime
Exercise
Zo
Zo
Zo
C
Zo
Question: Why did we ignore C but use L
when calculating pushout?
Introduction
52
53
Shunt Capacitor
Z0
Z0
U(t)
Z0
C
Z0
( sC ) 1 // Z 0  Z 0
 s


( sC ) 1 // Z 0  Z 0 1  s
s  j
( sC ) 1 // Z 0
1/ 2
T

Z 0  ( sC ) 1 // Z 0 1  s
  CZ0 / 2
Step Response:
VL ( s ) 
Equivalent risetime:
1/ 2 1
1  s s


1
VL (t )  1  e t / U (t )
2
trise  2.2  CZ 0
Introduction
53
54
Connector design considerations: Summary
•Cost
•Connector length (minimize!)
•Series L and Z discontinuities (minimize!)
•Pin Pattern
•Power and Ground pins adjacent
•Each signal pin coupled to a return pin
•Modeling: field solvers or measurements: no simple way
Introduction
54
55
Agenda
Packages
•Definition: what they are and why we need them
•Common types (e.g. flip-chip, bondwire) and history
•Creating package models
•Effect of a package on signal integrity
•Design considerations
Introduction
55
56
Chip Package
•Container for the integrated circuit
•Provides mechanical, electrical, and thermal connections
necessary for system functionality.
Introduction
56
57
Connections made in a package
•Attachment of die to package
•On-package connections
•Attachment of package to PCB
Introduction
57
58
Attachment of die to package
•Wire bond
A ring of bondwire attach pads
on the periphery of the face of the
die. On the package, the
bondwire lands on package
routing. A bondwire is about 1mil
in diameter, 50-500mils long. A
bondwire acts like an inductor.
The die is placed face down.
Solder balls attach the on-die
pads to the surface of the
package. The die pads are not
limited to the periphery. The
technology is self-aligning because
the solder ball surface tension
pulls the die pads into alignment
with the package pads.
•Flip-chip
Introduction
58
59
Q: Fill in this table noting pros/cons to each technology
Wirebond
Flip-Chip
Inductance
Much higher (1-5nH)
Much less (.1nH)
Crosstalk
High
Virtually none!
Cost
Cheap!
High
Good
Physical tolerances tight
since must align.
Mechanical
Thermal
Back of die attached to pkg
for max surface area contact
and max heat transfer out.
Ugly: thermal coefficients of die and
package must be similar or expansion
will break it. Cooling hard because
die lifted off package by solder balls.
Die Size
Limits I/O since pads only
around periphery.
Die size can be minimized
even when many I/O’s.
Introduction
59
60
Wirebond Modeling
Ball bond
Bond pad
Routing on Package
Package dielectric layer
Chip
Package Substrate
(reference plane in this case)
A
B
C
D
•To approximate by hand:
•Subdivide the problem into sections for approximation
•Sections A and D are roughly perpendicular to the plane beneath, so they
can be approximated using a simple straight-wire formula.
o
L
2
  2l  3 
l ln    
  r  4
For round wire, r<<l

L o
2
  4l  1 
l ln    
 2
  pIntroduction
For rectangular wire
60
61
Wirebond Modeling by hand, continued:
•Sections B and C are roughly parallel to the plane. Their approximation
must therefore consider the presence of the plane. Each section has a
different (rough) height from the plane.
LA
4h
L  l (5.08 10 ) ln
d
LB
LC
LD
9
Cpad
•To create a much
better model:
• Use a 3D field
solver.
Introduction
61
62
Routing of Signals within Package
•Small T-lines route from bond pad of package to the
board attachment (e.g., pin or solder ball)
•High speed design requires controlled impedance
• A miniature PCB: layers, power/ground planes.
Layers have well-defined impedance and there are
routing rules that consider effects like crosstalk.
Introduction
62
63
Attachment of package to the board
• Lead frame: metal frame connects wire bonds to PCB
• PGA: array of pins that stick out of the package
• BGA: array of solder balls that attach to board
• LGA: array of pads that attach to board
Remember the connector section? Sounds like a BGA
would be better than a PGA…short, simple solder balls
versus long metal pins? But there are important business
reasons for the socketable PGA.
• Interchangeability (e.g., memory sticks, CPU upgrades)
• OEM inventory control, the impact of tax and duty, and
manufacturing flexibility.
Introduction
63
64
Packaging Timeline as requirements/technology developed
Ceramic DIP
• Product: 8086, 8088
• Features: Wirebond, 1 row of pins, 1 layer
Ceramic Pin Grid Array
• Product: 286, 386, 486, Pentium
• Features: More pins, multi-layer, increasingly more
attention to signal quality and power delivery and
thermal management
• Reason for change: More I/O, Performance
Introduction
64
65
Packaging Timeline as requirements/technology developed
Dual Cavity Ceramic Pin Grid Array
•Product: P6
•Features: Memory and CPU packaged together
•Reason for change: Performance requirements
Introduction
65
66
Packaging Timeline as requirements/technology developed
Plastic Land Grid Array (PLGA)
•Product: 2nd generation P6
•Features: CPU and memory separate but in cartridge
•Reason for change: Cost
Introduction
66
67
Packaging Timeline as requirements/technology developed
Flip-Chip Ball Grid Array (FCBGA, OLGA)
•Product: Chipsets, Pentium 4
•Features: No wirebond but must be soldered to board or
to an intermediary socketable component
•Reason for change: More I/O in smaller space, less L
Introduction
67
68
Packaging Timeline as requirements/technology developed
Flip-Chip Pin Grid Array (FCPGA)
•Product: Pentium 3, 2nd generation Pentium 4
•Features: High-performance substrate and no wirebond
•Reason for change: Performance, relative thermals of
die and package and motherboard, directly socketable
Introduction
68
69
Packaging Timeline as requirements/technology developed
Flip-Chip Pin Grid Array (FCPGA)
Introduction
69
70
Modeling of a Package
 Traces
 Transmission Line
 Via
 Inductor/Capacitor
 Connector  Inductor/Capacitor
 Pwr/Gnd plane
Introduction
70
71
Package Modeling
•
•
Trace the path of the signal from the die to the motherboard.
Let’s try an example with a BGA bondwire package. It’s logical
to break this particular problem into six sections.
1.
Silicon
2.
Bondwires
3.
Package routing
4.
Via pads
5.
Ball pads
6.
PCB (motherboard) traces
Package Traces:
coupling and xD
sections
Top-view of pkg
Bondwire side-view
and x-sections
C
H
B
A B
A
1 2 3
D
A
C
Die
B
B
H
A
Introduction
71
72
Package Modeling
LA
Lvia
LB
Lball
Cvia
Cpadpkg
Cpadchip
K
LA
A
B
C
K
LA
Cpadchip
Cballpad
K
Cpcbpad
LB
Lvia
Cpadpkg
Cpadchip
D
Lball
Cvia
Cballpad
K
LB
Cpcbpad
Lvia
Lball
Cvia
Cpadpkg
Cballpad
Coupled sections on
package traces.
Introduction
Cpcbpad
72
73
Full System Modeling – Putting it together
• If the package model seemed complex,
imagine an entire system. How about one
with >2 driving chips?
CPU2
Chipset
CPU 1
Introduction
73
74
Modeling of short stubs
Zb
Zo
Short stub
TDstub Zo
( TDstub  0.5 trise ) treated as lumped C:
Zo
Zo
TDstub
Cstub 
Zb
Introduction
74
75
Modeling of long stubs – more variants
Cload
Zb
TDstub Zo
Zo
Long stub ( TDstub  0.5 trise ) modeled as T line; And
Cload modeled as a segment of T line
Zb
Zb
Zo
TDc  ZbCload
TDc
TDstub Zo
Simplification in based on edge rate
Introduction
75
76
Summary
Interconnect is The path that connects one silicon die (e.g.
CPU, chipset, memory…) to another.
• Silicon has driving and receiving buffers.
• Vias are vertical metal interconnections that connect
different metal layers (within packages and PCB boards
and on silicon)
• Connectors are designed to connect multiple PCB boards
• Packages have vias and traces designed to interface die
and PCB boards
• PCB boards have vias and traces to connect various
component packages.
Introduction
76