Graduate Computer Architecture I
VHDL Structure and
Testing
Michael Sorensen
Overview
• Everything You Always Wanted To Know About Synthesizable
VHDL But Where Afraid To Ask by William D. Richard, PhD.
• Components
• VHDL 2 Process Structure
– ALU using 2 Processes
• Using Modelsim (Tips)
• Testing
– VHDL Test bench / Test Vectors
– Modelsim Do files
• VHDL Debugging Notes and Tips
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Everything You Always Wanted To Know
• Everything You Always Wanted To Know About Synthesizable
VHDL But Where Afraid To Ask by William D. Richard, PhD.
– It is available on the website, just remember William D. Richard.
– It is a great resource for those that don’t have a VHDL book.
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Components
Component AND2
architecture Behavioral of and4 is
entity and2 is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic);
end and2;
architecture Behavioral of and2 is
Begin
component and2
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic);
end component;
s <= a and b;
end Behavioral;
Begin
and2one:and2
port map ( a => a,
b => b,
s => temp1);
Component AND4
entity and4 is
Port ( a :
b :
c :
b :
s :
end and4;
signal temp1, temp2 : std_logic;
in std_logic;
in std_logic;
in std_logic;
in std_logic;
out std_logic);
and2two:and2
port map ( a => c,
b => d,
s => temp2);
and2three:and2
port map ( a => temp1,
b => temp2,
s => s);
end Behavioral;
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-- Ports must match
VHDL 2 Process Structure
• Benefits
– Design Pattern, easily recognized
– “Easier” to program
– “Easier” to debug
– Works best for finite state machines
• Basics
– First process defines what occurs on a rising clock
– Second process defines the combinational logic
• Basics (in terms of finite state machine)
– First process sets the state from the next_state on a rising clock
– Second process calculates the next_state
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VHDL 2 Process Structure
entity example is
Port ( clk : in std_logic;
reset : in std_logic;
a : in std_logic_vector(31 downto 0);
z : out std_logic_vector(31 downto 0));
end example;
architecture Behavioral of example is
signal a_int, z_int : std_logic_vector(31 downto 0);
Begin
-- D-Flip Flops
process (clk)
-- <-- process of only clock
begin
if clk'event and clk = '1' then
-- <-- proper way to trigger on a rising clock edge
if reset = '1' then
-- <-- proper way to create a reset
z <= “00000000000000000000000000000000”;
a_int <= “00000000000000000000000000000000”;
else
a_int <= a;
z <= z_int;
end if;
end if;
end process;
-- Combinational Logic
process (a_int) -- <-- process of signals used in c/l but no clock
begin
-- z_int <= F(a_int);
end process;
end Behavioral;
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ALU using the 2 Processes
entity alu32bit is
Port ( clk : in std_logic;
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(31 downto 0);
ctrl : in std_logic_vector(2 downto 0);
z : out std_logic_vector(31 downto 0);
ovr : out std_logic;
zero : out std_logic);
end alu32bit;
architecture Behavioral of alu32bit is
signal
signal
signal
signal
a_int, b_int, z_int : std_logic_vector(31 downto 0);
ctrl_int : std_logic_vector(2 downto 0);
ovr_int, zero_int : std_logic;
tmp1, tmp2 : std_logic_vector(31 downto 0);
begin
process (clk)
begin
if clk'event and clk = '1' then
a_int <= a;
b_int <= b;
ctrl_int <= ctrl;
z <= z_int;
ovr <= ovr_int;
zero <= zero_int;
end if;
end process;
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ALU using the 2 Processes (cont.)
process (a_int, b_int, ctrl_int, tmp1, tmp2)
begin
ovr_int <= '0';
zero_int <= '1';
z_int <= tmp1;
case ctrl is
when "000" => -- ADD
-- REMOVED FOR SPACE REASONS
when "001" => --SUBTRACT
tmp1 <= a_int - b_int;
if tmp1 = "00000000000000000000000000000000" then
zero_int <= '0';
end if;
when "010" => --bitwise AND
tmp1 <= a_int and b_int;
when "011" => --bitwise OR
tmp1 <= a_int or b_int;
when "100" => --bitwise XOR
tmp1 <= a_int xor b_int;
when "101" => --shift
tmp1 <= to_stdlogicvector(to_bitvector(a_int) sll conv_integer(b_int));
when "110" => --less
if a_int < b_int then
tmp1 <= "00000000000000000000000000000001";
else
tmp1 <= "00000000000000000000000000000000";
end if;
when others => null;
end case;
end process;
end Behavioral;
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Using Modelsim (Tips)
• Commands:
– vcom
• Modelsim’s vhdl compiler. Run Vcom and a GUI pops up to allow you
to select files to compile. Make sure you do them in order of
dependency.
– vsim
• Start a simulation. Example: vsim alu32bit
(notice no .vhd)
– quit -sim
• Exits out of a simulation. For you to recompile if you make changes.
– restart -f
• Restarts a simulation. For you to change your do file and rerun it.
• Zoom Full, the blue magnify glass, Auto Scales the wave form
• Change Radix, right click on signals, select Radix
– View signals or vectors in Binary, Unsigned, Decimal, etc.
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Testing (VHDL Test Vectors)
• To create one select, New Source, VHDL Test Bench
• OR – Create a new VHDL Module and rewrite
• Benefit – can be set to check desired results
Example: Synchronized And Gate
entity syncand2 is
Port ( clk : in std_logic;
a : in std_logic;
b : in std_logic;
s : out std_logic);
end syncand2;
architecture Behavioral of syncand2 is
begin
process (clk)
begin
if clk'event and clk = '1' then
s <= a and b;
end if;
end process;
end Behavioral;
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Testing (VHDL Test Vectors)
library ieee;
use ieee.std_logic_1164.all;
entity syncand2tb is
end syncand2tb;
-- No Ports for VHDL Test Bench
architecture stimulus of syncand2tb is
component syncand2
Port ( clk : in std_logic;
a : in std_logic;
b : in std_logic;
s : out std_logic);
end component;
signal
signal
signal
signal
signal
signal
clk : std_logic;
a: std_logic;
b: std_logic;
s: std_logic;
vector_cnt: integer := 1;
error_flag: std_logic := '0';
type test_record is record
a: std_logic;
b: std_logic;
s: std_logic;
end record;
-- Declare a record type
-- Signals of component to test
-- Expected result
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Testing (VHDL Test Vectors)
The Test Vectors
type test_array is array(positive range <>) of test_record;
-- in an array
-- Collect them
-- The following constant declaration describes the test vectors to be
-- applied to the design during simulation, and the expected result after a
-- rising clock edge.
constant test_vectors : test_array := (
-- a, b, s
('0', '0', '-'), -- RESET (IGNORE THE RESULT)
('0',
('1',
('0',
('1',
('0',
);
'0',
'0',
'1',
'1',
'0',
'0'),
'0'),
'0'),
'1'),
'0')
begin
-- instantiate the component
UUT: syncand2
port map ( clk => clk,
a => a,
b => b,
s => s);
-- instance declared as UUT (Unit Under Testing)
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Testing (VHDL Test Vectors)
-- provide stimulus and check the result
testrun: process
variable vector : test_record;
begin
for index in test_vectors'range loop
vector_cnt <= index;
vector := test_vectors(index); -- Get the current test vector
-- Apply the input stimulus...
a <= vector.a;
b <= vector.b;
-- Clock (low-high-low) with a 100 ns cycle...
clk <= '0';
wait for 25 ns;
-- Quarter of the desired clock cycle
clk <= '1';
wait for 50 ns;
-- Half of the desired clock cycle
clk <= '0';
wait for 25 ns;
-- Quarter of the desired clock cycle
-- Check the results...
if (vector.s /= '-'
and s /= vector.s) then
error_flag <= '1';
assert false
report "Output did not match!"
severity WARNING;
else
error_flag <= '0';
end if;
end loop;
wait;
end process;
end stimulus;
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Testing (VHDL Test Vectors)
Results
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Testing (Modelsim Do files)
• To create a Do file use any standard text editor
Example: Synchronized And Gate
entity syncand2 is
Port ( clk : in std_logic;
a : in std_logic;
b : in std_logic;
s : out std_logic);
end syncand2;
architecture Behavioral of syncand2 is
begin
process (clk)
begin
if clk'event and clk = '1' then
s <= a and b;
end if;
end process;
end Behavioral;
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Testing (Modelsim Do files)
Set a clock
force -freeze sim:/syncand2/clk 1 0, 0 {50 ps} -r 100ps
Force a signal
force -freeze sim:/syncand2/a 0 0
• Copy generated commands to do file
• To read bidirectional lines after Freezing them, select Force,
set value to Z and set Kind to Deposit
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Testing (Modelsim Do files)
syncand2.do
force -freeze
force -freeze
force -freeze
run 200
force -freeze
force -freeze
run 100
force -freeze
force -freeze
run 100
force -freeze
force -freeze
run 100
force -freeze
force -freeze
run 200
sim:/syncand2/clk 1 0, 0 {50 ps} -r 100ps
sim:/syncand2/a 0 0
sim:/syncand2/b 0 0
To run do file from
Modelsim command
prompt type:
sim:/syncand2/a 1 0
sim:/syncand2/b 0 0
VSIM #> do syncand2.do
sim:/syncand2/a 0 0
sim:/syncand2/b 1 0
sim:/syncand2/a 1 0
sim:/syncand2/b 1 0
sim:/syncand2/a 0 0
sim:/syncand2/b 0 0
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Default unit of time is ns.
VHDL DEBUGING NOTES AND TIPS
• Make backups, at least backup copies of working code before
you add features to it.
• Correct all undefined (red) signals in Modelsim first.
• Check sensitivity list
• Check that signals are only modified/driven in one process (or
if outside of a process, modified/driven on only one line)
• If problems are with bidirectional lines make sure that
components correctly share line. And if your forcing the line
in simulation remember to deposit Z’s before you want to read
values from it.
• Ask Questions!
18 - CSE/ESE 560M – Graduate Computer Architecture I