Metal Gate PMOS Process - People
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Metal Gate PMOS Process Metal Gate PMOS Process This is the process flow you will use to fabricate your own transistors in the sophomore level EMCR350 course 10 Micrometer Design Rules 4 Design Layers 4 Photolithography Layers Metal (Aluminum) Gate Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-1 Metal Gate PMOS Process Process Flows 1 Resistors PMOS Transistors Get wafer, scribe and clean Grow masking oxide Pattern for diffusion Etch masking oxide Strip resist Clean and spin on dopant Diffuse Strip off dopant source and masking oxide Grow new thick oxide Get wafer, scribe and clean Grow masking oxide Pattern for diffusion Etch masking oxide Strip resist Clean and spin on dopant Diffuse Strip off dopant source and masking oxide Grow new thick oxide Pattern for thin (gate) oxide Grow gate oxide Pattern for contact cuts Etch thick oxide Strip resist Deposit Aluminum Pattern for aluminum etch Etch Aluminum Strip resist Sinter 1 2 2 3 Pattern for contact cuts Etch thick oxide Strip resist Deposit Aluminum Pattern for aluminum etch Etch Aluminum Strip resist Sinter 3 4 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-2 Metal Gate PMOS Process Design Rules The smallest a contact can be is one unit (lambda, l) by one unit. In this case lambda will be 10 microns Diffusion and metal have to extend at least one unit around a contact The gate oxide has to extend over a diffusion by at least on unit Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-3 Metal Gate PMOS Process STARTING WAFER N-TYPE, 5 OHM-CM Silicon Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-4 Metal Gate PMOS Process ID01 - Scribe Identification Code on the Wafer DE01 - Four Point Probe to Check Resistivity I V D1 L030924 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-5 Metal Gate PMOS Process OXIDE THICKNESS COLOR CHART Thickness 500 700 1000 1200 1500 1700 2000 2200 2500 2700 3000 3100 3200 3400 3500 3600 3700 3900 4100 4200 4400 4600 4700 Color Tan Brown Dark Violet - Red Violet Royal Blue Light Blue - Metallic Blue Metallic - very light Yellow Green LIght Gold or Yellow - Slightly Metallic Gold with slight Yellow Orange Orange - Melon Red Violet Blue - Violet Blue Blue Blue - Blue Green Light Green Green - Yellow Green Yellow Green Yellow Light Orange Carnation Pink Violet Red Red Violet Violet Blue Violet Thickness 4900 5000 5200 5400 5600 5700 5800 6000 6300 6800 7200 7700 8000 8200 8500 8600 8700 8900 9200 9500 9700 9900 10000 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 Color Blue Blue Green Green Yellow Green GreenYellow Yellow -"Yellowish"(at times appears to be Lt gray or matellic) Light Orange or Yellow - Pink Carnation Pink Violet Red "Bluish"(appears violet red, Blue Green, looks grayish) Blue Green - Green "Yellowish" Orange Salmon Dull, LIght Red Violet Violet Blue Violet Blue Blue Green Dull Yellow Green Yellow - "Yellowish" Orange Carnation Pink EMCR201 PMOS page-6 Metal Gate PMOS Process Dry Oxidation 1.0 Oxide Thickness (mm) Oxide Thickness (mm) 1.0 0.1 0.01 0.1 0.1 0.01 1.0 10.0 0.1 Oxidation time in hours Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 1.0 Oxidation time in hours EMCR201 PMOS page-7 10.0 Metal Gate PMOS Process Steam Oxidation 10 Oxide Thickness (mm) Oxide Thickness (mm) 10 1 1 0.1 0.1 0.01 0.01 0.1 1.0 Oxidation time in hours 10.0 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 0.1 1.0 Oxidation time in hours 10.0 EMCR201 PMOS page-8 Metal Gate PMOS Process MINIMUM OXIDE THICKNESS FOR DIFFUSION MASKING 10 1200 C Phos. 1 1000 1100 900 Xox , µm 1200 10-1 1100 Boron 1000 10-2 900 10-3 10 t, Time, (min) 100 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 1,000 EMCR201 PMOS page-9 Metal Gate PMOS Process RCA Clean then Grow 5000 Å Oxide Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 48 min. in wet O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2 5000 Å SiO2 Bare silicon After silicon dioxide growth (should look blue-green) It can be hard to tell under the microscope Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-10 Metal Gate PMOS Process STEP ETCH APPARATUS Oxide Plastic, right! BUFFERED HF Lower 1/4 inch every 30 seconds Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-11 Metal Gate PMOS Process ETCH STEPS IN OXIDE ON C1 4200 Å 3500 Å 2800 Å 2100 Å 1400 Å 700 Å BARE SILICON Top View Side View Actual colors are not this saturated Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-12 Metal Gate PMOS Process COAT WITH PHOTORESIST 1 µm Positive Photoresist 5000 Å SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-13 Metal Gate PMOS Process Expose with Mask Layer One – Diffusion Openings 1x Mask opaque clear Ultra-Violet Radiation Shadow exposed areas develop away positive photoresist SiO2 Silicon Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-14 Metal Gate PMOS Process ETCH OXIDE Not drawn to the same scale horizontally as vertically, the actual Cross-sectional view should be 20-50 times wider. Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-15 Metal Gate PMOS Process STRIP RESIST and RCA CLEAN Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-16 Metal Gate PMOS Process After Patterning of Diffusion Masking Oxide Bare Silicon Silicon Dioxide Diffusion openings (Bare Silicon) Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-17 Metal Gate PMOS Process SPIN-ON P-TYPE DOPANT Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-18 Metal Gate PMOS Process PRE-DEPOSIT, OXIDE ETCH and RCA CLEAN Xj1 rs1 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-19 Metal Gate PMOS Process ETCH STEPS IN OXIDE ON C5 FIND SLOW AND FAST ETCH RATES SiO2 Mask Si 8000 Å SLOW FAST BARE SILICON After diffusion and step etch Before Diffusion Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-20 Metal Gate PMOS Process PAINT RESIST STRIP ETCH C1 BARE FIND MINIMUM OXIDE THICKNESS TO MASK BORON DIFFUSION 8000 Å . V/I= V/I= V/I= V/I= V/I= . . . BARE SILICON WITH SPIN-ON DOPANT Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 XXXX EMCR201 PMOS page-21 Metal Gate PMOS Process GROOVE and STAIN C2, FIND Xj1 AFTER PRE-DEPOSIT Groove Xj = (N * M) / D D M N After Stain Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-22 Metal Gate PMOS Process DE01 - FOUR POINT PROBE C1, C2, C3, C4 FIND SHEET RESISTANCE OF DIFFUSION AFTER PREDEPOSIT I V V r s ohms/square I ln 2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-23 Metal Gate PMOS Process FIELD OXIDE GROWTH (5000 Å) Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 48 min. in wet O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2 Slightly Thicker Oxide Over Diffusion Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-24 Metal Gate PMOS Process After Field (Thick) Oxide Growth Oxide over lightly doped silicon Oxide over heavily doped silicon Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-25 Metal Gate PMOS Process Photolithography, Mask Level 2 (define thin OXIDE regions) opaque clear Shadow Ultra-Violet Radiation Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-26 Metal Gate PMOS Process Active (thin oxide) Area Etch and resist strip Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-27 Metal Gate PMOS Process After Patterning/Etching Masking SiO2 (before Thin Gate SiO2 Growth) Note that text has been added to the design to label devices, pads etc. Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-28 Metal Gate PMOS Process OXIDE ETCH C3 and C4 BARE These wafers are used to find the intermediate junction depths and sheet resistances as we go through the process. Note that Xj2 is deeper than Xj1. Xj2 rs2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-29 Metal Gate PMOS Process GROOVE and STAIN and 4PT PROBE C3 Groove Xj = (N * M) / D D M N After Stain I V V r s ohms/square I ln 2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-30 Metal Gate PMOS Process ASH RESIST, CLEAN, GROW GATE OXIDE - 700 Å SiO2 Push at 900 C in N2 Ramp to 1100 C in dry O2 Start Soak at 1090 C Time = 50 min. in dry O2 Ramp down to 1000 C in N2 Pull at 1000 C in N2 700 Å SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-31 Metal Gate PMOS Process After Thin Gate Oxide Growth (dark brown areas) Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-32 Metal Gate PMOS Process PHOTOLITHOGRAPHY MASK LEVEL 3 - CONTACT CUT opaque clear Shadow Shadow Shadow Shadow SiO2 SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-33 Metal Gate PMOS Process OXIDE ETCH C4 BARE Xj3 rs3 Xj3 is deeper than Xj2! Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-34 Metal Gate PMOS Process GROOVE and STAIN and 4PT PROBE C4 Groove Xj = (N * M) / D D M N After Stain I V V r s ohms/square I ln 2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-35 Metal Gate PMOS Process CONTACT CUT ETCH SiO2 SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-36 Metal Gate PMOS Process Photomicrograph after contact cut etch and resist strip Contact Thin Oxide ~700 Å Thick Oxide Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-37 Metal Gate PMOS Process ASH RESIST, RCA CLEAN and SPUTTER ALUMINUM rs aluminum Xal SiO2 SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-38 Metal Gate PMOS Process After Aluminum Deposition Note how reflective the aluminum is Aluminum everywhere, Everything short circuited Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-39 Metal Gate PMOS Process PHOTOLITHOGRAPHY LEVEL 4 - METAL opaque clear v Shadow SiO2 SiO2 Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-40 Metal Gate PMOS Process ETCH ALUMINUM (40°C Phosphoric Acid) photoresist Aluminum SiO2 SiO2 P-type P-type Silicon Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-41 Metal Gate PMOS Process ASH RESIST Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-42 Metal Gate PMOS Process After Aluminum Etch and Resist Strip Electrical Probe Pads are now visible, pad numbers were done in the diffusion layer Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-43 Metal Gate PMOS Process SINTER – Improves Contacts and Threshold Voltage Before Sinter After Sinter Reduce Contact Resistance Native Oxide Hydrogen, neutral region Oxygen SiO2 + charge region Interface silicon atom that has Nothing to bond to (missing electron) Silicon Crystal Reduce Surface States Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 EMCR201 PMOS page-44 Metal Gate PMOS Process Electrical TEST X D CROSS-OVER S D Aluminum G SOURCE DRAIN GATE SiO2 SiO2 Silicon Rochester Institute of Technology - MicroE © REP/LFF 3/10/2016 PMOS TRANSISTOR EMCR201 PMOS page-45
