Architecture By: Xinya (Leah) Zhao Abdulahi Abu Logo Source: http://gamez-gear.com/ds/images/logos/playstation3logo%20%281%29.gif Outline • Evolution of Game Consoles and Gaming Industry • PlayStation 3 Architecture • High Level Architecture Comparison • What's next? Evolution of Game Consoles 1983 1972 Supported high-resolution Based around vector sprites and tiled display, not analog backgrounds with more video colors Ex: Odyssey 200 Ex: Nintendo Entertainment System • • • 1st Gen • 2nd Gen 3rd Gen 4th Gen 1994 More polygon processing Use of discs that contained far more information and cheaper More onscreen colors Ex: PlayStation • • • • 5th Gen 6th Gen 2005 Support of new disc formats: Blu-ray Disc, HD DVD Wireless controller support Motion as input and IR tracking Ex: PlayStation 3 • • • • 7th Gen 1988 1999 Increased storage space PC-like architecture 1976 for multimedia-based DVD for game media Contained a programmable games Emergency of online microprocessor gaming. 32X: added polygonCartridges only needed a singleprocessing Implementation of flash ROM chip to store microprocessorEx: Mega Drive/Genesis and hard drive storage instructions Ex: PlayStation 2 Ex: Atari 2600 • • • • • • • • • • • 8th Gen 2011 Support high definition graphics up to 1080p Controller with built-in touchscreen EX: Wii U • • • Industry Development Gamers Developers High definition graphics compatibility Good hardware •Affordable • •High definition graphics •Backwards compatibility • Evolution of Gaming Industry Business Model Roll out cutting-edge hardware and couple it with compelling games and novel new ways to play. New Game Plan!! •Integration of social media •Extend life of console by offering add-ons PlayStation 3 Development • Released in 2006 o o • Sony Cut 70% production cost in 2009 o o o • Cost $805.85 for the 20 GB model and $840.35 for the 60 GB For the first 2.5 years Sony lost $306 or $241 per console Shrinking technology Removing the Emotion Engine Blu-ray Disc diodes are cheaper to manufacture Current Cell CPU at 65nm, GPU at 45nm PlayStation 3 Sales Region Units sold First available Canada 1.5 million as of October 6, 2010 November 17, 2006 Europe 16 million as of August 17, 2010 March 23, 2007 Japan 6,341,950 as of April 1, 2011 November 11, 2006 United Kingdom 3 million as of January 26, 2010 March 23, 2007 United States 13.5 million as of November 11, 2010 November 17, 2006 Worldwide 55.5 million as of September 30, 2011 November 11, 2006 Source: Wikipedia PlayStation 3 Specs • CPU: Cell Processor • GPU: RSX at 550MHz • Full HD support (up to to 1080P) • • 256MB XDR Main RAM @3.2GHz 256MB GDDR3 VRAM @700MHz • Memory: • 10/100/1000Base-T Ethernet Adapter • Wi-Fi: IEEE 802.11 b/g PlayStation 3 Architecture Overview Source : http://www.cg.tuwien.ac.at/events/EG06/gmgfiles/perthuis-talkeg2006.ppt Architecture Outline • • • CPU Architecture o Power Processing Element (PPE) o Synergistic Processing Element (SPE) RSX GPU Architecture Memory Architecture o XDR DRAM o XIO CPU Architecture • PowerPC-base Core @3.2GHz o 512KB L2 cache o VMX (aka Altivec) ISA support • 7 x SPE @3.2GHz o 7 x 128b 128 SIMD GPRs o 7 x 256KB SRAM for SPE o 1 of 8 SPEs reserved for redundancy total floating point performance: 218 GFLOPS o 1 VMX vector unit(Altivec) per SPE CPU Architecture Source:http://www.ibm.com/developerworks/power/library/pa-cellperf/ POWER Processing Element (PPE) • Handles most of the work load of all the • • • • processors Dual-issue, in-order processor with dualthread support (4 fetch, 2 issue) 2 instructions issued per cycle 64kB L1 (instruction + Data), 512kB L2 Cache Includes VMX (aka Altivec) ISA POWER Processing Element (PPE) • • • • Direct Memory Access to and from main memory Super-scalar with deep 2-way pipeline Delayed-execution pipeline Limited out-of-order execution of load instructions Source:http://www.unixer.de/publications/img/22c3_slides.pdf PPE Pipeline Source:http://www.ibm.com/developerworks/power/library/pa-cellperf/ Synergistic Processing Elements (SPE's) • Clocked at 3.2 GHz (2506 GFLOPS of single precision perfamance theoretica) Based on the pervasively data parallel computing (PDPC) architecture. (wide datapaths throughput Compute Engine with SIMD support 256Kb embedded SRAM for intruction and data ("Local storage") . • • • SPE Block diagram Source:http://www.ibm.com/developerworks/power/library/pacellperf/ SPE continued... • Can Compute 16 8-bit integers, 8 16-bit • • integers, 4 32-bit integers or 4 single precision floating-point numbers in one cycle Usually used for small programs (i.e threads) Floating point and fixed point units are on even pipeline, rest on odd pipeline RSX GPU • Developed joinly by • • NVidia and Sony specifically by the PS3 Same Architecture as GeForce 7800 GTX Rendering to both local and system memory Source:http://www.spuify.co.uk/?p=64 5 RSX GPU • Over 300 million transistors on 8 layer 90nm • • • process. (currently on 40nm) Connected to the cell by 35GB/s link (20GB/s Write, 15GB/s read) Multi-way programmable parallel floating point shader pipeline Made of 24 parrallel pixel-shader ALU pipes and 8 parallel vertex pipelines at 550MHz RSX GPU • • • 5 ALU operations per pipeline, per cycle (2 vectors, 2 scalar/dual/coissue and fog ALU, 1 Texture ALU) for pixel shaders 27 floating-point operations per pipeline, per cycle for pixel shaders 2 ALU operations per pipeline, per cycle (1 vector4 and 1 scalar, dual issue) and 10 floating-point operations per pipeline, per cycle for parallel vertex pipelines RSX GPU • • • 256K DDR3 RAM at 700 MHZ 128-bit memory bus width and has a read and write bandwidth of 22.4 GB/s FlexIO provides bandwidth of 62.4 GB/s (36.4 GB/s outbound, 26 GB/s inbound) at 2.6 GHz Source:http://www.spuify.co.uk/?p=645 PS3 Memory Architecture Rambus XDR Memory Architecture •3 Primary Semiconductor Components o o o XDR DRAM XIO XMC Purpose To be effective in small, high bandwidth consumer systems, high-performance memory applications, and high-end GPUs. • Source : http://www.rambus.com/us/technology/solutions/xdr/index.html XDR DRAM Extreme Data Rate Dynamic Random Access Memory CMOS DRAM organized as 32M words by 16bits Bi-directional Differential RSL (DRSL) • • Source: http://www.rambus.com/us/technology/solutions/xdr/xdr_dram.html • • • • • Eight banks: bank-interleaved transactions at full bandwidth Capable of sustained data transfers of 8000/6400/4800 MB/s Dynamic request scheduling Early-read-write support Zero overhead refresh XIO Controller IO Cell • High performance, low-latency controller • • interface. Can support bandwidths of up to 28.8 GB/s Composition o o o o One or two 12-bit Request bus block (RQ) One control block (CTL) A variable number of 8 or 9-bit data blocks (DQ) Source: http://www.rambus.com/us/technology/solutions/xdr/xdr_controller.html XDR Memory Controller (XMC) • Configurable Soft macro reference design • Flexible with integration o Direct integration o Use as a reference design • Flexible to accommodate a wide variety of expected DRAM configurations • Supports Dynamic Point-to-Point I/O Architecture Flex I/O Interface Unidirectional 8-bit wide point-to-point path (12 lanes) o 5 inbound and 7 outbound •Peak bandwidth 62.4GB/s (36.4 GB/s outbound, 26GB/s inbound) at 2.6 GHz •Can be clocked independently •4 inbound and 4 outbound lanes support memory coherency IO: BluRay, HDD, USB, Memory Cards, GigaBit Ethernet • High Level Architecture Comparison PC and Multi-Core PC • • Memory is cached As long as synchronization primitive are used to avoid race conditions, the system takes care of getting the right data Wii • • Two types of memory and both accessible by CPU and GPU A portion of the L1 cache could be locked and explicitly managed by DMA transfers Source: http://beautifulpixels.blogspot.com/2008/08/multi-platform-multi-core-architecture.html High Level Architecture Comparison (Cont.) Xbox 360 • • • PS3 Multiple hardware threads per core Single memory use for CPU and GPU GPU is the memory controller and has access to L2 • • • Cell processor Series of co-processors named SPUs that have dedicated memory for instructions and data Why floodgate was built Source: http://beautifulpixels.blogspot.com/2008/08/multi-platform-multi-core-architecture.html What's Next? • PS3>XBox360 • Sony wants to lead the next generation o • • PS3 was last to be release and is behind in sales Market is Very Different o Integration with other technologies such social media o Customers want more than a gaming system o Moving away from traditional controller PS4 soon? Questions?