RSR ELECTRONICS
PLDT-2 USER'S MANUAL
ver 1.08
1.0 INTRODUCTION
The RSR Electronics PLDT-2 digital logic trainer board, shown in Figure 1, has been designed as a
"target board" for students and other users to design, implement, and test digital circuits using a modern
programmable device and industry-standard design tools. It is built around the ALTERA corporation
EPM7128SLC84 CPLD device in an 84-pin PLCC package.
While the fundamental principles of digital logic design have remained constant, the technology in which
digital designs are implemented has changed rapidly. From transistors in the 1950s to small-scale
integrated circuits (ICs) in the 1960s to large-scale ICs such as microprocessors in the 1970s, to the
sophisticated programmable ICs of today
Early digital IC devices, such as 7400 series TTL, were initially built as standard building-blocks that had
to be interconnected by copper traces on a circuit board. By the 1980s, the blocks could be mounted on
one chip, and the interconnection done by "burning" a design into it. Those were the early programmable
logic devices (PALs, PLAs, PLDs). They were one-time programmable (OTP), and required an
electronic "box" called a device programmer to do the "burning". Later came devices that could be erased
electrically and reprogrammed.
Today, ICs such as the venerable 7400 TTL chip are almost obsolete. Modern digital designs use largescale programmable ICs such as field-programmable gate arrays (FPGAs) and complex programmable
logic devices (CPLDs). Internally, FPGAs implement logic functions using look-up tables in memory
blocks while CPLDs use sum-of-product terms configured from arrays of gates. Both FPGAs and CPLDs
also contain flip-flops.
To program such devices, special computer-aided design (CAD) software is required that allows the user
to enter a digital design on a PC, check it for validity, simulate its performance, and then download it into
the target chip. Depending on the CAD package being used, a design can be entered using schematic
capture software to draw a diagram showing interconnected gate symbols. Or a design may be entered
using a text editor to create a file containing a set of Boolean equations written in a hardware description
language (HDL). A common HDL is ABEL (Advanced Boolean Expression Language). Either way, the
CAD software compiles the design into the low-level commands needed to configure the device.
The EPM7128SLC84 CPLD contains 128 macrocells with 2500 usable gates arranged in 8 logic array
blocks as shown in Figure 2. The chip is available in speeds from 6 ns to 15 ns delay time pin-to-pin.
Outputs can drive 25 mA (max) loads.
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PLDT-2 USER'S MANUAL
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Figure 1
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PLDT-2 USER'S MANUAL
ver 1.08
Figure 2
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PLDT-2 USER'S MANUAL
ver 1.08
2.0 GENERAL DESCRIPTION
The EPM7128SLC84 used in the PLDT-2 digital logic trainer is in-service programmable (ISP). ISP
means that the CPLD can be erased and reprogrammed while it is in a circuit, so a separate deviceprogrammer box is not required. The PLDT-2 is powered by a wall-mounted power module which comes
with the trainer.
The PLDT-2 connects to the parallel port of a personal computer via a standard 25-wire cable with DB25
connectors at both ends. The cable is part of the package when purchasing the PLDT-2. Standard design
software, such as the ALTERA MAX+PLUS Software, can be used with the PLDT-2.
Once commands are down-loaded from the PC to the CPLD, the cable may be disconnected; the CPLD
"remembers" the design. Or the cable can be left attached for rapid reconfiguration of the logic design.
Either way, the digital circuit programmed into the CPLD can be tested using the on-board switches and
LEDs of the PLDT-2 board. Almost all pins of the CPLD are brought out via four dual-row receptacles
(HD4, HD5, HD6, HD7) surrounding the CPLD socket. CPLD pins, together with power, ground, and
other signals, are brought out via pin-headers for the easy attachment of ribbon cables, making the full
power of the EPM7128SLC84 available for advanced designs. A 60-pin header (P2) allows the PLDT-2
to be connected to a Motorola M68HC11EVBU/D micro-controller board.
The 16 toggle switches and 16 LEDs of the PLDT-2 can be accessed via pin jacks to allow connection of
external circuits. Thus external circuits built with small scale ICs, such as 7400 series TTL or 4000 series
CMOS logic, can also be used. Also on board the PLDT-2 are two N.O. momentary push-button switches,
a 4 MHz clock oscillator, and dual 7-segment displays.
3.0 DETAILED DESCRIPTION (refer to Figure 1)
3.1 POWER
Power is supplied to the PLDT-2 from a wall-mounted 9 Volt DC power supply (or a 7-9 Volt DC bench
supply) connected to J14 (see detail E). Note that the center pin of J14 is positive. The input voltage is
regulated down to 5 Volts by an on-board 7805 regulator (U2). Note that 5 Volts and ground are brought
out on screw terminals next to J14 (detail G).
3.2 TOGGLE SWITCHES S1 & S2
Sixteen toggle switches, numbered 1 to 8, are provided by two DIP mounted switch modules, S1 and S 2
(detail D). When a toggle switch is in the position marked H (high), the switch pole is connected via a
pull-up resistor to +5 Volts. In the position marked L (low), the switch pole is connected to ground.
The eight poles from module S1 are wired to pin-jack strips J1 and J2, and to pins on one side of jumper
strip HD1 (see detail M). The opposite side of HD1 is connected to CPLD pins as shown in Table 1. When
no jumpers are installed on HD1, the CPLD is isolated from the switches.
The eight poles from S2 are wired to pin-jack strips J6 and J5. Note that pin-jack strips J2, J5, J4, and J8 are
positioned for easy connection to an external solderless breadboard.
*** WARNING ***
After testing the board, remove all eight jumpers from HD1 before programming your own
design into the CPLD. FAILURE TO DO SO WILL CAUSE PERMANENT DAMAGE TO
THE CPLD CHIP:
When using the SK1 Dip-Switch as inputs in your design, DO NOT program the associated CPLD to be
Highs (1s). Those pins are 33, 34, 35, 36, 37, 39, 40, and 41.
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PLDT-2 USER'S MANUAL
SWITCH
S1
CPLD
PIN
LEDs
1-8
ver 1.08
CPLD
PIN
1
34
1
44
2
33
2
45
3
36
3
46
4
35
4
48
5
37
5
49
6
40
6
50
7
39
7
51
8
41
8
52
INSTALL JUMPERS TO CONNECT
TABLE 1
3.3 DEBOUNCED TOGGLE SWITCHES S5
Four debounced toggle switches are provided by switch module S5 (see detail D). The outputs of the
switches are available at pin-jacks on J12. The four LEDs next to J12 indicate switch status. When a switch
is "on", it provides a high TTL level to J 12 and the LED lights. When a switch is off, it places a TTL low
on J12 and the LED is off.
3.4 MOMENTARY SWITCHES S3 & S4
Two momentary push-button switches, S3 and S4 (detail C), can be used to apply manually generated
input pulses to the CPLD. Both switches have pull-up resistors and are normally open (NO), so they will
produce a pulse with a falling (+5 V to 0) edge. Neither switch is debounced. The output of S 3 is on pin
jack J9 while the output of S4 is on pin jack J10.
3.5 ON-BOARD OSCILLATOR & CLOCK
The PLDT-2 has an on-board 4 MHz oscillator module. The output of this module can be connected to
pin 83 of the CPLD by placing a shorting bar across jumper J 1 (detail B). The clock signal is also
accessible via single pin socket “CLK”.
3.6 LEDs
The PLDT-2 has sixteen LEDs, numbered 1 to 16 (details J, K), connected through resistor packs to pin
jacks. LEDs 1 to 8 are connected to pin-jack strips J3 and J4 while LEDs 9 to 16 are connected to pin-jack
strips J7 and J8. LEDs 1 to 8 are also connected to one side of jumper-strip HD2. The opposite side of
HD2 is connected to CPLD pins as shown in Table 1. When no jumpers are installed on HD2, the CPLD
is isolated from the LEDs.
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PLDT-2 USER'S MANUAL
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3.7 THE 7-SEGMENT DISPLAY
A common-anode dual 7-segment display (detail F) is connected through current-limiting resistors to the
CPLD pins as shown in Table 2 below.
7- SEGMENT DISPLAY
(see detail H on Figure 1)
DISPLAY 1 CPLD
DISPLAY 2
SEGMENTS
PIN
SEGMENTS
A
58
A
B
60
B
C
61
C
D
63
D
E
64
E
F
65
F
G
67
G
DP
68
DP
CPLD
PIN
69
70
73
74
76
75
77
79
TABLE 2
In order to deactivate Dual 7-Segment Display cut the trace under the jumper JP3 (copper side of PCB).
Display can be activated again by placing the shorting bar across the jumper JP3.
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PLDT-2 USER'S MANUAL
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4.0 RIBBON CABLE CONNECTORS
Most of the CPLD pins are brought out to ribbon cable connectors P1, P2, and P3. The pin-outs are given
in the tables below. Power (+5 Volts) and ground (GND) are also brought out.
4.1 CONNECTOR P1 (DETAIL Q)
P1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CPLD
PIN
GND
+5 V
CLK
1
2
4
5
6
8
9
10
11
12
15
16
17
18
80
+5 V
GND
TABLE 3
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PLDT-2 USER'S MANUAL
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4.2 CONNECTOR P2 (DETAIL H)
P2
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CONNECTION
GND
N/C
N/C
HD3 PIN1
HD3 PIN2
HD3 PIN3
N/C
N/C
S1 - 8
S1 - 7
S1 - 6
S1 - 5
S1 - 4
S1 - 3
S1 - 2
S1 - 1
HD3 PIN4
HD3 PIN5
HD3 PIN6
N/C
N/C
HD3 PIN7
HD3 PIN8
HD3 PIN9
HD3 PIN10
N/C
HD3 PIN11
HD3 PIN12
HD3 PIN13
HD3 PIN14
P2
PIN
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
CONNECTION
HD3 PIN15
HD3 PIN16
HD3 PIN17
HD3 PIN18
LED 1
LED 2
LED 3
LED 4
LED 5
LED 6
LED 7
LED 8
HD3 PIN19
HD3 PIN20
HD3 PIN21
HD3 PIN22
HD3 PIN23
HD3 PIN24
HD3 PIN25
HD3 PIN26
HD3 PIN27
HD3 PIN28
N/C
N/C
N/C
N/C
+5 V
+5 V
GND
GND
TABLE 4
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PLDT-2 USER'S MANUAL
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4.3 CONNECTOR P3 (detail N)
P3
PIN
CPLD
PIN
P3
PIN
CPLD
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
UNREG DC
GND
+5 V
GND
+5 V
GND
N/C
N/C
N/C
N/C
N/C
1
84
2
4
5
6
8
9
10
11
12
15
16
17
18
20
21
22
24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
25
27
28
29
30
31
33
34
35
36
37
39
40
41
44
45
46
48
49
50
51
52
54
55
56
57
+5 V
GND
+5 V
GND
TABLE 5
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RSR ELECTRONICS
PLDT-2 USER'S MANUAL
ver 1.08
5.0 EXPERIMENTS
The switches and LEDs of the PLDT-2 trainer board can be used with external circuitry. A simple TTL
experiment is given in 5.1 below. Three simple PLD experiments are given in 5.2, 5.3, and 5.4 below.
5.1 EXPERIMENT: GATE CIRCUIT USING 74LS00 TTL CHIP
OBJECTIVE
To examine a simple combinatorial circuit built with a TTL chip. The switches of the PLDT-2 will be
used to generate input while the LEDs of the PLDT-2 will be used to show output.
PARTS
1. Solderless Breadboard
2. 74LS00 TTL Quad-2 Integrated Circuit
3. PLDT-2 with power module
PROCEDURE
A) Use Boolean Algebra to get an equation for Q from the following circuit:
Q = __________________________________________________
B) Using the equation, fill in the truth table on the next page (just fill in the column labeled Q).
C) Build the circuit. (NOTE: solderless breadboard & PLDT-2 must have common +5 & GND)
Check off each step as you complete it.
___ 1.
___ 2.
___ 3.
___ 4.
___ 5.
___ 6.
___ 7.
___ 8.
___ 9.
___ 10.
Insert the 74LS00 into the solderless breadboard.
Connect a wire from pin 7 of the 74LS00 to GND.
Connect a wire from pin 14 of the 74LS00 to +5V.
Connect a wire from pin 1 of the 74LS00 to S1 - 1.
Connect a wire from pin 2 of the 74LS00 to S1 - 2.
Connect a wire from pin 3 to pin 4 of the 74LS00.
Connect a wire from pin 13 of the 74LS00 to S1 - 3.
Connect a wire from pin 12 of the 74LS00 to S1 - 4.
Connect a wire from pin 11 to pin 5 of the 74LS00.
Connect a wire from pin 6 of the 74LS00 to LED 1.
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PLDT-2 USER'S MANUAL
ver 1.08
PROCEDURE (continued)
Connect the power module to the PLDT-2 and plug the power module into a 110 VAC outlet.
Assuming a switch at H is a logic 1 and a lit LED is a logic 1, fill in the column labeled LED on the truth
table on the next page.
SW 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SW 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SW 3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SW 4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
11
Q
LED
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PLDT-2 USER'S MANUAL
ver 1.08
6.2 CPLD EXPERIMENT: BASIC GATES
The objective of this experiment is to gain familiarity with the use of Altera Max+Plus software by
designing and implementing a simple gate circuit.
AND gates and OR gates are two fundamental building blocks of digital circuits. Both AND and OR
gates can have two or more inputs, but only one output. The input / output behavior of a gate is shown by
a truth table and is written as a Boolean equation as shown below.
Gate Characteristics:
The AND Gate
Symbol
Boolean Equation
Truth Table
A
0
0
1
1
B
0
1
0
1
X
0
0
0
1
The OR Gate
Symbol
Boolean Equation
Truth Table
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
PROCEDURE:
1.
Create a new directory on your C: drive (call it ALLABS, or you name it). You will save all your
experiment files in this directory since they will be too big for a floppy.
2.
Start the Software by clicking on the following: Start  Programs  Altera Max+Plus II..
3.
Open the File Project and click on Name
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4. When the Project Name window
appears, type AND_OR3 in the Project
Name editor box as your project name.
In the Directory edit box, browse to get
Allabs
5. The new project is now
created and you should see a
window like this:
6 Open File New and select
Graphic Editor File, click OK .
Open File click on Save As
And type the name AND_OR3
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7. Open Symbol and click on enter symbol.
In symbol libraries window double click
on C:\maxplus2\max2lib\prim
In symbol files window click on
And3 then click on OK button.
The symbol of 3 input AND gate will be
placed in graphics window.
Using this same procedure place symbol
of 3 input OR gate
8.Using this same technique place 6
inputs and two outputs.
Connect each inputs and outputs to
AND and OR gates.
9.Each input has to have unique name .
Place the mouse cursor over input
symbol and single click the right
mouse button, choose Edit Pin Name
For inputs use following names:
Gate AND : A,B,C
Gate OR : D,E,F
For inputs
Gate AND : X
Gate OR : Y
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10.
PLDT-2 USER'S MANUAL
ver 1.08
Each input and output must be assigned to the
Altera device and to a specific pin number. To
begin, place the mouse cursor over an input
symbol and single click the right mouse button.
Choose Assign / Pin / Location / Chip
11. Select the Assign Device button and select
the Device Family MAX7000S. In Devices
window, selectEPM7128SLE84-6
12.
.For driving the inputs we will use switches
S1 and for monitoring the outputs :
LED1and LED2.
Input
A 34
B 33
C 36
D 35
E 37
F 40
Pin
X
Y
Output Pin
44
45
Type the Node Name (A, B, X,Y, etc), select
Pin Number (44,45, etc) and Pin Type (Input
or Output), and click on the Add button.
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13.
PLDT-2 USER'S MANUAL
ver 1.08
After finishing the process of assigning pin numbers, schematic should look like:
14. Select Max+Plus II and
click on Compiler. In the
Compiler window, click on
START button. After the
compilation is finished,
click on OK button . Then
close the Compiler window
115.
16.
Select (open) Max+Plus II /
Programmer. Select Options /
Hardware Setup. In the hardware type
window select Byte Blaster. In
Parallel Port, select LPT1 or LPT2 as
appropriate. (Note: in the DeVry Lab,
LPT1 is believed to be the correct
choice)
Click on the Program button.
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17.
PLDT-2 USER'S MANUAL
Run the program on your PLDT-2 board and fill in the following truth-tables by using the
switches for inputs and the LEDs for output.
Truth-Table for 3-Input AND Gate
A
0
0
0
0
1
1
1
1
ver 1.08
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Truth-Table for 3-Input OR Gate
X=ABC
A
0
0
0
0
1
1
1
1
17
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y=A+B+C
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PLDT-2 USER'S MANUAL
6.3 CPLD EXPERIMENT: ASYNCHRONOUS (RIPPLE) COUNTER
ver 1.08
The objective of this experiment is to gain familiarity with the use of Altera software by designing and
implementing an asynchronous counter using JK flip-flops (FFs).
In an asynchronous counter, the output of each FF serves as the CLK input signal for the next FF. The
name asynchronous comes from the fact that all the FFs do not change states at the same time. After each
clock, change "ripples down" the chain of FFs, which is why they also are called ripple counters.
The clock pulses applied to CLKIN are generated by the PULSE switch.
C
B
A
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18
NUMBER OF
PULSES
0
1
2
3
4
5
6
7
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PLDT-2 USER'S MANUAL
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PROCEDURE:
Using this same technique as described in previous experiment create new project ASY_COU
Give this same name for graphics file. Create the circuit based on the picture below:
For CLK_IN use pin 2
For RESET use pin 1
For A,B,C use accordingly 44,45,46
TESTING :
Using jumper wires connect pin 2 block HD4 to any switch S5 This switch will simulate the clock
Using jumper wire connect the pin 1 block HD4 to any free switch S5, This switch will simulate RESET.
LED1,2 and 3 will monitor outputs A,B and C.
Fill out:
Truth-Table for 3-bit Asynchronous Counter
LED
1
LED
2
LED
3
19
PULSE
SWITCH
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