97/59.203 P.N./Alb MASSEY UNIVERSITY PALMERSTON NORTH and ALBANY CAMPUS EXAMINATION FOR 59.203 COMPUTER SYSTEMS Semester 2 - 1997 Time Allowed: TWO (2) hours ANSWER ALL QUESTIONS. 1. (a) A vending machine dispenses either tea or coffee. The controller for the machine has four input signals: COIN the user has paid. TEA_REQ the user has requested tea. COFFEE_REQ the user has requested coffee. DRINK_DISPENSED the drink is ready two output signals (both single pulses): DISP_TEA start dispensing a cup of tea DISP_COFFEE start dispensing a cup of coffee and follows these rules: Wait for a coin to be inserted. Wait for either TEA_REQ or COFFEE_REQ. Assert the relevant signal (DISP_TEA or DISP_COFFEE) for one cycle. Wait until DRINK_DISPENSED is true. Repeat. For the controller of the above vending machine: (i) Draw an ASM chart. [3 marks] (ii) Give Boolean expressions for the states. [2 marks] (iii) Design a circuit, including the output signals [5 marks] 1 97/59.203 P.N./Alb Question 1 continued over... Question 1 continued Turn over to p.2, etc... The Pico-computer Architecture WEMEM OEMEM Bus OEPC Tristate buffer OECONST Tristate buffer Program INCPC counter LDPC OEACC Tristate buffer LDACC Accumulator const mux 1 2. Memory Input Port CO/C1 0 zero detect EQZ Arithmetic Logic Unit xor invertor LDABR A Buffer Register (b) OEPORT Tristate buffer sub LDMAR Memory Address Register Describe how machine instructions are implemented on the Pico-computer, using an example, eg the LDA operand instruction, to illustrate your answer. [5 marks] Information about the 8051 instruction set can be found in tables at the end of the paper. (a) Describe 4 different ways that parameters may be passed to subroutines. [4 marks] (b) Write a program in 8051 assembler, that will output a string of characters (terminated with a NUL character) to an LCD display. You may assume that the display has already been initialised. The address of the first character to be output is held in the R1 register. To display a character on the LCD: Set bit 5 of Port 3 (P3.5) then delay for at least 100 cycles Copy the character into Port 1 (P1) then delay for at least 100 cycles Clear bit 5 of Port 3 (P3.5) then delay for at least 100 cycles [6 marks] 2 97/59.203 P.N./Alb (c) Describe how interrupts are handled by the 8051 microcontroller architecture. [5 marks] Turn over to p.3, etc... 3. 4. (a) Describe the modulation technique used to transmit data, at bit rates of 4800 and above, over telephone lines. [5 marks] (b) Describe two different types of error that can be detected by a receiving UART during asynchronous communications between two users. [2 marks] (c) Errors in transmission can be detected and corrected if a suitable encoding scheme is used. 11 bit Hamming codes are one way of protecting 7 bit ASCII, so that single bit errors can be corrected. If the following code is received 11100000110, what was the transmitted character (in binary)? [3 marks] (d) One method of allocating bit patterns to characters is by Huffman encoding. Describe how this is performed, and its advantages/disadvantages over ASCII. [5 marks] (a) What is the purpose of the BIOS? Illustrate your answer with examples of some of the functions it performs. [7 marks] (b) Describe the implementation of the DOS File System. [8 marks] +++++++++++ 3 97/59.203 P.N./Alb AT89C2051 Reference Program Memory: Data Memory: 07FFH 7FH 2FH Bit-addressable space (0-7F) Serial Port 0023H Interrupt Locations Timer 1 001BH 20H Ext Int 1 0013H Timer 0 000BH 11 { 18H Bank Select 10 { 10H bits in 01 { 08H PSW 00 { 00H Ext Int 0 0003H RESET 0000H 1FH 17H 4 banks of registers 0FH R0 - R7 07H Reset value of Stack Pointer Program Counter: 16 bit register restricted to 0000H -> 07FFH Special Function Registers (SFR) Space: Byte Address 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 98H 99H A8H B0H B8H D0H E0H F0H | | | | | | | | | | | | | | | | | | | | Name SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF IE P3 IP PSW ACC B | | | | | | | | | | | | | | | | | | | | Description Stack Pointer Low byte of DPTR High byte of DPTR Power control Timer control Timer mode control Timer 0 low byte Timer 1 low byte Timer 0 high byte Timer 1 high byte Parallel port 1 Serial control Serial buffer Interrupt Enable Parallel port 3 Interrupt priority Program Status Word Accumulator B register Interrupt control register IE: EA ES,ETx Bits not bit addressable not bit addressable not bit addressable not bit addressable TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0 not bit addressable not bit addressable not bit addressable not bit addressable not bit addressable P1.7 -> P1.0 SM0-SM1-SM2-REN-TB8-RB8-TI -RI not bit addressable EA -ES -ET1-EX1-ET0-EX0 P3.7 -> P3.0 -PS -PT1-PX1-PT0-PX0 CY -AC -F0 -RS1-RS0-OV -F1 -P ACC.7 -> ACC.0 B.7 -> B.0 Global bit to enable interrupts Serial interrupt (either RI or TI), Clock interrupt on overflow Power control register PCON: | | | | | | | | | | | | | | | | | | | | set to 2 will stop the processor 4 97/59.203 P.N./Alb Timer control and mode registers - 2 timers, 0 and 1 TCON: TF0/TF1 TR0/TR1 TMOD: mode1-mode0 mode = 0 mode = 1 mode = 2 Timer overflow flag timers 0/1 Timer run control bit. Set by software to switch timer ON 2 4-bit nibbles. Timer 1 high order nibble, Timer 0 low order. 13 bit timer 16 bit timer 8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial i/o as bit rate (*32). 0FDH in THx gives 9600bps for 11.059Mhz clock Serial control register SCON: SM0-SM1-SM2-REN-TB8-RB8 should be set to 010100 for normal operation TI set when the character has been transmitted RI set when a character is received Addressing Modes: Rn direct @Ri #data #data16 addr11 addr16 rel bit Arithmetic ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA = Register R0 - R7 of the currently selected register bank. = 8-bit internal data location's address. This could be an internal Data RAM location (0-127) or a SFR. = 8-bit internal Data RAM location addressed indirectly through R0 or R1. = 8-bit constant included in instruction. = 16-bit constant included in instruction. = 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of Program Memory as the first byte of the following instruction. = 16-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 2K byte Program Memory address space. = Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction. = Direct addressed bit in internal Data RAM or SFR. A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A,Rn A,direct A,@Ri A,#data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A | | | | | | | | | | | | | | | | | | | | | | | | Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Acc. with Carry Add direct byte to Acc. with Carry Add indirect RAM to Acc. with Carry Add immediate data to Acc. / Carry Subtract reg. from Acc. with borrow Sub. direct byte from Acc. / borrow Sub. indirect RAM from Acc./ borrow Sub. imm. data from Acc. / borrow Increment Accumulator Increment register Increment direct byte Increment indirect RAM Decrement Accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A and B Divide A by B Decimal adjust Accumulator 5 | Byte | Cycle | C OV AC | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | X X X | 2 | 1 | X X X | 1 | 1 | | 1 | 1 | | 2 | 1 | | 1 | 1 | | 1 | 1 | | 1 | 1 | | 2 | 1 | | 1 | 1 | | 1 | 2 | | 1 | 4 | 0 X | 1 | 4 | 0 X | 1 | 1 | X 97/59.203 P.N./Alb | | | | | | | | | | | | | | | | | | | | | | | | | AND register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exc-OR register to Accumulator Exc-OR direct byte to Accumulator Exc-OR indirect RAM to Accumulator Exc-OR immediate data to Acc. Exc-OR Accumulator to direct byte Exc-OR imm. data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator left Rotate Acc. left through Carry Rotate Accumulator right Rotate Acc. right through Carry Swap nibbles within the Accumulator | Byte | Cycle | C OV AC | 1 | 1 | | 2 | 1 | | 1 | 1 | | 2 | 1 | | 2 | 1 | | 3 | 2 | | 1 | 1 | | 2 | 1 | | 1 | 1 | | 2 | 1 | | 2 | 1 | | 3 | 2 | | 1 | 1 | | 2 | 2 | | 1 | 1 | | 2 | 1 | | 2 | 1 | | 3 | 2 | | 1 | 1 | | 1 | 1 | | 1 | 1 | | 1 | 1 | X | 1 | 1 | | 1 | 1 | X | 1 | 1 | A,Rn | A,direct | A,@Ri | A,#data | Rn,A | Rn,direct | Rn,#data | direct,A | direct,Rn | direct,direct| direct,@Ri | direct,#data | @Ri,A | @Ri,direct | @Ri,#data | DPTR,#data16 | A,@A+DPTR | A,@A+PC | direct | direct | A,Rn | A,direct | A,@Ri | A,@Ri | | Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct byte Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Load Data Pointer with 16-bit const Move Code byte rel. to DPTR to Acc. Move Code byte rel. to PC to Acc. Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Acc. Exchange indirect RAM with Acc. Exchange low order digit indirect RAM with Accumulator | Byte | Cycle | C OV AC | 1 | 1 | | 2 | 1 | | 1 | 1 | | 2 | 1 | | 1 | 1 | | 2 | 2 | | 2 | 1 | | 2 | 1 | | 2 | 2 | | 3 | 2 | | 2 | 2 | | 3 | 2 | | 1 | 1 | | 2 | 2 | | 2 | 1 | | 3 | 2 | | 1 | 2 | | 1 | 2 | | 2 | 2 | | 2 | 2 | | 1 | 1 | | 2 | 1 | | 1 | 1 | | | | | 1 | 1 | Logical ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC SWAP A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A A A A A A A Data transfer MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC PUSH POP XCH XCH XCH XCHD Constants: Numbers: Characters: Operators: Decimal - 34, Binary - 01110101B, Hexadecimal - 0A8H ‘A’ - ‘Abc’ - ‘A’,00DH,00AH (mixed mode) ()’s + - / * MOD SHR SHL NOT AND OR XOR 6 97/59.203 P.N./Alb | | | | | | | | | | | | | | | | | Clear Carry Clear direct bit Set Carry Set direct bit Complement Carry Complement direct bit AND direct bit to Carry AND complement of dir. bit to Carry OR direct bit to Carry OR complement of dir. bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry not set Jump if direct bit is set Jump if direct bit is not set Jump if dir. bit is set & clear bit | Byte | Cycle | C OV AC | 1 | 1 | 0 | 2 | 1 | | 1 | 1 | 1 | 2 | 1 | | 1 | 1 | X | 2 | 1 | | 2 | 2 | X | 2 | 2 | X | 2 | 2 | X | 2 | 2 | X | 2 | 1 | X | 2 | 2 | | 2 | 2 | | 2 | 2 | | 3 | 2 | | 3 | 2 | | 3 | 2 | | | | | | | | | | | | | A,#data,rel | | Rn,#data,rel | | @Ri,#data,rel| | Rn,rel | direct,rel | | | Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Compare direct byte to Accumulator and jump if not equal Compare immediate data to Accumulator and jump if not equal Compare immediate data to register and jump if not equal Compare immediate data to indirect RAM and jump if not equal Decr. register and jump if not zero Decrement direct byte and jump if not zero No operation | Byte | Cycle | C OV AC | 2 | 2 | | 3 | 2 | | 1 | 2 | | 1 | 2 | | 2 | 2 | | 3 | 2 | | 2 | 2 | | 1 | 2 | | 2 | 2 | | 2 | 2 | | | | | 3 | 2 | X | | | | 3 | 2 | X | | | | 3 | 2 | X | | | | 3 | 2 | X | 2 | 2 | | | | | 3 | 2 | | 1 | 1 | Boolean CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV JC JNC JB JNB JBC C bit C bit C bit C,bit C,/bit C,bit C,/bit C,bit bit,C rel rel bit,rel bit,rel bit,rel Branching ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 SJMP rel JMP @A+DPTR JZ rel JNZ rel CJNE A,direct,rel CJNE CJNE CJNE DJNZ DJNZ NOP Assembler directives and controls $MOD2051 ; Label: TEN ON_FLAG BUFFER RESET SP_BUFFER: IO_MAP: MESS1: EQU BIT DATA CODE DSEG CSEG BSEG DS DBIT DB ORG 10 6 32 0 6 8 ‘Hi’ 56H Include file MOD2051 - defines 2051 symbols Everything following a semicolon is a comment Labels of statements used for program branches. EQUates 10 with the symbol TEN Assigns bit 6 (either data or SFR space) to the symbol ON_FLAG Assigns byte 32 (either data or SFR space) to the symbol BUFFER Assigns 0 in code space to the symbol RESET Makes the data space the currently selected segment Makes the code space the currently selected segment Makes the bit addressable area of data space the cur sel seg. Reserves 6 bytes of storage in data space. DSEG must be active. Reserves 8 bits of storage in bit space. BSEG must be active. Store byte constants in code space. Specify a value for the cur sel segments location counter. 7