CP
0301/159.233
Alb
Internal
MASSEY UNIVERSITY
ALBANY CAMPUS
EXAMINATION FOR 159.233 COMPUTER ARCHITECTURE
Semester 1 - 2003
Time Allowed: THREE (3) hours
ANSWER ALL FOUR QUESTIONS.
Questions 1 and 2 are worth 20 marks
Questions 3 and 4 are worth 15 marks
CALCULATORS PERMITTED
Page 1 of 8
CP
1.
(a)
(b)
0301/159.233
Alb
Internal
Write down the truth table for the XOR function
[2 marks]
Using the following truth table that has three inputs (A, B and C) and one output (D), write
down a Boolean expression for D and implement a circuit using AND gates, OR gates and
INVERTERS.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
D
0
1
1
0
0
1
0
1
[3 marks]
(c)
Show how 4 JK Flip-flops can be connected together to form a synchronous counter.
[5 marks]
(d)
Show how you would alter a single Flip-flop in question (c) to make the device into a
loadable counter. If a signal LOAD is true, then on the clock pulse the Flip-flop is loaded
with the value on the DataIn line. If the signal LOAD is false, then the Flip-flop acts as a
counter.
[5 marks]
(e)
Draw the circuit that allows read and write access to a 4 by 1 bit wide memory.
2.
(a)
[5 marks]
A coffee machine makes cups of tea for staff members. The staff member has the ability to
select whether milk and/or sugar is added. You have been asked to design an ASM to control
the machine. The hardware contains a 4-bit counter that is controlled with two signals ZERO
and INC, which set it to zero and increment it respectively. The counter has two status lines
EQ_THREE and EQ_TEN which are true if the counter is 3 or 10. The ASM reads three switches:
START, SUGAR?, MILK?, and controls the machine with 3 control signals: POUR_TEA,
POUR_SUGAR, POUR_MILK. The clock pulse of the ASM runs at 1 second.
The machine's controller obeys these rules:
Wait until the staff member presses the START button.
Assert the signal POUR_TEA for 10 seconds.
After the coffee has been poured:
if SUGAR? has been pressed assert POUR_SUGAR.
if MILK? has been pressed assert POUR_MILK.
These signals last for 3 seconds and occur at the same time.
Go back to waiting.
Page 2 of 8
CP
0301/159.233
Alb
Internal
Question 2(a), continued over…
Question 2(a), continued…
For the controller of the above coffee machine:
(i)
Draw an ASM chart.
(ii)
Give Boolean expressions for the states.
(iii) Design a circuit, including the output signals
[4 marks]
[2 marks]
[4 marks]
The rest of Question 2 refers to the Pico-computer Architecture shown below
WEMEM
OEMEM
Bus
OEPC
Tristate
buffer
OECONST
Tristate
buffer
Program INCPC
counter LDPC
OEACC
Tristate
buffer
LDACC Accumulator
const
mux
1
OEPORT
Tristate
buffer
Memory
Input Port
CO/C1
0
zero
detect
EQZ
Arithmetic
Logic Unit
LDABR A Buffer
Register
xor
invertor
sub
LDMAR Memory
Address
Register
(b)
How wide is the Bus?
[1 mark]
(c)
When C0 is 0 the output of the const mux is 0, when it is 1 the output is 1.
Show how you can implement this using NO gates.
[1 mark]
(d)
Why is the "A buffer Register" required?
[1 mark]
(e)
Describe the ASM states that are required to implement a new instruction DEC,
which subtracts one from the value in the accumulator.
(f)
[4 marks]
Adding and subtracting 1 from the accumulator are common operations in C (i++/i--),
state in general terms how you can alter the pico-computer hardware to enable these
operations to be performed more quickly.
[3 marks]
Page 3 of 8
CP
0301/159.233
Alb
Internal
3.
Information about the 2051 instruction set can be found in tables at the end of the paper.
(a)
Why is the use of the instruction CLR
(b)
There are 4 different forms of the ADD instruction, give an example of each and draw
diagrams indicating clearly where the values used in the addition are stored.
[4 marks]
(c)
Write a program in 2051 assembler that will control the tea machine described in question
2(a). When the buttons are pressed there will be a logic 1 on P1.0(START), P1.1(SUGAR?) and
P1.2(MILK?). To switch on a control, a logic 1 should be written to P3.0(POUR_TEA),
P3.1(POUR_SUGAR) and P3.2(POUR_MILK). You may assume that a function delay, that will
delay the 2051 for 1 second, has already been written for you, and that Ports 1 and 3 have
been correctly configured.
[10 marks]
4.
(a)
(b)
A
preferable to using the instruction MOV A,#0. [1 mark]
One disadvantage of creating a 4-bit adder from 4 1-bit adders is the slow time that the carry
signal takes to ripple through from one bit to the next. A carry-lookahead adder does not have
this problem. Describe how a carry-lookahead adder works.
[5 marks]
For each of the following addressing modes give an example of an assembler instruction that
uses it, write a description of where the value is found and write an equivalent piece of C
code:
Direct addressing
Immediate addressing
Register indirect addressing
Indexed with displacement addressing
Memory indirect addressing
[10 marks]
++++++++
Page 4 of 8
CP
0301/159.233
Alb
Internal
AT89C2051 Reference
Program Memory:
Data Memory:
07FFH
7FH
2FH
0023H
Serial Port
Timer 1 001BH
Interrupt Ext Int 1
0013H
Locations
Timer 0 000BH
Ext Int 0
0003H
RESET 0000H
20H
11{ 18H
Bank
Select 10{ 10H
bits in
01{ 08H
PSW
00{ 00H
Bit-addressable
space (0-7F)
1FH
17H 4 banks of
registers
0FH R0 - R7
07H
Reset value of
Stack Pointer
Program Counter:
16 bit register restricted to 0000H -> 07FFH
Special Function Registers (SFR) Space:
Byte Address
81H
82H
83H
87H
88H
89H
8AH
8BH
8CH
8DH
90H
98H
99H
A8H
B0H
B8H
D0H
E0H
F0H
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Name
SP
DPL
DPH
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
P1
SCON
SBUF
IE
P3
IP
PSW
ACC
B
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Description
Stack Pointer
Low byte of DPTR
High byte of DPTR
Power control
Timer control
Timer mode control
Timer 0 low byte
Timer 1 low byte
Timer 0 high byte
Timer 1 high byte
Parallel port 1
Serial control
Serial buffer
Interrupt Enable
Parallel port 3
Interrupt priority
Program Status Word
Accumulator
B register
Interrupt control register
IE:
EA
ES,ETx
Bits
not bit addressable
not bit addressable
not bit addressable
not bit addressable
TF1-TR1-TF0-TR0-IE1-IT1-IE0-IT0
not bit addressable
not bit addressable
not bit addressable
not bit addressable
not bit addressable
P1.7
->
P1.0
SM0-SM1-SM2-REN-TB8-RB8-TI -RI
not bit addressable
EA -ES -ET1-EX1-ET0-EX0
P3.7
->
P3.0
-PS -PT1-PX1-PT0-PX0
CY -AC -F0 -RS1-RS0-OV -F1 -P
ACC.7
->
ACC.0
B.7
->
B.0
Global bit to enable interrupts
Serial interrupt (either RI or TI), Clock interrupt on overflow
Power control register
PCON:
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set to 2 will stop the processor
Page 5 of 8
CP
0301/159.233
Alb
Internal
Timer control and mode registers - 2 timers, 0 and 1
TCON: TF0/TF1
TR0/TR1
TMOD: mode1-mode0
mode = 0
mode = 1
mode = 2
Timer overflow flag timers 0/1
Timer run control bit. Set by software to switch timer ON
2 4-bit nibbles. Timer 1 high order nibble, Timer 0 low order.
13 bit timer
16 bit timer
8 bit auto-reload timer. THx -> TLx on overflow. Used by Serial
i/o as bit rate (*32). 0FDH in THx gives 9600bps for 11.059Mhz clock
Serial control register
SCON: SM0-SM1-SM2-REN-TB8-RB8 should be set to 010100 for normal operation
TI
set when the character has been transmitted
RI
set when a character is received
Addressing Modes:
Rn
direct
@Ri
#data
#data16
addr11
addr16
rel
bit
Arithmetic
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
DA
= Register R0 - R7 of the currently selected register bank.
= 8-bit internal data location's address. This could be an internal Data
RAM location (0-127) or a SFR.
= 8-bit internal Data RAM location addressed indirectly through R0 or R1.
= 8-bit constant included in instruction.
= 16-bit constant included in instruction.
= 11-bit destination address. Used by ACALL and AJMP.
The branch will be within the same 2K byte page of Program Memory as
the first byte of the following instruction.
= 16-bit destination address. Used by LCALL and LJMP.
A branch can be anywhere within the 2K byte Program Memory address
space.
= Signed (two's complement) 8-bit offset byte. Used by SJMP and all
conditional jumps. Range is -128 to +127 bytes relative to first
byte of the following instruction.
= Direct addressed bit in internal Data RAM or SFR.
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AB
A
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Add register to Accumulator
Add direct byte to Accumulator
Add indirect RAM to Accumulator
Add immediate data to Accumulator
Add register to Acc. with Carry
Add direct byte to Acc. with Carry
Add indirect RAM to Acc. with Carry
Add immediate data to Acc. / Carry
Subtract reg. from Acc. with borrow
Sub. direct byte from Acc. / borrow
Sub. indirect RAM from Acc./ borrow
Sub. imm. data from Acc. / borrow
Increment Accumulator
Increment register
Increment direct byte
Increment indirect RAM
Decrement Accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment Data Pointer
Multiply A and B
Divide A by B
Decimal adjust Accumulator
Page 6 of 8
| Byte | Cycle | C OV AC
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
| X X X
| 2
|
1
| X X X
| 1
|
1
|
| 1
|
1
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| 2
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1
|
| 1
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1
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| 1
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1
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| 1
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1
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| 2
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1
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| 1
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1
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| 1
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2
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| 1
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4
| 0 X
| 1
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4
| 0 X
| 1
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1
| X
CP
0301/159.233
Alb
Internal
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AND register to Accumulator
AND direct byte to Accumulator
AND indirect RAM to Accumulator
AND immediate data to Accumulator
AND Accumulator to direct byte
AND immediate data to direct byte
OR register to Accumulator
OR direct byte to Accumulator
OR indirect RAM to Accumulator
OR immediate data to Accumulator
OR Accumulator to direct byte
OR immediate data to direct byte
Exc-OR register to Accumulator
Exc-OR direct byte to Accumulator
Exc-OR indirect RAM to Accumulator
Exc-OR immediate data to Acc.
Exc-OR Accumulator to direct byte
Exc-OR imm. data to direct byte
Clear Accumulator
Complement Accumulator
Rotate Accumulator left
Rotate Acc. left through Carry
Rotate Accumulator right
Rotate Acc. right through Carry
Swap nibbles within the Accumulator
| Byte | Cycle | C OV AC
| 1
|
1
|
| 2
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1
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| 1
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1
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| 2
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1
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| 2
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1
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| 3
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2
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| 1
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1
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| 2
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1
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| 1
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1
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| 2
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1
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| 2
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1
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| 3
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2
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| 1
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1
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| 2
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1
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| 1
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1
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| 2
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1
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| 2
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1
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| 3
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2
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| 1
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1
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| 1
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1
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| 1
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1
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| 1
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1
| X
| 1
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1
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| 1
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1
| X
| 1
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1
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A,Rn
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A,direct
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A,@Ri
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A,#data
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Rn,A
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Rn,direct
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Rn,#data
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direct,A
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direct,Rn
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direct,direct|
direct,@Ri
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direct,#data |
@Ri,A
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@Ri,direct
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@Ri,#data
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DPTR,#data16 |
A,@A+DPTR
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A,@A+PC
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direct
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direct
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A,Rn
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A,direct
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A,@Ri
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A,@Ri
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Move register to Accumulator
Move direct byte to Accumulator
Move indirect RAM to Accumulator
Move immediate data to Accumulator
Move Accumulator to register
Move direct byte to register
Move immediate data to register
Move Accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move Accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load Data Pointer with 16-bit const
Move Code byte rel. to DPTR to Acc.
Move Code byte rel. to PC to Acc.
Push direct byte onto stack
Pop direct byte from stack
Exchange register with Accumulator
Exchange direct byte with Acc.
Exchange indirect RAM with Acc.
Exchange low order digit indirect
RAM with Accumulator
| Byte | Cycle | C OV AC
| 1
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1
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| 2
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1
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| 1
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1
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| 2
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1
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| 1
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1
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| 2
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2
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| 2
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1
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| 2
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1
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| 2
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2
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| 3
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2
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| 2
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2
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| 3
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2
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| 1
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1
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| 2
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2
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| 2
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1
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| 3
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2
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| 1
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2
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| 1
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2
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| 2
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2
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| 2
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2
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| 1
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1
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| 2
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1
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1
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1
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Logical
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC
SWAP
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A,Rn
A,direct
A,@Ri
A,#data
direct,A
direct,#data
A
A
A
A
A
A
A
Data transfer
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
PUSH
POP
XCH
XCH
XCH
XCHD
Constants:
Numbers:
Characters:
Operators:
Decimal - 34, Binary - 01110101B, Hexadecimal - 0A8H
‘A’ - ‘Abc’ - ‘A’,00DH,00AH (mixed mode)
()’s + - / * MOD SHR SHL NOT AND OR XOR
Page 7 of 8
CP
0301/159.233
Alb
Internal
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Clear Carry
Clear direct bit
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of dir. bit to Carry
OR direct bit to Carry
OR complement of dir. bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if dir. bit is set & clear bit
| Byte | Cycle | C OV AC
| 1
|
1
| 0
| 2
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1
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| 1
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1
| 1
| 2
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1
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| 1
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1
| X
| 2
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1
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| 2
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2
| X
| 2
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2
| X
| 2
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2
| X
| 2
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2
| X
| 2
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1
| X
| 2
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2
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| 2
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2
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| 2
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2
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| 3
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2
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| 3
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2
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| 3
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2
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A,#data,rel |
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Rn,#data,rel |
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@Ri,#data,rel|
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Rn,rel
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direct,rel
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Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to the DPTR
Jump if Accumulator is zero
Jump if Accumulator is not zero
Compare direct byte to Accumulator
and jump if not equal
Compare immediate data to
Accumulator and jump if not equal
Compare immediate data to register
and jump if not equal
Compare immediate data to indirect
RAM and jump if not equal
Decr. register and jump if not zero
Decrement direct byte and jump if
not zero
No operation
| Byte | Cycle | C OV AC
| 2
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2
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| 3
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2
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| 1
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2
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| 1
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2
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| 2
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2
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| 3
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2
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| 2
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2
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| 1
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2
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| 2
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2
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| 2
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2
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| 3
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2
| X
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| 3
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2
| X
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| 3
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2
| X
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| 3
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2
| X
| 2
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2
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| 3
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2
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| 1
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1
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Boolean
CLR
CLR
SETB
SETB
CPL
CPL
ANL
ANL
ORL
ORL
MOV
MOV
JC
JNC
JB
JNB
JBC
C
bit
C
bit
C
bit
C,bit
C,/bit
C,bit
C,/bit
C,bit
bit,C
rel
rel
bit,rel
bit,rel
bit,rel
Branching
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ
rel
JNZ rel
CJNE A,direct,rel
CJNE
CJNE
CJNE
DJNZ
DJNZ
NOP
Assembler directives and controls
$MOD2051
;
Label:
TEN
ON_FLAG
BUFFER
RESET
SP_BUFFER:
IO_MAP:
MESS1:
EQU
BIT
DATA
CODE
DSEG
CSEG
BSEG
DS
DBIT
DB
ORG
10
6
32
0
6
8
‘Hi’
56H
Include file MOD2051 - defines 2051 symbols
Everything following a semicolon is a comment
Labels of statements used for program branches.
EQUates 10 with the symbol TEN
Assigns bit 6 (either data or SFR space) to the symbol ON_FLAG
Assigns byte 32 (either data or SFR space) to the symbol BUFFER
Assigns 0 in code space to the symbol RESET
Makes the data space the currently selected segment
Makes the code space the currently selected segment
Makes the bit addressable area of data space the cur sel seg.
Reserves 6 bytes of storage in data space. DSEG must be active.
Reserves 8 bits of storage in bit space. BSEG must be active.
Store byte constants in code space.
Specify a value for the cur sel segments location counter.
Page 8 of 8