UNIVERSIDADE FEDERAL DO RIO DE JANEIRO
IM – DCC
CURSO DE CIÊNCIA DA COMPUTAÇÃO
SISTEMAS OPERACIONAIS I – 2009/1
LISTA 1
1. Pontuação Extra
Conforme combinado na primeira aula da disciplina, as Listas de Exercícios valerão como um
trabalho extra nas seguintes condições:
a) Grau 10 – para quem fizer e entregar no prazo todas as listas;
b) Grau 8 – para quem fizer e entregar no prazo acima de 75% das listas
2. Prazo de Entrega
Os alunos que desejarem concorrer pelo trabalho extra devem entregar 10 dos 17 exercícios
sugeridos, até a aula do dia 8 de abril. A escolha dos 10 exercícios é de livre arbítrio de cada
aluno.
A lista resolvida deve ser entregue impressa e no início da aula do dia 8/4.
3. Exercícios
Stallings:
1.3 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two
fields. The first byte contains the opcode and the remainder an immediate operand or an operand
address.
a. What is the maximum directly addressable memory capacity (in bytes)?
b. Discuss the impact on the system speed if the microprocessor bus has
1. a 32-bit local address bus and a 16-bit local data bus, or
2. a 16-bit local address bus and a 16-bit local data bus.
c. How many bits are needed for the program counter and the instruction register?
1.4 Consider a hypothetical microprocessor generating a 16-bit address (for example, assume that
the program counter and the address registers are 16 bits wide) and having a 16-bit data bus.
a. What is the maximum memory address space that the processor can access directly if it is
connected to a “16-bit memory”?
b. What is the maximum memory address space that the processor can access directly if it is
connected to an “8-bit memory”?
c. What architectural features will allow this microprocessor to access a separate “I/O
space”?
d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit
I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain.
1.5 Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input
clock.Assume that this microprocessor has a bus cycle whose minimum duration equals four input
clock cycles.What is the maximum data transfer rate across the bus that this microprocessor can
sustain in bytes/s? To increase its performance, would it be better to make its external data bus 32
bits or to double the external clock frequency supplied to the microprocessor? State any other assumptions you make and explain. Hint: Determine the number of bytes that can be transferred per
bus cycle.
1.6 Consider a computer system that contains an I/O module controlling a simple keyboard/printer
Teletype.The following registers are contained in the CPU and connected directly to the system bus:
INPR: Input Register, 8 bits
OUTR: Output Register, 8 bits
FGI: Input Flag, 1 bit
FGO: Output Flag, 1 bit
IEN: Interrupt Enable, 1 bit
Keystroke input from the Teletype and output to the printer are controlled by the I/O module.The
Teletype is able to encode an alphanumeric symbol to an 8-bit word and decode an 8-bit word into
an alphanumeric symbol.The Input flag is set when an 8-bit word enters the input register from the
Teletype. The Output flag is set when a word is printed.
a. Describe how the CPU, using the first four registers listed in this problem, can achieve
I/O with the Teletype.
b. Describe how the function can be performed more efficiently by also employing IEN.
1.7 In virtually all systems that include DMA modules, DMA access to main memory is given
higher priority than processor access to main memory.Why?
1.8 A DMA module is transferring characters to main memory from an external device transmitting
at 9600 bits per second (bps).The processor can fetch instructions at the rate of 1 million instructions per second. By how much will the processor be slowed down due to the DMA activity?
1.9 A computer consists of a CPU and an I/O device D connected to main memory M via a shared
bus with a data bus width of one word.The CPU can execute a maximum of 106 instructions per
second. An average instruction requires five processor cycles, three of which use the memory bus.
A memory read or write operation uses one processor cycle. Suppose that the CPU is continuously
executing “background” programs that require 95% of its instruction execution rate but not any I/O
instructions.
Assume that one processor cycle equals one bus cycle. Now suppose that very
large blocks of data are to be transferred between M and D.
a. If programmed I/O is used and each one-word I/O transfer requires the CPU to execute
two instructions, estimate the maximum I/O data transfer rate, in words per second, possible
through D.
b. Estimate the same rate if DMA transfer is used.
1.11 Generalize Equations (1.1) and (1.2) in Appendix 1 A to n-level memory hierarchies.
Ts = H x T1 + (1 - H) x (T1 + T2)
= T1 + (1 - H) x T2
(1.1)
Where:
Ts = average (system) access time
T1 = access time of M1 (e. g., cache, disk cache)
T2 = access time of M2 (e. g., main memory, disk)
H = hit ratio (fraction of time reference is found in M1)
Cs = (C1S1 + C2S2) / (S1 + S2)
Where:
(1.2)
Cs = average cost per bit for the combined two-level memory
C1 = average cost per bit of upper-level memory M1
C2 = average cost per bit of lower-level memory M2
S1 = size of M1
S2 = size of M2
1.12 Consider a memory system with the following parameters:
Tc = 100 ns Cc = 0.01 cents/bit
Tm = 1200 ns Cm = 0.001 cents/bit
a. What is the cost of 1 MByte of main memory?
b. What is the cost of 1 MByte of main memory using cache memory technology?
c. If the effective access time is 10% greater than the cache access time, what is the hit ratio
H?
1.13 A computer has a cache, main memory, and a disk used for virtual memory. If a referenced
word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60
ns are needed to load it into the cache (this includes the time to originally check the cache), and then
the reference is started again. If the word is not in main memory, 12 ms are required to fetch the
word from disk, followed by 60 ns to copy it to the cache, and then the reference is started
again.The cache hit ratio is 0.9 and the main-memory hit ratio is 0.6.What is the average time in ns
required to access a referenced word on this system?
2.1 Suppose that we have a multiprogrammed computer in which each job has identical characteristics. In one computation period, T, for a job, half the time is spent in I/O and the other half in processor activity. Each job runs for a total of N periods.Assume that a simple round-robin scheduling
is used, and that I/O operations can overlap with processor operation. Define the following quantities:
• Turnaround time actual time to complete a job
• Throughput average number of jobs completed per time period T
• Processor utilization percentage of time that the processor is active (not waiting) Compute these
quantities for one, two, and four simultaneous jobs, assuming that the period T is distributed in each
of the following ways:
a. I/O first half, processor second half
b. I/O first and fourth quarters, processor second and third quarter
2.2 An I/O-bound program is one that, if run alone, would spend more time waiting for I/O than
using the processor. A processor-bound program is the opposite. Suppose a short-term scheduling
algorithm favors those programs that have used little processor time in the recent past. Explain why
this algorithm favors I/O-bound programs and yet does not permanently deny processor time to processor-bound programs.
2.4 What is the purpose of system calls, and how do system calls relate to the OS and to the concept
of dual-mode (kernel mode and user mode) operation?
Silberschartz:
1.9 Describe the differences between symmetric and asymmetric multiprocessing. What are three
advantages and one disadvantage of multiprocessor systems?
1.10 What is the main difficulty that a programmer must overcome in writing an operating system
for a real-time environment?
2.3 What are the differences between a trap and an interrupt? What is the use of each function?
2.7 Some early computers protected the operating system by placing it in a memory partition that
could not be modified by either the user job or the operating system itself. Describe two difficulties
that you think could arise with such a scheme.