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Mehran University of Engineering & Technology, Jamshoro
Institute of Information and Communication Technologies
M.E- Electronic Systems Engineering (3rd Term)
Advanced FPGA Based Design
Lab Experiment No. 2
Name: _____________________________________________________ Roll No: ______________
Score:_________________ Signature:__________________________________ Date:___________
Design Basic Digital Logic Gates Using Xilinx ISE
PERFORMANCE OBJECTIVE:
After the successful completion of this lab, students will be able to:
 Design, Simulation, Synthesis and Implementation of the basic logic gates using Xilinx
ISE Design Suite 12.3 Software and develop concepts with design entry using VHDL.
LAB REQUIREMENTS:

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PC with Windows XP/2007 operating system.
Xilinx ISE Design Suite 12.3 Software installed.
Digilent Adept Software.
NEXYS2 Spartan 3E Kit.
DISCUSSION:
Everything in the digital world is based on the binary number system. Numerically, this
involves only two symbols: 0 and 1. Logically, we can use these symbols or we can equate them
with others according to the needs of the moment.
Digital logic may be divided into two classes: combinational logic, in which the logical
outputs are determined by the logical function being performed and the logical input states at that
particular moment; and sequential logic, in which the outputs also depend on the prior states of
those outputs. Both classes of logic are used extensively in all digital computers.
Since both types of logic circuits begin with logic gates to combine logical input
signals in various ways to produce the desired outputs, we will begin our lab studies with the
very simple AND gate design and will progress through by designing other Universal
combinational logic gates.
This lab will purely highlight to increase your Software skills, rather your
programming skills. Focus on designing Very basic logic using Xilinx ISE Software and work
through your exercises to gain more knowledge.
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DESIGNING PROCEDURE:
STEP1: DESIGN ENTRY
1. Invoke Xilinx ISE Design Suite 12.3 Software
Double click the Xilinx ISE Design Suite icon (Fig 2.1) present on your desktop, Check
with YOUR instructor if not available.
Fig 2.1: Xilinx ISE
Design Suite
A screen like that of figure 2.2 will be displayed
Fig 2.2: Xilinx ISE Design Suite Project Navigator
2. Creating a New Project
To create a new project using the New Project Wizard, do the following:
From Project Navigator, select File > New Project.
The New Project Wizard appears, as shown in figure 2.3
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Figure 2.3: New Project Wizard—Create New Project
3. Enter your desired Project name in the Name field.
4. In the Location field, browse to the directory in which you installed the project.
5. Verify that HDL is selected as the Top-Level Source Type, and click Next.
Choose the following settings (Fig 2.4) as shown below:
 Product Category: All
 Family: Spartan3E
 Device: XC3S1200E
 Package: FG400
 Speed Grade: -4
 Top-Level Source Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)
 Simulator: ISim (VHDL/Verilog)
 Preferred Language: VHDL
 Property Specification in Project File: Store All Values
 VHDL Source Analysis Standard: VHDL-93
These settings can be done any time, but if settled once will not change automatically until
user disturbances.
After Fulfill the Setting Click Next, the following Project summary window (Fig 2.5) will
appear.
6. Click Finish (Fig 2.5) to complete the project creation and begin the design process.
Figure 2.4: New Project Wizard- Project
Setting Design Suite
7.
Figure 2.5: New Project Wizard- Project Summary
Suite
Creating a New Source file; Go to Project _ New Source, select VHDL Module and
Enter the name “and_gate” as shown in figure 2.6 and click next you will get a window
as shown in figure 2.7.
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8. Enter the ports for your module (fig 2.7). This is strictly optional, and saves you the typing of
Figure 2.6: New Source Wizard- Source Type
Figure 2.7: New Source Wizard- Specify ports
creating the VHDL entity manually. Whether you fill this out or not, the resultant text file
will be totally under your control for later editing.
9. After enter the ports click Next, the following summary window (Fig 2.8) will appear.
Figure 2.8: New Source Wizard- Summary
10. Click Finish (fig 2.8) to open the empty VHDL file in the ISE Text Editor (Fig 2.9). In
the ISE Text Editor, the ports are already declared in the VHDL file, and some of the
basic file structure is already in place. Keywords are displayed in blue, comments in
green, and values are black. The file is color-coded to enhance readability and help you
recognize typographical errors.
Figure 2.9: VHDL File in ISE Text Editor
Review Questions:
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1. Repeat the same Exercise for XOR, X-NOR and NOR gates and attach results.
Step No.2 Simulation:
Simulation is the process of testing the logical or processing functionality of
designed logic. Several kinds of Software and hardware Tools to provide this functionality. With
Xilinx ISim Simulator you can simulate your design by writing “Test benches” and/or by
assigning Manual wave flows to inputs and check functionality of outputs after simulation.
The Xilinx® ISE® Design Suite provides an integrated flow with the Mentor
ModelSim simulator and the Xilinx ISim simulator that allows simulations to be run from the
Xilinx Project Navigator.
Behavioral Simulation:
After Creating New project and New source File now it is ready to simulate our
design.to simulate the Design follow the following steps.
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
In the Design Panel, select the Simulation radio button. The Simulation type drop-down list
appears.
Select gate_logic_Behavioral file (figure 2.10) and double click on Simulator Behavioral
Model in the Process window, following ISim window (Figure 2.11) will appear.
Fig 2.10: Behavioral Simulation Process
Some features of this window include:
1. A Source Files panel where source files to be viewed can be selected
2. An Objects panel where different signals can be added to the simulation
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3. A simulation panel where the state of signals can be observed
4. A Console panel
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Fig 2.11: ISim Window
Select the Simulation from the menu bar and click on Restart as shown in following
figure2.12. After click on Restart window (figure 2.13) will appear.
Fig 2.12: ISim window- Simulation Process

Fig 2.13: Simulation Process-After Restart
To force the input signal (a & b) to an alternating pattern (clock), Right click on the
input port “a” (figure 2.14) and select the Force clock.
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
Enter the following parameter (figure 2.15). click on apply and OK.
Fig 2.14:
 Leading
EdgeSimulation
Value: 1/0Process-Assigning clock input
 Trailing Edge Value: 1/0
 Starting at the time offset: 0
 Cancel after the time offset: 100, 200, …
 Duty cycle (%): 10, 20, 30 ,……
 Period: 100
Similarly Right click on the input port “b” (figure 2.16),
select the Force clock and set the parameter.
 Select the Simulation from the menu bar and click on
Run as shown in following figure 2.17. After click on
Run following waveform window (figure 3.8) will appear.
Fig 2.15: Force the Signal- Enter Parameter
Fig 2.16: Force the Signal- Run the process
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Fig 2.17: Behavioral Simulation- Output
Synthesis and implementation:
Waveform
The design has to be synthesized
and Result
implemented before it can be checked for
correctness, by running functional simulation or downloaded onto the prototyping board. With
the top-level VHDL file opened (can be done by double-clicking that file) in the HDL editor
window in the right half of the Project Navigator, and the view of the project being in the
Module view , the implement design option can be seen in the process view. Design entry
utilities and Generate Programming File options can also be seen in the process view. The
former can be used to include user constraints, if any.
Step No.3 Synthesis:
Synthesis is a process by which an abstract form of desired circuit behavior (typically
register transfer level (RTL)) is turned into a design implementation in terms of logic gates.
Synthesis is one aspect of electronic design automation. With Xilinx ISE Design Suite user can
convert the HDL (hardware description language) or other kinds of designs created with Design
entry tool into the Gate level design for any FPGA family.

To synthesize the design, double click on the Synthesize Design option in the Processes
window (Figure 2.18) .
Figure 2.18: Synthesize the Design

The schematic diagram of the synthesized VHDL code can be viewed by double clicking
View RTL Schematic under Synthesize-XST menu in the Process Window. By double
clicking it opens the top level module showing only input(s) and output(s) as shown below
(figure 2.19).
Figure 2.19: RTL Schematic Symbol
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
Similarly you can view the Technology Schematic Symbol by double clicking View
Technology Schematic under Synthesize-XST menu in the Process Window. By double
clicking it opens the top level module showing the type of input(s) and output(s) as shown
below (figure 2.20).
Figure 2.20: Technology Schematic Symbol
Step No.4 Implementation
To implement the design, double click the Implement design option in the Processes
window. It will go through steps like Translate, Map and Place & Route. If any of these steps
could not be done or done with errors, it will place a “X” mark in front of that, otherwise a tick
mark will be placed after each of them to indicate the successful completion. If everything is
done successfully, a tick mark will be placed before the Implement Design option. If there are
warnings, warning symbol will be placed in front of the option indicating that there are some
warnings. One can look at the warnings or errors in the Console window present at the bottom of
the Navigator window. Every time the design file is saved; all these marks disappear asking for a
fresh compilation.
Before implement the design you must create the User Constraint File UCF.

User Constraint File (UCF):
In order to test the design in the NEXYS2 Board, the inputs need to be connected to the
switches/buttons on the board and the outputs need to be connected to the onboard LED’s. To
create the constraint file, ensure that the implementation radio button is selected and your VHDL
module is highlighted. In the processes window, expand User Constraints and double click on
I/O Pin Planning (Plan Ahead) Post Synthesis (figure 2.21-a). Answer “Yes” when asked if you
want to create the UCF file. This will create the constraint file but also open the Plan Ahead
application. Wait for the Plan Ahead to fully open, then close it. You will now see the .ucf file in
your hierarchy (figure 2.21-b).

Single Click on and gate.ucf file from within Project Navigator, and then Select “Edit
Constraints (Text)” from the Process window as below (figure 2.22).
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Fig-2.21-a: Creating User Constraints
Figure 2.21-b: Edit UCF
File
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Then you can edit the constraints as shown below (figure 2.21). To figure out the correct
pin locations, consult the NEXYS2 manual. Even simpler, you may notice that most pins
of interest are printed on the board surface.
Fig-2.22: Editing UCF- Assigning Pins
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
After assigning the pins to inputs and outputs of our design save Ucf file. Now clicking
once on your top-level design in the Sources Pane, followed by a double click on
“Implement Design” option in the Processes window. It will go through steps like
Translate, Map and Place & Route as shown in figure 2.23.
Fig-2.23: Implement the Design

The next step in the process is to have the Xilinx ISE create a programming file of the
design. This is done by clicking once on your top-level design in the Sources Pane, followed
by a double click on “Generate Programming File” in the process window (figure 2.24).
Now the programming file (bitstream file) of extension “.bit” has been generated, it is time
to load your design into the FPGA, and test it out. This can be done in many different ways
depending on your available equipment and preferences.
Fig-2.24: Generate the Programming File
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 Programming the Device
Once the programming file (bit stream file) is generated, the file has to be
downloaded to the NEXYS2 Spartan3E device. This is done by using another
application Adept Software provided by Digilent.
 Connect the Demo board to the PC using the USB extension cable. Connect the USBType A connector to PC and Mini-AB end to the demo board.
Click on Start and Go to Adept.
 Following window (figure 2.25) will appear. If the board is working properly it should
show the following information which is highlighted by the box. If it is not showing there
might be problems with the board and/or the cable.
 To download the program, click on Browse command in the first Row which says FPGA
(XC3S1200E). Browse to the project folder and choose the corresponding bit file as
shown below figure (2.26) and click open
Click
Figure 2.25: Adept Opening screen after
connecting FPGA board

Figure 2.26: Choosing the bit stream file
to download
Once this is done, a warning window will pop up if the clock is set to CCLK which can be
closed by clicking Yes as shown below (Figure 2.27). Or it can be fixed by setting Clock
source to JTAG Clock in the Synthesize setting in Xilinx ISE.
Figure 2.27: Warning about CCLK and JTAG CLK

Now click on the Program button (figure 2.28) to program the FPGA and if it successfully
programming the following information should show up in the status window (figure 2.29).
Ensure that the “Programming Successful” message appears in the message window.
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Click
Figure 2.28: Programming
Figure 2.29: Showing the Programming Status
Review Question:
 Repeat the same Exercise for All Logical Gates.
Final Assignment:
1. What is Simulation?
2. Attach the Simulation result of OR & XOR, NAND gates.
3. What is Implementation?
4. What is UCF?
5. What is difference between CCLK and JTAG CLK?
6. Define the Synthesis. Write down the steps for synthesize the design.
7. Attach VHDL codes Simulation results for following Boolean expression.
Z  ABC  ABC  ABC
X  ABCD  ABC