ECE 441 Senior Design
Technology Research
Brent Hansen
Team #22
1. Revision History
Date
October 18,
2008
October, 19
2008
Description
Contributor
Initial Creation
Brent Hansen
Proofreading and Documentation
Brent Hansen
2. Introduction
The PCIe memory card (PMC) is a project sponsored and mentored by Intel, for whom we
are specifically creating this project. It will give them more flexibility in troubleshooting
issues with the CPU’s during initial start-up. It will be a PCIe add-in card with one memory
bank that is capable of holding a minimum of two gigabytes of memory. The PMC will then
be used to investigate issues where the CPU cannot communicate correctly to the memory.
The PMC will allow Intel to bypass the built-in memory controller in the CPU during
troubleshooting. This is the basic requirement of the PMC; and the more interesting feature
that we are hoping to build into the board is a USB port for programming of the memory.
This will allow for testing software and scripts loaded onto the memory in the PMC. Then the
computer can be set up to run the test or even boot from the software on the memory. This
feature will allow for a new type of testing and also make the card more active in the testing
of the CPU.
2.1 Customer Requirements & Project Background
When Intel creates a new type of CPU they go through initial release (A0 silicon) and then
make changes to the architecture as needed. This initial silicon is tested with a customized
platform created by Intel platform and test engineers. Each platform is built with the
capability of testing all the functions of the new CPU along with its compatibility with all
types of computer devices. Intel has had problems in the past where the CPU could not
communicate with the memory on the test platform (on-board memory). This is a significant
problem because the memory controller and the CPU is one unit so it is hard to tell which
part of the CPU is not working correctly. The objective of this project is to create an add-in
card that will give Intel the ability to continue testing if the on-board memory is not seen. The
PCIe memory card (PMC) will give Intel the ability to have system-memory on an add-in
card so the memory controller on the CPU can be bypassed, testing can continue, and
trouble-shooting can begin on the CPU issues.
Intel’s requirements are to have a PCIe add-in card with enough memory to load an operating
system or test software. The PMC must be recognizable by all operating systems and be sized
to fit properly in the Intel test platform and other ATX computer systems. These are the basic
requirements; however, the way we implement the hardware design and device drivers is up
to the team. Intel has extra features that are useful for testing and give the card more dynamic
testing features. Intel would like the board to have a USB port for programming the memory
with tester software or an operating system. This feature turns the PMC into a programmable
test card with infinite testing processes available for execution. The PMC could be
programmed from a third source so that it runs tests on the platform and the CPU while the
next test is being loaded into the next PMC in the adjacent PCIe slot. This gives much more
functionality to the PMC and gives Intel more ways of testing.
The PMC hardware architecture is initially going to contain these parts:
1. FPGA
2. Bridge
3. Memory
4. USB port
5. Microcontroller
6. Programming ports and corresponding ROMS
7. LED
The card will interface with a by-one PCIe signal. The PCIe bridge allows for extension of
the PCIe buss and will feed the newly converted PCI buss to the FPGA. The FPGA is the
intelligence center of the project and will do all the sorting of commands and logic. It will
then connect to the memory where there will be a single DIMM slot for a removable memory
stick. The microcontroller will be used to take the input from the USB port and talk to the
FPGA. To get the programmable memory to work, we will need to devise some type of
protocol for requests and interruptions between the incoming computer signals and the
microcontroller requests. I think an indicator LED that illuminates when the FPGA has seen
the USB connection would be helpful along with LEDs that shut off when the FPGA has
successfully uploaded its EEPRFOM.
2.2 Project Research
Manufact
ure
Programmable
(software)
Description
Memory
size
Hardware setup
Pros
Cons
Cost
DDR
Kingston
, Corsair,
OCZ
NO
On-board memory
1GB
DDR-200 100
MHz DDR266 133 MHz
DDR-300 150
MHz DDR333 166 MHz
DDR-400 200
MHz
Used as an
industry
standard for
a significant
period of
time.
Abundant
information
available
about
designing
with DDR
Half the
speed of
DDR2
$26.00 per
GB
DDR2
Kingston
, Corsair,
OCZ
NO
On-board memory.
1GB
DDR2-400
100MHz
DDR2-533
133 MHz
DDR2-667
166 MHz
DDR2-800
200 MHz
DDR2-1066
266 MHz
Operates
quickly and
is available
at a good
price per
GB.
The memory
interface is
more
complicated
with DDR2
$15.00 per
GB
DDR3
Kingston
, Corsair,
OCZ
NO
On-board memory
1GB
DDR3-800
100 MHz
DDR3-1066
133 MHz
DDR3-1333
166 MHz
DDR3-1600
200 MHz
Very fast
transfer
rates.
Slower
clock then
DDR2. Is
the most
expensive
option.
$35.00 per
GB
Flash
memory
add-in
card
Referenc
e design
develope
d by Intel
Yes. This is a
PCI memory
card so it is
fully
programmable.
The Flash Memory
PCI Add-In Card
was created to
demonstrate the
feasibility of
interfacing flash
memory to
the PCI buss in an
embedded system.
In such a system,
flash memory
devices are used for
high density and
high
performance massstorage for user code
and data. *Intel
This
board’s
maximum
memory is
32MBytes
This card
interfaces with
the PCI buss and
uses an FPGA as
the main
controller. It is
programmable
with a ROM that
holds the
EEPROM. All of
the integrated
accessible
memory is
located in a flash
memory array. It
also has
expansion slots
for more flash.
It seems to
be exactly
what we are
going to
design. Our
version will
just be
updated to
current
technology
and
interfaces.
This board
was
developed in
1997 and
has very
limited
memory and
does not
work on
PCIe.
no price
given
DDR2
SDRA
M
Interfac
e for
Spartan3
Generati
on
FPGAs
Xilinx
This is an FPGA
that has a built in
DDR2 SDRAM
interface. The PGA
is a
Spartan®-3
generation.
N/A
Contains 12
devices ranging
from 50,000 to
3.4 million
system gates.
This FPGA
could
connect
directly to
the DDR2
and would
not need an
intermediate
memory
controller.
These types
of FPGA’s
are rather
expensive.
$150.00
Altera
Stratix
II
Devices
Altera
YES. ISE®
WebPACK™
software is the
ideal
downloadable
solution for
FPGA and
CPLD design.
Offers HDL
synthesis and
simulation,
implementatio
n, devicefitting, and
JTAG
programming.
*Xilinx
Yes. Altera
uses Quartus II
software.
This is another
FPGA that has a
DDR2 system builtin.
N/A
Stratix II GX
devices are
available in
densities ranging
from 33,880 to
132,540
equivalent logic
elements (LEs),
with over 6.7
Mbits of on-chip
RAM and up to
252 (18-bit x 18bit) embedded
multipliers.
*Altera
This FPGA
does not
need an
extra
memory
interface. It
also can be
setup to not
need a PCI
bridge. This
means it can
interoperate
the PCIe
buss.
Faster than
the Xilinx
FPGA, but
its memory
solutions
look a little
less
comprehensi
ve.
Stratix ->$600.00
for just
the silicon
Arria
$170.00
PLX
PCIePCI
Bridge
PLX
Yes. Uses
PLXmon
software to
write the
EEPROMS.
A PLX PCIe to PCI
bridge extends the
PCIe buss to our
device. This will
take the serial PCIe
buss and convert to
a parallel PCI signal
structure.
N/A
N/A
Could make
the signal
work easier
by
formatting
the PCI buss
to be a
parallel
signal.
Pericom
PCIePCI
bridge
Pericom
Yes
A PCIe-PCI Bridge.
N/A
N/A
Consists of
less BGA
connections
to the board
compared to
the Pericom.
No
This is a PCIe x16
memory adapter. It
had 4 DIMM slots.
4gb of
memory.
Any DDRDIMMs of
the
DDR266,
DDR333 or
DDR400
are
compatible.
Not published
Contains a
lot of
memory and
looks like it
could work
perfectly for
the project.
GIGA Gigabyte
BYTE
i-RAM
memor
y
board -
Larger than
the Pericom
bridge.
$16.00
The card has
a five-volt
supply, so it
is a specific
slot-type and
will not fit
in the
standard PCI
slot.
2.2.1 Technology Review Analysis - Systems
From the data and information collected, it seems there is no current system that can
accomplish the tasks for this project. The products listed are some of the many
components, that when put together, can make an add-in memory card. Along with many
products there are many prices available and variations of each component to support
every task you could think of. The difficulty in deciding on components and technologies
is determining if they are compatible and if they encompass every function you could call
from it.
Based on the information in the chart, and the research, I would prefer to get an Altera
FPGA and probably a variety of the Arria line. This line will do a DDR2 interface while
still being more than half the price of the Stratix FPGA. The Arria line has less logic
gates and less frills, but I think it will do the job nicely. The PCI bridge that is rather
cheap, is there as a simplifier for the signal input and output. Each vendor has its own
software and architecture and each is comparable in price, so it is a toss-up as to which is
better. It will come down to possible pinout, power consumption, it our mentor has any
input and software type.
2.3 Feature Set
2.3.1 Absolute Minimum Requirements
o Meets the PCIe spec requirements for a PCIe adaptor card
o Card is recognized by all operating systems
$15.00
$140.00
o Card size will fit in ATX case and Intel test platform
o Card will work properly the test platform uses the additional memory
correctly
o All of the memory is viewable by the computer
o Will not damage host platform built-in safety circuits and fuses for overcurrent protection
o Design and hardware layout approved by mentor
o LED’s used as status indicators throughout the board
o Solution for any thermal heating issues
2.3.2 Desired Feature Set
o Send the SMBUS signal to the FPBGA allowing for the resting of the
memory control unit
o USB input for memory programming
Appendix A. References
Intel Corporation, “Flash Memory PCI Add-In Card for Embedded Systems” Santa Clara,
CA. September, 1997 [cited October 18th, 2008]
Available from World Wide Web:
http://www.eetasia.com/ARTICLES/1999OCT/1999OCT25_BD_EMS_AN.PDF?SOUR
CES=DOWNLOAD
Samson Ng, “DDR2 SDRAM Interface for Spartan-3 Generation FPGAs” Xilinx, Inc.
May 9, 2008 [cited October 18th, 2008]
Available from World Wide Web:
http://www.xilinx.com/support/documentation/application_notes/xapp454.pdf
PLX Technology, “ExpressLane™ PCI Express to PCI Bridge”
Sunnyvale, CA 94085 USA., October 2005[cited October 18, 2008]
Available from World Wide Web:
http://www.plxtech.com/pdf/product_briefs/PEX8111_PB_EC_26Oct05.pdf
Pericom superconductor company, “PCI Express®-to-PCI Reversible Bridge” 5/14/2008
[cited October 18th, 2008]
Available from World Wide Web:
http://www.pericom.com/pdf/databriefs/PI7C9X110_db.pdf
Geoff Gasior, “Gigabyte's i-RAM storage device
RAM disk without the fuss” January 25, 2006[cited October 18, 2008]
http://techreport.com/articles.x/9312
Appendix B. Naming Conventions and Glossary
ATX  The ATX ( Advanced Technology Extended) is a standard form factor for
computer cases created by Intel in 1995 has been revised numerous times since, the most
recent being released in 2004. A full size ATX board is 305mm wide by 244mm deep
(12" x 9.6”).
BUSS  An electrical bus (sometimes spelled buss) is a physical electrical interface
where many devices share the same electric connection. This allows signals to be
transferred between devices all connected to the same buss allowing for information or
power to be shared). A bus often takes the form of an array of wires that terminate at a
connector which allows a device to be plugged into the bus.
CPU  A Central Processing Unit (CPU) is the main logic device for a computer.
Test Platform  a test platform is a customized testing station where the development and
design on the platform is to test a certain product with certain criteria.
Boot  Booting means that the computer has turned on and successfully executed the start
up or initial functions it was instructed to do.
ROM  Read-only memory is a class of storage memory used in computers and other
electronic devices. Because data stored in ROM cannot be modified it is mainly used to
distribute firmware (software that is very closely tied to specific hardware, and unlikely
to require frequent updates).
EEPROM  EEPROM also known as E2PROM stands for Electrically Erasable
Programmable Read-Only Memory, is a type of non-volatile memory used in computers
and other electronic devices to store small amounts of data that must be saved when
power is removed.
Block  A block is the basic element of a system. It is a standalone object that performs
some function in the system. A block should be ‘small’ enough that everything contained
inside of it can be fully understood as a whole, or the contents can be purchased as a whole.
Customer Requirement  A requirement that may or may not be able to be tested as is. A
requirement supplied by the customer, sponsor, or mentor.
Engineering Requirements  A requirement that can be tested and evaluated through a step
by step process. Usually a numerical specification is included.
Environment  The set of influences that the system will be operating within. These could
include temperature, humidity, immersion, vacuum, etc…
Interface Characteristics  Every connection between blocks is defined by a unique name
and a list of interface characteristics. These characteristics define an interface to the degree
that a block can be built without knowledge of other blocks in the system
Locality Decomposition  The process of dividing a system into blocks based on the
similarity (locality) of blocks. (e.g. all inputs together, all outputs together)
Sub-System  This is a grouping of one or more blocks that function together to perform
some task. (e.g. a motor and a motor controller perform the task of motion.)
System  The complete system that you are designing. This includes all blocks in your
design.
Top-Level  This refers to the system block diagram containing all blocks in the system.
PCI Express  Peripheral Component Interconnect Express, abbreviated as PCI-E or
PCIe, is a computer expansion card interface format introduced by Intel in 2004. It was
designed to replace the general-purpose PCI expansion bus, the high-end PCI-X bus and
the AGP graphics card interface. Unlike previous PC expansion interfaces, rather than
being a bus it is structured around point-to-point serial links called lanes.