In the preceding chapters, you have studied the application of digital ICs to implement logical and arithmetic functions. In this chapter, You will look more closely at the characteristics of the circuits you have used. Particular attention will be paid to the switching characteristics of these digital circuits and the resulting limits on the circuit usage.
Upon completion of this chapter you should be able to:
•
Identify the two major IC logic gate families.
•
Use IC specification sheets
•
Understand the use of tri-state logic circuits
•
Interface the different logic families together in circuits
•
Understand the need for Electrostatic Discharge (ESD) control
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In this chapter you will study the circuits used to perform the switching required in digital logic. Both the TTL and CMOS logic families will be examined. The characteristics of both families will be covered well enough so that you will be ab le to choose the best circuit for an application when switching speed, power consumption and cost are considered.
In order to understand logic circuits you need to learn the terminology associated with the pulse waveforms that these circuits produce. Until now, we have considered all digital signals to be perfect square wave pulses. Such a signal can only be generated by an amplifier with infinite bandwidth. Since all amplifiers have a finite bandwidth, the pulse outputs of digital circuits will deviate from the ideal perfect pulse. A typical pulse signal is shown in Figure 8-1. An ideal pulse is shown for comparison.
The frequency of pulses is the number of pulses occurring in a time period. The frequency in digital circuits is often e x p r e s s e d i n m e g a h e r t z ( M H z ) , w h i c h i s m i l l i o n s o f cycles/second. The period of a pulse is defined as the time between two adjacent pulse. The period is expressed in seconds.
The relationship between frequency, F, and period, T, is F = 1/T.
The pulse amplitude is the maximum steady-state value of the voltage. The rise and fall times are measures of the amount of time required for the circuit to switch from one state to another.
The rise time is the amount of time needed for the pulse voltage to change from 10% of the ideal value to 90% of the ideal value. Likewise, the fall time is the time required for the pulse voltage to drop from 90% of the ideal value to 10% of the ideal

value. The 90% and 10% values are chosen since these choices will avoid measuring pulse parameters in areas where ring, overshoot and undershoot occur.
The pulse width is a measure of time between the 50% point on the leading and falling pulse edges. Pulse width is expressed in seconds.
At the end of pulse transitions, distributed capacitances and inductances form a resonant circuit which produces a decaying sinusoidal oscillation. This oscillation is known as ringing. When switching from LO to HI, the added amplitude beyond the ideal is known as overshoot. When switching from
HI to LO, the voltage below the ideal minimum is known as undershoot. Undershoot and overshoot are expressed as a percentage of the ideal pulse maximum. Ringing may last from one-half cycle to several cycles depending on the amount of energy to be dissipated in the tank circuit.
Another important parameter in switching circuits is the propagation delay. Propagation delay is the amount of time required for a pulse to pass through a gate. Propagation delay results from the rise and fall times and is additive for multielement circuits. Fortunately, rise and fall times are not cumulative for a circuit since switching circuits do not amplify waveform defects from previous gates.
For convenience, logic circuits are frequently grouped by the number of gates contained in the circuit. SS I circuits are logic circuits containing less than twelve gates. MSI circuits contain more than 11 gates and less than 100 gates. LSI circuits contain 100 or more gates. The term VLSI is used often but no agreement on the exact definition of this term has been reached.
The forerunner of the TTL logic family is the diode logic g a t e. T he A ND and O R d i o de lo g ic g a t e s ar e sh o w n i n
Figure 8-2.
Diode logic gates work well but cannot deliver significant cuiTent. The obvious solution to this problem is to add a transistor amplifier to the diode gate output. This type of circuit was used for many years and was known as DTL or diode transistor logic. DTL is obsolete since the advent of TTL circuits.

TTL or transistor-transistor logic circuits are implemented using multiple emitter transistors. This multi-emitter circuit is actually a more integrated and compact method of making a circuit which will perform the same function as the DTL circuits mentioned earlier. Figure 8-3 shows a basic TTL circuit.
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You have a basic understanding of the logic functions performed by TTL gates. Now you will study the switching characteristics of these circuits. Table 8-1 lists some characteristics of TTL circuits.
You know already that the two logic levels of TTL are 5
^DC for Vcc (ideal voltage at HI output) and .4 VDC for Vol
[ voltage at LO output). Vcc and Vol are the normal HI and LO
[TL voltage levels for inputs or outputs. In practica l TTL zircuits a logic LO is between 0 and 0.8 volts and a logic HI is between 2.8 and 5.0 volts.
When the output of a TTL gate is LO, a current Iol flows
Tom Vcc of the next connected gate through the gate output to ground, this condition is known as current sinking. A standard
FTL circuit can sink 16 ma. When the output of a TTL circuit is
Ell a current, Ioh, flows from Vcc through the gate output then
:hrough the input of the next connected gate to ground. This current is known as sourcing current and ha s a value of .4 ma for standard TTL circuits. Examples of sinking and sourcing rurrent flow are shown in Fieure 8-4.

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In addition to the output current specification, each gate has two input current specifications. The two input current specifications are logic LO current, HI, and logic HI current, Iih,.
For standard TTL circuits, Iil is 1.6 ma and Iih is .040 ma.
The current capabilities of a gate for the logic HI and LO conditions are very important in determining the number of gates that a particular logic gate can drive. The term fan -out describes the number of gate inputs which can be driven by a single gate output. The fan-out can be calculated from the input and output logic currents.
For the logic HI currents, fan-out = Ioh/Iih = .4ma/.04ma =
10. For the logic LO currents, the fan-out = Iol/Iil = 16ma/1.6ma
= 10. Notice that the logic LO and HI fan-outs are the same. This is not an accident and for members of the same logic family the fanouts will be the same. When families or subfamilies are mixed, the fan-out must be calculated from the logic currents.
Specification sheets are used by the manufacturers of logic devices to typify device performance. Specifications are available to describe both the electrical and mechanical characteristics of logic devices. Frequently a manufacturer will publish a book containing the specifications of all TTL devices which their company manufactures for sale. One example of a book of this type is THE TTL DATA BOOK VOLUME 2

published by Texas Instruments in 1985. This book describes all standard, Schottky, and Low-Power Schottky TTL circuits manufactured by Texas Instruments.
The data in this book will also apply to circuits manufactured by other companies to a large extent; however, some differences will occur. This book contains four sections which provide a large amount of information about TTL devices.
T h e G e n e r a l I n f o r m a t i o n s e c t i o n p r o v i d e s a n alphanumeric index, a glossary of TTL symbols ,terms and definitions, parameter measurement information and graphical representations of typical circuit characteristics.
The index will help you find the data sheet of interest while the other parts of the general section are used to interpret the specification sheet. The Functional Index section gives a list of TTL circuits by their logical function. This section is used to find the 74 series device which will perform the logic function to be implemented.
The Mechanical Data section specifies the mechanical configuration of all available IC packages. This includes data on dual inline packages, chip carrier packages and flat packages.
The mechanical section also contains ordering information to allow buyers to obtain the needed IC package.
The major section of the book is the TTL Devices section.
This section contains data sheets on each device. The data sheet contains a short device description, a functional truth table, a logic diagram for each gate of the device and basing diagrams for each package the device is manufactured in. Additionally, schematics for a typical gate are included for the less complex devices.
Four tables of device data are included for each device. The tables are: absolute maximum ratings over free-air temperature range, recommended operating characteristics, electrical chara cter ist ics o v er reco mme nd ed opera ting f ree -a ir temperature range, and switching characteristics, Vcc = 5V, Ta =
25 C. The most common parameters and their definition are shown in Table 8-2.
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The TTL family of circuits basically consists of a diode AND gate followed by an inverting transistor amplifier. While a simple inverting transistor amplifier like the one in Figure 8-5 would work, it would have a number of drawbacks.

The largest drawback is that the switching propagation delay would not be the same for switching from LO to HI as from HI to LO. This occurs since to cause the transistor to switch, the collector resistor will be several times larger than the resistance of the transistor when it is turned on. Thus the LO to
HI transition will take place more slowly than the HI to LO transition since the RC time constant is changed when the transistor is turned on. The solution to this problem in the TTL family has been the totem-pole output amplifier as shown in
Figure 8-6.
The totem-pole output amplifier closely approximates the equivalent circuit shown in Figure 8-6. The circuit provides nearly equal LO-HI and HI-LO switching times by equalizing the resistance for the logic on and logic zero states. While most
TTL circuits use this output configuration, some do not. Notice that for a totem-pole output amplifier the only method of tying the outputs together is via the input of another gate. Some TTL gates are available using a single output transistor with an opencollector. This configuration is shown in Figure 8-7.

This circuit is very much like the simple inverting amplifier discussed earlier and will switch more slowly from logic LO to HI than the totem-pole transistor output TTL devices. The open collector circuit was an early solution to connecting several gate outputs to a bus. This sort of connection is known as wired logic. Some examples of wired logic are shown in Figure 8-8.

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Wired logic may appear complex but it is simplified when you remember that: a. If any gate output goes LO then all outputs are pulled LO.
b. The bus can only be HI when all outputs are HI.
Another type of output circuit useful in bus oriented systems is the three-state output circuit. In this type of circuit the logic gate output is not connected to the output wiring until the gate has received an enable signal. This results in the circuit having three kinds of outputs. In addition to the normal binary
LO and HI, the output can be in a high impedance (disconnected) state.
Three state logic was initially developed as Tri-State Logic by National Semiconductor Corp. An example of a three state logic circuit and it's schematic symbol is shown in Figure 8-9.

The utility of three-state circuits is that they allow the time divided use of shared buses. This means a variety of circuits can have access to the shared bus one at a time. The tristate circuit is widely used in computers.
Until now we have concentrated on the switching characteristics of the standard TTL family. One problem encountered in using standard TTL circuits is that when the circuits used in TTL switch from ON (saturated with E-B and C-B junctions both forward biased) to OFF, a large number of current carriers are present in the depletion zone. The time required to remove these carriers form the depletion zone is known as the storage time.
Storage time and interelectrode capacitance are the major contributors to propagation delay. Schottky, low-power Schottky and advanced low-power Schottky are the fastest and most popular TTL series. These circuits obtain their high switching speed by clamping the collector of each transistor to it's base with a Schottky barrier diode. A Schottky barrier diode or hot carrier diode is formed with a junction made from a metal such as gold or aluminum and N-type material. The use of a clamping diode between collector and base is not new; however, normal junction diodes have considerabl e storage time problems of their own. A Schottky diode has no storage problems and virtually eliminates transistor carrier storage when applied as a collector-base clamp. Figure 8-10 shows the use of a Schottky barrier diode as a clamp, the schematic symbol for a transistor with a Schottky diode clamp and a typical Schottky TTL circuit.

FIGURE 8-10. Continued.
O Vcc
© Output
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FIGURE 8-11. MOSFET
Construction. c. Schematic Diagram
The Schottky Diode Clamped TTL NAND Gate
MOSFET is an acronym for Metal Oxide Semiconductor
Field Effect Transistor. MOSFETS are available as either P channel or N channel devices. A diagram of the construction of an N channel MOSFET is shown in Figure 8-11.
Drain Well
Gate
Note: Substrate is
Source
Silicon or
Metal Gate
Dielectric
Layer
Drain
N-
Substrate
Source Well
Silicon
Substrate generally connected to source.
N-Channel MOS b. Symbol
Channel MOS
Transistor a.
Structure
The gate is made of metal, and is insulated from the P-type silicon substrate by a thin layer of silicon dioxide. The gate, dielectric and substrate form a small capacitor. The device can be constructed as shown, operated with the drain more positive than the source, and no current will flow from drain to source when no voltage is applied to the gate.
This type of operation is known as enhancement mode operation. The transistor will conduct larger currents as larger positive voltages are applied to the gate. This type of circuit is popular for use in logic circuits since it can be operated with only positive voltage sources.

Another mode of operation for MOSFETS is known as depletion mode. A depletion mode device is constructed similarly to the enhancement mode device of Figure 8-12, except that a thin channel of N-type material connects the source and drain. The device is connected with the drain more positive than the source. With no gate voltage, current will flow from the drain to the source. A negative gate voltage will cause the device to conduct less current while a positive gate voltage increases current flow. This means that a positive voltage makes the device conduct while a negative voltage is needed to shut the device off.
MOSFETS can also be constructed as P channel devices; however, N channel devices are more common since they are more easily manufactured.
MOSFETS are most commonly available as LSI circuits.
Devices combining N-channel and P-channel transistor in the same device are known as CMOS devices. Many of the gates used in this book are available as CMOS devices. The CMOS digital logic circuits compete with TTL for the digital IC market.
The primary advantages of CMOS circuits are high noise immunity and low power consumption. A list of CMOS circuit characteristics is shown in Table 8-3.
Currently, three CMOS families are widely available.
They are the 4000 series of CMOS logic circuits, which has an A and B series, and the 74C series of CMOS logic circuits. The 4000 series is the oldest and slowest family of CMOS devices. The
4000A subfamily is composed of unbuffered logic circuits, and is known as the UB series. The 4000B subfamily consists of buffered logic circuits.
The 74C series and it's subfamilies are pin and function compatible with the 7400 series of digital devices. The similarity

of function is carried through to the part number so that a 74C04 is a hex inverters IC. The 74C series is the newest and fastest
CMOS logic family and has HC, HCU and HCT subfamilies which provide high speed, unbuffered outputs, and TTL compatibility respectively.
The 74C4XXX and 74C14XXX subfamilies provide functional equivalents of CD4XXX and MC14XXX series circuits offered by RCA and Motorola respectively. Some of the 4000 family of devices have three-state outputs. This feature is primarily available with bus oriented device such as buffers and latches.
CMOS devices require 1.5 V or less for a logic zero and greater than 3.5 V for a logic one. The supply voltage can range from 3-18 V. The higher the supply voltage the greater the noise immunity, speed, and power consumption of the circuitry.
Unused CMOS inputs should be tied to ground or Vdd (supply voltage). CMOS devices have a fan-out of 50 or more.
Interfacing between TTL and CMOS is needed since the logic levels are not the same. Some typical methods of interfacing the two logic families are illustrated in Figure 8-12.

In addition to these methods, specialized level shifters are use to interface CMOS and TTL ICs.
ESD is the acronym for electrostatic discharge. ESD can easily destroy the thin insulating layer of silicon dioxide between the gate and the substrate of CMOS devices. Many newer CMOS devices have diode circuits on the inputs to suppress voltage surges and protect the transistors making the device. In spite of this, extra care should be used when handling CMOS devices.
Static voltages generated by a person walking across a waxed floor have been measured in the 4 to 15 KV range.
Voltages of this level are sufficient to destroy CMOS devices. A large number of rules for handling CMOS devices are available in the manufacturer's data sheets and CMOS data books. Most of these rules are simply taking reasonable precaution that a charged surface or person doesn't contact one of the device inputs.
This requires that all personnel and handling surfaces be grounded when CMOS devices are handled. Grounding straps are available for both working surfaces and individuals. CMOS devices should only be stored in their original container which should provide adequate static protection. Use of these types of precautions will prevent inadvertent damage to the CMOS device.
In this chapter you have studied the two major logic types available, CMOS and TTL. You have studied the switching characteristics of each type of circuit. You have learned about three-state logic and it's uses.
Interfacing CMOS and TTL ICs was discussed and some example interfaces shown. You learned about the calculation of fan-out and the use of device data sheets. The need for special handling precautions with CMOS circuits was discussed and methods presented to prevent ESD damage to CMOS devices.
1. Name the two major types of logic devices.
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174
2.
What are the logic levels for TTL circuits?
3.
Are propagation delays cumulative?
4.
Are rise times cumulative?
5.
Explain the need for ESD protection around CMOS devices.
6.
Where are open-collector outputs used?
7.
What are the states of a three-state device?
8.
What does MOSFET stand for?

In this lab exercise you will learn about TTL loading rules and some of the effects of excessive loading on TTL devices.
C.A.D.E.T.
74LS04 Hex Inverters IC
DC Voltmeter
Jumper Wires
TTL Data Book
1.
Insert the 74LS04 IC onto the breadboard and wire power and ground to the circuit.
2.
Wire LI1-LI4 together. Wire LI5-LI8 together. Wire Input switch LSI to pin 1 of the 74LS04. Connect a voltmeter set to measure about 5 VDC to pin 2 of the 74LS04.
3.
Switch LSI to LO. Turn on power.
4.
Measure and record the voltage on the output of the inverter
(pin 2).
5.
Connect the LI1-LI4 LEDs to pin 2 of the IC.
6.
LI1-LI4 should light. Repeat step 4.
7.
Connect LI5-LI8 to pin 2.
8.
All LEDs should light. Repeat step 4.
9.
Turn off power to the C.A.D.E.T. Remove the circuit from the breadboard.

What happens as the number of loads connected to a single output increases?
In this lab exercise you will study open-collector outputs. You will learn some of the characteristics of open-collector gates and examine some applications.
C.A.D.E.T.
74LS05 Hex Inverters with Open-Collector Output
IK Ohm Resistor
Jumper Wires
TTL Data Book
DC Voltmeter /DMM-02
1.
Insert the 74LS05 onto the C.A.D.E.T. breadboard and wire power and ground to the IC.
2.
Wire pin 1 to LS2 and pin 2 to LI2.
3.
Switch LS2 to LO. Turn on power.
4.
Switch LS2 HI then LO the HI again. Observe the inverter output on LI2 and record your observations.
5.
Connect a voltmeter to pin 2 and record your observation when
LS2 is cycled.
6.
Turn off power. Connect a IK ohm resistor between pin 2 and
Vcc. Switch LS2 to HI. Turn on power

7.
Cycle LSI and record your observations about LI2.
8.
Turn off power. The circuit we will wire next is a wired logic circuit made from inverters.
9.
Wire LS3 to pin 3 and pin 4 to LI2.
10.
Switch LS2 and LS3 to HI. Turn on power.
11.
Use LS2 and LS3 as inputs and LI2 as output. Record the truth table for this function.
12.
Leave this circuit connected while you answer the following questions.
I What happens when an open -collector circuit does not have a pull-up resistor?
2. What logic function is performed by the circuit in step 11?
Three-state logic will be studied in this lab exercise. The characteristics and usage of three-state devices will be learned.
C.A.D.E.T.
74365 Hex Bus Drivers with 3-State Outputs
Jumper Wires
TTL Data Book
DC Voltmeter/DMM-02

5.
Use the voltmeter and LI2 to observe the circuit output. Use LS3 and LS2 as the control and data inputs.
6.
Leave the circuit connected while you answer the following questions.

In this lab exercise you will study interfacing between TTL and
CMOS circuits.
C.A.D.E.T.
74LS04 Hex Inverters IC TTL
TC4049 Hex Inverters IC CMOS
74LS00 Quad 2-Input NAND IC TTL
MC4011 Quad 2-Input NAND IC CMOS
(2) IK Ohm Resistors
Jumper Wires
TTL Data Book
CMOS Data Book
1.
In the first part of this laboratory, you will interface CMOS outputs to TTL level inputs. Use caution when handling
CMOS circuitry to avoid destroying the gates. Wear a grounding strap or ensure that all static charges are dissipated to ground before handling CMOS devices.
2.
Place the 401 IB and the 74LS04 on the C.A.D.E.T. breadboard.
Wire power and ground to both circuits.
3.
Wire the circuit shown in Figure 8-13. Wire all unused gate inputs to ground.
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4. Switch LSI and LS2 to LO. Turn on power. Use LSI and LS2 as inputs and LI1 as the output. Observe and record the truth table for this circuitry.
5. Turn off power. Remove the circuit on the breadboard and place 74LS00 and 4049B ICs onto the breadboard. Wire power and ground to these ICs. Wire the circuit shown in
Figure 8-14. Wire all of the unused CMOS gate inputs LO.
6. Use LSI and LS2 as inputs and LI1 as the output. Determine the truth table for this circuit and record it. Leave the circuit assembled while answering the following questions.
1.
What is the function of the resistors in steps 3 and 5?
2.
Name two advantages of CMOS logic.