Clocked Storage Elements
MODULE 5
Chapter 7
Outline
 Background
 Timing, terminology, classification
 Static CSEs
 Latches
 Registers
 Dynamic CSEs
 Latches
 Registers
Clocked Storage Elements
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FSM with Positive Edge Triggered
Registers
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Store a temporary value, remember a state
Separate the past, current, future
Typically controlled by clock.
May have load signal, etc.
y is created by:
y
In CMOS,, memory
 capacitance (dynamic);
 feedback (static).
 Also see http://en.wikipedia.org/wiki/Flip-flop_(electronics)
 CSEs/Flip-flops provide memory/state
 VLSI uses predominantly D-type flip-flops
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Memory elements





§ 7.1
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D-Latch
Variations in memory elements
 Form of required clock signal.
 How behavior of data input around clock affects
the stored value.
 When the stored value is presented to the output.
 Whether there is ever a combinational path from
input to output.
 Noise sensitivity on input and output
…
[Taskin, Kourtev & Friedman, The VLSI Handbook]
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1
D-Register
Latches vs. Registers
Terminology of book
(more commonly known as D-Flip-Flop)
Latch
Register
Level-sensitive
Edge-triggered
Transparent when clock
is active
Input and output isolated
p g on 0  1 clock:
Sampling
positive edge triggered
Clock active high:
positive latch
Sampling on 1  0 clock:
negative edge triggered
Clock active low:
negative latch
Safer
Faster, smaller
[Taskin, Kourtev & Friedman, The VLSI Handbook]
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7
Timing Metrics Reminder
tc-q
tsu
thold
tplogic
tcd
T
: delay from clock (edge) to Q
: setup time
: hold time
: worst case propagation delay of logic
: best case propagation delay
(contamination delay)
T  tc-q + tplogic + tsu
: clock period
t
+t
t
cdregister
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cdlogic
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Static vs. Dynamic Memory Elements
Static
Dynamic
Operate through positive
feedback
Store charge on
(parasitic) capacitor
Preserve state as long as
power is on
Charge leaks away (in
milliseconds)
Can work when clock is
off
Clock must be kept
running (for periodic
refresh)
More robust
Faster, smaller
hold
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Positive Feedback: Bi-Stability
Static CSEs / Flipflops
Vi1
Vo1 =V i2
Vo2
V
o1
Vi2 = Vo1
 Latches
 Registers
Vi1
Vi2 = Vo1
Large part of literature talks about
Clocked Storage Elements
Are called Flip-Flops in book
Vo2
A
C
 Loop-gain in A,B <<1
 A,B: stable points
 Loop-gain in C >> 1
 C: meta-stable point
§ 7.2.1
B
Vi1 = Vo2
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2
Meta-Stability
SR-Latch
S
>1
Vi2= Vo1
Vi2= Vo1
S
B
R
S
S

&
Q
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D
RCK
&
Q
R
Q
Q
Q
1
0
0
Q
0
1
0
S
R
Q
Q
1
0
1
0
1
1
0
0
Q
1
0
1
Q
0
1
1
R
forbidden
forbidden
 Construction of D-latch
 D-latch most common in VLSI
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VDD
S
Q
R
Q
R
&
&
Q
&
Q
&
Q




Naïve implementation
16 transistors
D latch requires 9xN, 9xP
Master-slave D-register
needs 18xN, 18xP
 Larger area, cost, power
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M4
Q
Q
&
&
Q

M6
M1
S
M5
M8
M3

M7
R
 = CK
 Save 6 PMOS, 2 NMOS transistors
 D-latch requires 7 x N, 3 x P (instead of 9xN, 9xP)
{TPS}:
15
Is this a ratioed design or not?
Does it consume static power?
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Sizing for ‘Set’ Action
 M3-M4 form conventional inverter
 Model M5-M6 as one equivalent (double
length) transistor M56
 Assume Q = 0  M1 is off, M2 is on
 M2-M56 operate like ratioed pseudo
NMOS inverter
 Latch switches when M56 pulls input of
M3-M4 below their switching threshold
(assume VDD/2)
 Positive feedback amplifies switching
 M2 and M56 both in velocity saturation
around VQ = VDD/2
M2
Q
CK
Q
S
S
Q
0
0
1
1
CMOS Clocked SR-Latch
S
&
Q
R
0
1
0
1
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Q
R
R
R
S
Q
>1
>1
S
Q
S
§ 7.2.5
Clocked SR-Latch
S
S
QQ
&
R
Vi1= Vo2
 Gain should be larger than 1 in the transition region
 Smaller than 1 in stable region
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QQ
Q
R

Vi1= Vo2
>1
R
C
QQ
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YES
NO
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Sizing for ‘Set’ Action
VDD
M2
Q

M6
M1
S
M5
M4
Q
M8
M3

M7
R
2

VDSATp

V2
W  
W  

k'n    VDD  VTn VDSATn  DSATn   k'p     VDD  VTp VDSATp 
2 
2 
 L 5 6 
 L  2 
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3
SR Latch Timing
Multiplexer-Based Latches
VDD
M2
M4
Q
Q

M6
M1
S
M5
M8
M3

M7
R
CLK
Restoration
IN
CLK
Multiplexer
§ 7.2.2
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Recirculating latch
Pass Transistor Latch
 Tiny
 Low clock load
2
2






 Quasi-static, static on one phase
 Feedback restores value
 Requires 4 x N, 4 x P, minimum size
(compare 7 x N, 3 x P, non-minimum size)
 1 and 2 inverse but should be non-overlapping
 Definitely not ideal, because… {TPS}
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D
Q
Used in 1970’s
[“Latch Design” slides based on Weste & Harris],
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Latch Design
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Latch Design
Transmission gate
 No Vt drop
Inverting buffer / Basic Dynamic Latch
 Restoring
 No backdriving
X
D
 Fixes either

D
Q
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Q
 Output noise sensitivity
 Or
O diffusion
diff i input
i
t

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
Vt drop
nonrestoring
t i
backdriving
output noise sensitivity
dynamic
diffusion input
Let’s explore TG/PG based latch designs
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 Requires inverted clock
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Latch Design
1
1
Mux-based latches much more common in modern dig. IC’s
 Inverted output
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D
Q
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4
Noise Sensitivity
Dynamic Latch
Diffusion Input Noise Sensitivity
 Noise on input can drop node
below VT
“0”
 TG NMOS turns on, and X can
discharge if it was a “1”
 Similar problems for
Vin > VDD
 Storage capacitance comes primarily from inverter gate
capacitance.
 Setup and hold times determined by transmission gate—
must ensure that value stored on transmission gate is solid.
 Stored charge leaks away
 Duration of stored value being good depends on
technology
 Worst conditions during burn-in (High VDD, high Temp).
 Modern technologies (almost) mandate static latches.
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Latch Design
Q
X
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Latch Design
Buffered input
 Fixes diffusion input
 Noninverting

X
D
 Static latches are now essential
because of leakage
X
< -VT
Output Noise Sensitivity
 State node X is exposed
 Noise spike on output can
corrupt the state
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Tristate feedback
 Static
 Backdriving risk
Coupling Noise
and Supply Noise
Q
X
D



Q



 If only during burn-in
(@ high VDD, T)



=

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
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Latch Design
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Latch Design
Buffered output
Widely used in standard cells
Datapath latch
(only use in noise-controlled environments)
 Smaller

 Faster
Q

X
D
 No backdriving
 Very robust (most important)


 Unbuffered input
 Rather large
 Rather slow (1.5 – 2 FO4 delays)
 High clock loading

Q
X
D



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5
Registers
Latch Designs can Suffer from
Race Problems
t
 Not transparent—use multiple storage elements
to isolate output from input.
 Master-slave, edge triggered principle
loop
t

1
D
Q

Q
master
t
slave
D
Q
Signal can race around during 

§ 7.2.3
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Master-slave operation
master
slave
D

 = 0:
 master latch is disabled;
 slave latch is enabled,
Q
 but master latch output is stable,
 so output does not change.
 = 1:
aste latch
atc is
s enabled,
e ab ed,
 master
 loading value from input;
 slave latch is disabled,
 maintaining old output value.
 = 1  0:
 Slave latch copies current value of
master, and master stops changing
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www.play-hookey.com
l h k
clickable
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Transistor Level Master Slave
Positive Edge Triggered Register
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Set-up Time Simulation
 Robust Design
 Can eliminate I1 and I4, however, they make design
more robust (avoid charge sharing, robust input)
(see next)
Slightly smaller delay
between D and CLK
 High Clock Load (8 x)
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6
Ratioed Reduced Clock Load
Register
Simple Master-Slave Register
Clock phase overlap is important design problem
CK1
CK2
CK2=1
CK1=1
 Similar problem for 0-0 overlap




I2 and I4 are small, even long
Lower clock load
Increased design complexity
Reduced robustness (reverse conduction / backdriving)
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Dynamic Edge Triggered Register
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Clocking and CSE problems
§ 7.3.1
tT1
approximately zero
tI1 + tT2 + tI3
tsu
thold
tcq
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 Clock overlap with multiple phases
great problem in view of clock skew
 Power – in some cases, around 50% of total power
 Delay – setup time, clk-to-Q, ..
 Robustness
 Noise-sensitivity of element,
specifically for dynamic elements
Next: advanced CSEs to combat some of the above
toverlap 0-0 < tT1 + tI1 + tT2 Prevent race through T1, I1, T2
thold
> toverlap 1-1
Enforce hold-time constraint
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Clocked CMOS Register – insensitive to overlap
VDD
M2
M6
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C2MOS Latch
Other Latches/Registers: C2MOS
VDD
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VDD
Clocked CMOS Latch
M2
CLK
M4
CLK
M3
CLK
M8
CLK
M7
X
D
CL1
=
Q
CL2

=
CLK
M4
CLK
M3
M1
M1
Master Stage
M5
Slightly … Slower
Slightly … Smaller
Slave Stage
“Keepers” can be added to make circuit pseudo-static
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Insensitive to Clock-Overlap
Other Latches/Registers: TSPC
True Single Phase Clocking
VDD
M2
CLK
0
CLK
M4
0
VDD
VDD
VDD
M6
M2
M6
Q
D
1
M1
In
X
M5
CLK
In
Out
Positive latch
(transparent when CLK= 1)
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VDD
VDD
Q
Q
Q
CLK
CLK
X
M2
CLK
CLK
M1
In1
PDN
M9
Y
D
CLK
VDD
M6
In2
Q
CLK
VDD
CLK
M3
In
44
Alternative TSPC Register
VDD
PUN
Negative latch
(transparent when CLK= 0)
TSPC register: positive and negative latch in cascade
43
Including Logic in TSPC
In1
CLK
M5
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VDD
CLK
M7
1
Output always decoupled from input, even with overlap
VDD
VDD
Out
CLK
(b) (1-1) overlap
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VDD
Q
M3
M1
(a) (0-0) overlap
VDD
X
M8
X
D
VDD
M5
CLK
M4
M8
M7
In2
Clk = 0
Example: logic inside the latch
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D sampled on X
Clk = 1
45
Falling X can’t charge Y Y is stable
L1
L2
D Q
Clk
Clk
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VDD
VDD
M3
M6
CLK
D
CLKG
M2
CLKG
VDD
M1
MP
M5
CLKG
X
MN
M4
D Q
(a) register
Clk
(b) glitch generation
Clk
CLK
Clk
Master-Slave Latches
46
Q
L
Data
Y sampled on Q
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Pulsed Latches
Remember: Use registers to avoid race-around problem.
Two latches in cascade: master-slave
Alternative: Pulse triggered latches
D Q
Y ↑ doesn’t make Q’ ↓
Evaluate based on X
Pulse-Triggered Latches
An Alternative Approach
Data
Precharge Y to VDD
Clk ↑
AND latch
CLKG
Pulse-Triggered Latch
(c) glitch clock
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8
Pulsed Latches
Hybrid Latch-FF Timing
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
3.0
P3
x
M3
D
2.5
Q
2.0
M6
P2
M2
Volts
P1
CLK
M5
D
Q
1.5
1.0
VDD
M1
CLKD
0.5
M4
CLKD
CLK
0.0
20.5
0.0
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0.2
0.8
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More Topics







0.4
0.6
time (ns)
1.0
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Summary
 Background
Reset and enable inputs
Scan-enabled CSEs
Sense-amplifier based CSEs
Double-edge triggered
g sleep
p mode
Low-leakage
(Ultra) Low voltage
Soft-error / SEU tolerance
 Timing, terminology, classification
 Static CSEs
 Latches
 Registers
 Dynamic CSEs
 Latches
 Timing of CSEs
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 Registers
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9