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SSCS
IEEE SOLID-STATE CIRCUITS SOCIETY NEWS
Spring 2007
Vol. 12, No. 2
www.ieee.org/sscs-news
The Origins of the Integrated Circuit
Robert Noyce
Jack Kilby
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Editor’s Column
W
elcome to
the Spring
2007 issue
of the Solid-State Circuits Society Newsletter! We appreciate all
of your feedback on
our first two issues that present The
Technical Impact of Moore's Law and
The Impact of Dennard’s Scaling
Theory. Thank you for your support
of our efforts! Please refer to the two
Letters to the Editor in this issue for
comments from our readers. This
Spring 2007 issue is the second of
four issues that SSCS plans to publish annually (one each in Winter,
Spring, Summer, and Fall).
The goal of each issue is to be a
self-contained resource with background articles (that is, the ‘original
sources’) with current articles by
experts who describe the current
state of affairs in technology and the
impact of the original papers and/or
patents.
This issue contains two Highlights
articles:
IEEE Solid-State Circuits Society AdCom
President:
Richard C. Jaeger
Alabama Microelectronics Center
Auburn University, AL
jaeger@eng.auburn.edu
Fax: +1 334 844-1888
Vice President:
Willy Sansen
K. U. Leuven
Leuven, Belgium
Secretary:
David A. Johns
University of Toronto
Toronto, Ontario, Canada
Treasurer:
Rakesh Kumar
Technology Connexions
Poway, CA
Past President:
Stephen H. Lewis
University of California
Davis, CA
Other Representatives:
Representative to Sensors Council
Darrin Young
Representative from CAS to SSCS
Domine Leenaerts
Representative to CAS from SSCS
Un-Ku Moon
Newsletter Co-Editors:
Mary Y. Lanzerotti
IBM T.J. Watson Research Center
myl@us.ibm.com
Fax: +1 914 945 1358
Lewis Terman
IBM T. J. Watson Research Center
terman@us.ibm.com
Fax: +1 914 945-4160
Elected AdCom Members at Large
Terms to 31 Dec. 07:
Bill Bidermann
David Johns
Terri Fiez
Takayasu Sakurai
Mehmet Soyuer
Terms to 31 Dec. 08:
Wanda K. Gass
Ali Hajimiri
Paul J. Hurst
Akira Matsuzawa
Ian Young
Terms to 31 Dec. 09:
John J. Corcoran
Kevin Kornegay
Hae-Seung (Harry) Lee
Thomas H. Lee
Jan Van der Spiegel
Region 8 Representative:
Jan Sevenhans
Region 10 Representative:
CK Wang
Chairs of Standing Committees:
Awards
David Hodges
Chapters
Jan Van der Spiegel
Education
CK Ken Yang
Meetings
Bill Bidermann
Membership
Bruce Hecht
Nominations
Stephen H. Lewis
Publications
Bernhard Boser
For detailed contact information, see the Society e-News: www.ieee.org/portal/site/sscs
For questions regarding Society business, contact the SSCS Executive Office.
Contributions for the Summer 2007 issue of the Newsletter must be received by
8 May 2007 at the SSCS Executive Office. A complete media kit for advertisers is
available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS.
Anne O’Neill, Executive Director
IEEE SSCS
445 Hoes Lane
Piscataway, NJ 08854
Tel: +1 732 981 3400
Fax: +1 732 981 3401
Email: sscs@ieee.org
2
IEEE SSCS NEWS
Katherine Olstein, SSCS Administrator
IEEE SSCS
445 Hoes Lane,
Piscataway, NJ 08854
Tel: +1 732 981 3410
Fax: +1 732 981 3401
Email: k.olstein@ieee.org
(1) “0-60 GHz in Four Years: 60
GHz RF in Digital CMOS,” by
Ali Niknejad, Associate Professor of Electrical Engineering
and Computer Sciences at the
University of California at
Berkeley, CA.
(2) “Out of the Park Home Runs:
Legendary Digital Circuits that
Tracked Technology Scaling,”
by Kerry Bernstein, Senior
Technical Staff Member at IBM
T. J. Watson Research Center in
Yorktown Heights, NY;
The theme of this issue is “The
Origins of the Integrated Circuit.”
Two feature articles discuss this
theme:
(1) “The (Pre-) History of the Integrated Circuit: A Random
Walk,” by Thomas Lee at Stanford University;
(2) “Crystal Fire: The Invention,
Development, and Impact of
the Transistor,” by Michael Riordan at the University of California at Santa Cruz and Lillian
Hoddeson at the University of
Illinois at Urbana-Champaign.
We reprint these original patents
in this issue:
(1) W. Shockley, “Semiconductor
Amplifier Patent.” U. S. Patent
2,502,488 (page 1 and first figure);
(2) J. Bardeen et al., “Three-Electrode Circuit Element Utilizing
Semiconductive Materials,” U.
S. Patent 2,524,035 (page 1 and
Figs. 1, 1A, 2, 10, 11, 12);
(3) R. N. Noyce, “Semiconductor
Device-and-Lead Structure,” U.
S. Patent 2,981,877;
(4) J. A. Hoerni, “Method of Manufacturing Semiconductor Devices,’
U. S. Patent 3,025,589 (page 1
and Figures 1-10.
(5) J. S. Kilby, “Miniaturized Electronic Circuits,” U. S. Patent
3,138,743.
Thank you for taking the time to
read the SSCS News. We appreciate
all of your comments and feedback! Please send comments to
myl@us.ibm.com.
Spring 2007
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Photo of Robert N.
Noyce (left) courtesy
of Intel.
Spring 2007 Volume 12, Number 2
Photo of Jack Kilby
courtesy of Texas
Instruments.
Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Letters to the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
RESEARCH HIGHLIGHTS
0-60 GHz in Four Years: 60 GHz RF in Digital CMOS . . . . . . . . . . . . . . . . . . . . .5
“Out-of-the-Park Home Runs” Legendary Digital Circuits that Tracked
Technology Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
TECHNICAL LITERATURE
8
The (Pre-) History of the Integrated Circuit: A Random Walk . . . . . . . . . . . .16
Crystal Fire: The Invention, Development and Impact of the Transistor . . .24
PATENTS
12
Semiconductor Amplifier (U.S. Patent No. 2,502,488) . . . . . . . . . . . . . . . . . . . . . . .30
Three-Electrode Circuit Element Utilizing Semiconductive Materials
(U. S. Patent No. 2,524,035) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Semiconductor Device-and-Lead Structure (U. S. Patent No. 2,981 ,877) . . . . . . . .34
Method of Manufacturing Semiconductor Devices (U. S. Patent No. 3,025,589) 41
Miniaturized Electronic Circuits (U. S. Patent No. 3,138, 743) . . . . . . . . . . . . . . . . . .44
PEOPLE
58
Asad Abidi, Mark Horowitz and Teresa Meng Elected to U. S. National
Academy of Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Yannis P. Tsividis and Hugo De Man Receive IEEE Field Awards at ISSCC . . . . . . . . .56
SSCS Nominees Recognized at ISSCC Plenary for Elevation to Fellow . . . . . . . . .57
Huijsing, Makinwa, and Pertijs Receive JSSC 2005 Best Paper Award . . . . . . . . . .60
Best Student Design Awards Presented at ISSCC 2007 . . . . . . . . . . . . . . . . . . . . . .62
Lanzerotti Honored by IEEE Women in Engineering Society of New York . . . . . . . .64
New Senior Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Tools: How to Write Readable Reports and Winning Proposals . . . . . . . . . . . . . . .65
CHAPTER NEWS
New SSCS Chapters in Tainan and South Brazil . . . . . . . . . . . . . . . . . . . . . . . . . . .66
A Chapter is Born in Southern Taiwan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
CONFERENCES
60
Classic Books Remain Best Sellers at ISSCC 2007 . . . . . . . . . . . . . . . . . . . . .69
Digital and Analog Designers Spar at ISSCC Evening Panel Session . . . . . . .71
VLSI Circuits Symposium Celebrates 20th Anniversary in June . . . . . . . . . . .72
Persico and Streit to Speak at RFIC Symposium in Honolulu . . . . . . . . . . . .75
NEWS
66
Spring 2007
IEEE ABET Accreditation Criteria and Procedures in Spanish . . . . . . . . . . . . . . . .10
IEEE History Center Adds 75 Oral Histories to Web Site . . . . . . . . . . . . . . . . . . . . . .16
IEEE Expert Now Courses Available to Members Through IEEE Xplore . . . . . . . . .29
CEDA Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
IEEE SSCS Focuses on Strategic Planning in 2007 . . . . . . . . . . . . . . . . . . . . . . . . . .77
Call for Nominees for SSCS Administrative Committee Election . . . . . . . . . . . . . .79
IEEE Partners with Knowledge Master, Inc. to Offer Microelectronics in
Mandarin Chinese . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Call for Nominations: SSCS Predoctoral Fellowships 2007-2008 . . . . . . . . . . . . . . .81
Presubmission Professional Editing Services for IEEE Authors . . . . . . . . . . . . . . . . .82
IEEE SSCS NEWS
3
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Letters to the Editor
Dear Mary Lanzerotti and Lew Terman,
I got copies of the SSCS newsletter (the first two full color
printed versions of SSCS newsletter: Vol. 20 (3), Sept 2006
and Vol. 21 (1), Winter 2007) from the 2007 ISSCC conference site in San Francisco. When I returned to my office, the
Winter 2007 issue was also waiting for me on my office desk.
I read both of these two full color issues. I really enjoyed my
reading. I have to say this is the best newsletter in many professional societies I have ever read! Congratulations! Mary
and Lew, you really did a great job for members of SSCS. I
read most of the articles and news for many hours during
my whole holiday period of Chinese Lunar New Year.
I have found some mistakes in the newsletter, which
I would like to feed back to you for your information:
[1] On the cover and page 3, the winter issue of 2007
should be Vol. 21 instead of Vol. 12? Since the Sept
2006 issue is Vol. 20.
Editor’s Note: The September 2006 issue should have
been Vol. 11.
[2] In the Editor's Column of both issues, Mary told us
that the newsletter will be issued 4 times per year
for the first time in 2007, but in the back cover,
there is a pink block, in there it is still said the
newsletter is published 3 times per year. I think
starting from this first issue, this should be updated as Editor’s Column claimed.
Editor’s Note: The back cover has been corrected to
reflect our quarterly schedule.
Thank you again for such a nice magazine, I am
looking forward to enjoying more in the future.
Best Regards,
C. Y. Lu
Ph. D., IEEE Fellow, APS Fellow
Chairman & CEO, Ardentec Corporation,
HsinChu, Taiwan, ROC
Senior VP and CTO, Macronix International Co.,
Ltd, HsinChu Science Park, HsinChu, Taiwan, ROC
cy.lu@ardentec.com
oxide surface of the wafer resulting in a substantial
improvement in transistor reliability and manufacturability.
Of particular interest to Bob Noyce*, the oxide surface could be used for depositing circuit interconnects.
The resulting semiconductor junctions were “pure”
resulting in a remarkable conformity to the then recently described Ebers and Moll model.
The measurements by Don Farina on the small geometry 2N1210 planar transistor over several decades of
Collector current showed conformity to the Ebers and
Moll model even though its low Inverse Alpha was not
considered suitable in their original paper. Importantly,
the consistency of these transistors with this model
made it possible to use mathematical expansion of the
Ebers and Moll model to design the circuitry of this first
compatible family of monolithic logic circuits.
It is worth noting that the required Fan-In/Fan-Out
parameters had already been established in the development of several military digital computers at Sperry
Gyroscope Company.
The photomicrograph shows the first pass at isolating
the various circuit components, another important requirement for the successful development of monolithic integrated circuits. This approach was to etch apart semiconductor islands supported by the surface oxide then back
filling with plastic. It became immediately obvious that this
technique would not meet the -55 to + 125 degrees, Centigrade military temperature requirements or thermal cycling.
As shown the chips were chemically etched apart which
carried the evident manufacturing problems. Meanwhile,
Jean Hoerni developed diffused isolation which became
the production method. While the long backside diffusion
made the silicon wafers more brittle, leading to easy breakage in manufacturing, the Integrated Circuits were manufactured as multiple instances on silicon wafers which were
scribed and broken into chips in much the same fashion as
individual transistors were batch fabricated.
At about this time an IBM paper was published in the
“Proceedings of the IRE” on “Test to Failure”. Vic Grinich*,
Dear Ms. Lanzerotti,
V. P. Engineering, endorsed subjecting the Micrologic InteI was fascinated by the photomicrograph of the first grated Circuits to a similar “test to failure” reliability regimonolithic (one rock) integrated circuit produced by men. While all of the prior work on military computers
Fairchild Semiconductor, which I date to about October- noted above included transistor qualification tests and life
November 1959 Winter; 2007 issue, p. 10. This was the “F” tests by the Sperry Gyroscope Standards Laboratory, and
element, a Set-Reset Flip-Flop. The connection pads temperature and voltage margin tests, all were by and large
shown, clockwise from the top were: Ground, Set, F’, “ad hoc”. Using TO-5 cans made it possible to use the man+Supply, F, and Reset. The load resistors are the dark stripe ufacturing expertise already developed for transistors. Folacross from F’ to +Supply to F. Not visible were the series lowing the lead of the “Test to Failure” paper we were able
resistors to the base of each transistor to reduce the “cur- to quickly and convincingly arrive at mechanical, thermal,
rent hogging” that was a problem with DCTL configura- and electrical screens which assured the quality of the mantions. The planar technology invented by Jean Hoerni*, ufacturing process and the products, with two exceptions:
had three important attributes:
The detergent bomb used in the gross leak test could
The Collector-Base Junction was formed under the not be used since the circuit resistances were low and
therefore a device could pass with a small amount of
*Founders of Fairchild Semiconductor, Division of detergent in the TO-5 can which in turn could damage
Fairchild Camera and Instrument Co.
continued on page 10
4
IEEE SSCS NEWS
Spring 2007
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RESEARCH HIGHLIGHTS
0-60 GHz in Four Years: 60 GHz RF in Digital CMOS
Ali M. Niknejad, Electrical Engineering and Computer Science Department, University of California, Berkeley, CA, niknejad@eecs.berkeley.edu
C
MOS transistors are getting smaller and cheaper,
and we have witnessed a revolution in computation, signal processing, and communication
using this wonderful technology. As transistors have
gotten smaller, they have also gotten incredibly fast.
Our mission at the Berkeley Wireless Research Center
(BWRC) was to tap into this speed to realize the fastest
possible communication circuits operating in the 60
GHz band.
Silicon-based circuits operating at 60 GHz, especially in CMOS technology, represented a huge leap in the
operating frequency of silicon technology. At the time,
in early 2001, most researchers were focusing on the
spectrum from 1-5 GHz, with a few isolated research
groups pushing circuits up to 24 GHz. Our suggestion
to exploit 60 GHz with CMOS even seemed comic to
some observers. Fortunately DARPA funded this early
stage research project under the umbrella of the TEAM
program (Technology for Efficient, Agile Mixed-Signal
Microsystems), a program that supported a broad
range of research to advance silicon technology into
the mm-wave spectrum. Many of our industrial partners at BWRC also thought this was a worthy effort,
something that would be relevant to industry in 5-10
years. Our original plan was to take three steps to 60
GHz, starting at 20 GHz in 180nm CMOS, 40 GHz in
130nm CMOS, and finally 60 GHz in 90nm CMOS.
Midway through our effort we decided to leapfrog to
60 GHz directly using 130nm technology. This article
chronicles our efforts—and the challenges involved—
to reach 60 GHz.
Why 60 GHz?
Given the many challenges to working in this frequency, what are the benefits? The availability of a
large block of a nearly universal unlicensed spectrum
in this frequency band is an obvious motivation, with
7 GHz available in the U.S. and at least 3-4 GHz in the
intersection of the set of all international standards.
High bandwidth translates into high throughput, easily supporting Gb/s data wireless communication data
rates with low complexity modulation schemes. There
is a plethora of applications crying out for high bandwidth, especially in the domain of personal area networks (PANs). Data transfer from high resolution digital cameras, transfer of music and video and other
multimedia content between a computer and a
portable device, such as the ubiquitous iPod, are
some obvious examples. Other emerging applications
include transmission of uncompressed video between
a multimedia device and an HD flat screen television
Spring 2007
or projector. Taking the signals a bit further, we see a
WLAN counterpart to gigabit Ethernet. If we can go
up to 77 GHz, then there are applications in automotive radar for collision detection and automatic speed
control and mm-wave imaging for security.
Shannon’s theorem tells us that channel capacity is
proportional to bandwidth and a logarithmic function
of SNR. On the bandwidth front we have a big advantage over low GHz communication standards. This
allows us to utilize relatively inefficient modulation
schemes and still realize large data rates, a tradeoff we
can make in the complexity of the baseband architecture. High data rates with smaller bandwidths (e.g.
WLAN at 2.4 GHz), requires complex modulation
schemes to squeeze as many bits/Hz as possible.
There is also 7 GHz of untapped bandwidth in the
UWB spectrum from 3-10 GHz. In contrast to the 60
GHz band, in UWB systems the FCC regulations limit
the transmit power to an average of about 0 dBm.
There is also a great amount of complexity in a UWB
radio, either in the form of FFTs in an OFDM
approach, or in the form of long correlators to “pick
a needle out of a haystack,” or to find a weak signal
in a sea of noise and interference. In contrast, in the
U.S. the maximum power transmission in the 60 GHz
band is 40 dBm, or four orders of magnitude higher
than UWB. Power and bandwidth are good motivators for a communication system.
Fear of 60 GHz
With these motivations, we had to overcome some
consternation with 60 GHz. We were inundated with
questions and doubts about mm-wave circuits in silicon and wireless propagation in this frequency band.
In fact, we were certainly not the first to try to build
mm-wave circuits and systems. The Japanese were
early innovators in this field and demonstrated working
transceivers in III-V technologies [1]. Many of the questions about the validity of lumped circuit theory at mmwave frequencies are easily answered if you realize
that CMOS transistors are still a tiny fraction of the
wavelength, and can be treated as lumped circuits. The
interconnect and matching circuits must be treated as
distributed circuits, but this is a problem that was
solved decades ago by microwave engineers. The
important question is whether the conductive silicon
substrate will in some way be a big deterrent to realizing circuits at 60 GHz. We shall show in this article that
this is not the case and in fact very good active and
passive devices have been demonstrated by BWRC and
other groups working on silicon mm-wave circuits.
IEEE SSCS NEWS
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RESEARCH HIGHLIGHTS
Signal propagation at 60 GHz has a higher path
loss, and waves experience higher attenuation when
traveling through materials in the mm-wave band. In
particular, the oxygen absorption spectrum occurs
precisely in this frequency range, one of the reasons
this band is relatively unused for long-range communication. Furthermore, given the low supply voltages
of nanoscale CMOS (and the relatively high noise figure), we don’t expect to be able to transmit inordinate
power levels to overcome the path loss at 60 GHz. So
we turn to another strength of CMOS, and that is the
capability to integrate a large number of transceivers
on a die. A phased antenna array can overcome the
limitations of CMOS by improving the antenna gain,
and hence effective radiated power. Antenna elements are small in the mm-wave spectrum and can be
integrated into the package. This in turn allows beam
forming, which improves the antenna gain and
increases spatial diversity. A side benefit is resilience
to multi-path fading and interference. Finally, and
most importantly, an antenna array allows spatial
power combining, which simplifies the design of the
PA considerably. The vision for our system is captured
in Fig. 1, which shows several transceivers incorporating electronic phase shifters to form a smart antenna array.
Fig. 1.
The Phased “Smart” Antenna Array
The antenna array solves the fundamental problem
with higher frequency operation: path loss. Friis’s
equation tells us that the path loss drops with smaller
wavelengths (1/λ2). For instance, if we employ a simple dipole antenna with modest gain, the antenna
capture area is proportional to the wavelength
squared (λ2), and so we capture a smaller fraction of
the radiated power P which is divided over a sphere
of surface area 4πR2, resulting in a (λ/R)2 term in the
equation. This loss, though, can be overcome by
employing a larger area, such as a dish antenna, at the
cost of directionality. The antenna gain is in fact to
first order inversely proportional to the solid angle
beam width. For a mobile system we need a way of
moving the antenna beam dynamically, and this is
easily done in an antenna array by employing phase
shifters in the transmitter and receiver, which intro-
6
IEEE SSCS NEWS
duce just enough delay (2πdcosθ /λ) in each element
(spacing d) so that signals arriving at some angle do
so perfectly in phase. At the receivers the signals are
summed together to improve the SNR of the receiver,
and in the transmitter the signals sum to increase the
radiated power. Another benefit to a directional
antenna in the receiver is that it reduces multipath
propagation since signals arriving through paths other
than the LOS path arrive from different directions, and
thus are potentially attenuated by the nulls in the
antenna pattern. This simplifies the baseband of the
transceiver, allowing simpler equalization and lower
resolution ADCs to be employed. For the transmitter
the design of the power amplifier is simplified considerably. Not only is the total power divided by the
number of elements, but the increased antenna gain
allows one to even drop the transmit power more
than 1/N. To replace an isotropic transmitter with 100
mW with an array of 10 elements, we can transmit
power levels of a few mW per element and utilize the
antenna gain and spatial power combining to realize
an effective power of 100 mW transmitted in a given
direction.
Devices and Modeling
One of the biggest challenges in moving from low
GHz frequencies to the mm-wave band is the lack of
infrastructure, CAD tools, and models. Measurement
equipment requires a large investment of capital,
training, and finesse in making precise and accurate
measurements. Noise measurements are particularly
difficult at these frequencies, with a handful of groups
around the world that have expertise at noise measurements beyond 26 GHz. We upgraded our measurement facilities at BWRC to support small-signal,
large-signal, and noise circuit measurements up to 65
GHz and then again up to 110 GHz. We have characterized process nodes starting at 180nm down to
90nm through extensive test chips with building block
devices such as MOS transistors, transmission lines,
custom MIM capacitors, resistors, MOS capacitors, resonators, and inductors. By characterizing these
devices, we were able to build a library of active and
passive devices for mm-wave design.
Characterization of transmission lines with different
gap spacing allowed us to characterize the high frequency losses in the Si substrate and dielectric layers
to allow new structures to be simulated with a fullwave electromagnetic simulator. Transmission lines
are characterized by their characteristic impedance Z0
and the complex frequency dependent propagation
constant y (w). We make extensive use of transmission lines—as opposed to spiral inductors—since they
are length scalable, allowing us to precisely design
small reactance values to form matching circuits at 60
GHz. Inductors are more difficult to simulate, espe-
Spring 2007
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RESEARCH HIGHLIGHTS
cially since the lead inductance can become a substantial fraction of the circuitry. Moreover, transmission lines have well controlled field patterns with a
nearby ground return path, which limits the amount
of substrate coupling. Short sections of co-planar transmission lines act as inductors with Qs approaching 30
at 60 GHz, allowing high Q resonators. Varactors,
though, have small Q, making large tuning resonators
particularly challenging at mm-wave frequencies.
A typical transistor measurement is shown in Fig. 2,
where we plot the simulated and measured current
gain (H21), maximum stable gain (MSG), and unilateral gain (U) of the device.
into a larger external stabilizing termination (until the
stability factor K=1). On the other hand, if we stabilize the device through feedback, then the gain
increases to a limit given by Mason’s Unilateral Gain.
Incidentally, the noisiness of the U data is also a good
indicator of the quality of the measurements, since
any small error in the measurement of device loss
translates into a large variation of U. Conventionally,
the Fmax of the device is extrapolated from the value
of U = 1 from low frequency data. The measurements
show that this is a reasonable way to extract the
device Fmax beyond the measurement capability, but a
better approach is to model the device up to high frequencies and use a model extrapolated value.
The device is modeled with an extended BSIM3
model which incorporates gate/drain/source inductance and loss and a custom substrate resistance network (Fig. 3).
Fig. 2.
Microwave devices are characterized by their Fmax,
as opposed to the Ft, since the device Ft is independent of layout and does not include the influence of
device losses. The Fmax, on the other hand, defines
the maximum frequency of activity, setting the limit
on the highest frequency that we can extract power
gain from the device. This means that amplifiers and
oscillators can only be realized below the device Fmax.
The device Fmax can be shown to rely on device parasitics through the following relation
Ft
Fmax ≈ 2 R g (g mC g d /C g g ) + (R g + r ch + R s )g d s
which shows that the device performance increases proportional to Ft, but also depends strongly on the
gate, source, and channel resistance of the device.
The role of the layout parasitics is quite dramatic, with
Fmax ranging from 0.5 Ft to nearly 2 Ft when the gate
fingers range from 8µm to 1µm. An optimized device
is biased in strong inversion with short gate fingers.
The modeled results show an excellent match to
measurements, especially in the match of U, Mason’s
Unilateral Gain, which is a strong function of device
parasitics. Since the device is only conditionally stable
at 60 GHz, its maximum stable gain is not a strong
function of the device loss, since the loss is absorbed
Spring 2007
Fig. 3.
This model is first fitted to DC curves in the bias
regions of interest, from weak inversion to strong
inversion, with particular emphasis on fitting the
device transconductance. Next the device parasitics
are varied to fit the measured S-parameters up to 65
GHz. This modeling approach is verified with largesignal measurements of device output power versus
Vgs and harmonic power measurements. A further validation of the model comes from the measurement of
non-linear circuits such as mixers and amplifier compression point. The noise of the devices is modeled
using Pospieszalski’s noise model [2], with a shortchannel excess noise factor y = 1.4. This model is able
to predict the trends of NFmin, Rn, and Yopt over bias
and device geometry reasonably well. The measured
Fmin for a 130nm is 4 dB at 65 GHz, which means that
moderately low noise amplifiers are possible.
Circuits and Building Blocks
Given a good library of active and passive devices,
the actual circuit design is relatively simple. Transmis-
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sion lines are used extensively for matching, bias, and
interconnect. Bypass and AC coupling capacitors are
used to bias and de-couple the amplifier stages. A
three-stage amplifier incorporating unconditionally
stable cascode stages was designed, fabricated and
measured. This amplifier, the world’s first 60 GHz
CMOS amplifier, was reported at ISSCC in 2004 [3].
The amplifier had a measured gain of 11.5 dB, a NF
of 9 dB, and an output compression point of +2 dBm.
A quadrature balanced mixer was designed to convert a 60 GHz RF to a 2 GHz IF signal. The mixer
schematic and layout, shown in Fig. 4-5, utilizes a
quadrature coupler to combine the RF and LO signals,
with the LO (0dBm) signal modulating the transistor
operating point to realize the -2 dB down-conversion
gain in the 60 GHz band.
60 GHz receiver front-end in a digital CMOS 130nm
process [4]. The chip micrograph is shown in Fig. 6,
which occupies an area of 3.3 mm x 1.7 mm, consumes 77 mW of power, has 12 dB of RF conversion
gain, a NF of 10.4 dB.
Fig. 6.
The free running VCO has a phase noise of -93
dBc/Hz at a 1 MHz offset. Even at this early stage,
assuming modest transmit power of 6 dBm per element in a 12-fold array, the receiver can support 1
Gb/s data rate communication over a LOS 10m range,
with 26 dB SNR at the receiver. This leaves quite a bit
of margin since 10-3 BER communication is feasible
with 10 dB SNR, but in a real system many other
sources of loss need to be accounted for.
Future of CMOS
Fig. 4.
Fig. 5.
This mixer and LNA were combined together with
other building blocks, including the VCO, LO buffer,
and frequency doubler, to realize a highly integrated
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IEEE SSCS NEWS
The future of CMOS is bright, so put on your shades.
We are now actively pursuing 90nm CMOS for 60
GHz applications and we have already demonstrated
a new device layout which achieves an extrapolated
Fmax of 300 GHz, three times the device Ft. With more
gain at 60 GHz, we can back off and consume less
power in the amplifiers. Oscillators and frequency
dividers are also less power hungry, allowing one to
lower the overall power consumption. We have
already demonstrated the world’s fastest CMOS amplifier, running at 104 GHz [5]. As the operating frequency increases, we envision new applications, with
300 GHz “THz” spectrum within the grasp of CMOS in
a few generations of technology scaling. New emerging applications include imaging for radar, security,
and medical systems. In a security application, due to
the relatively small wavelength, mm-waves provide
medium resolution imaging which can penetrate
through clothes and display potentially hidden
weapons, even non-metallic objects. In medical applications mm-waves can penetrate the skin and be
incorporated into a low resolution CAT scan. The
advantage over an X-ray system is the low non-ionizing photon energy level, which makes these tests
much safer.
Conclusion
CMOS technology continues to amaze us, with scaling
pushing the operating frequency up to 100 GHz with
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standard digital transistors. Successful circuit design
requires a combination of careful measurements and
compact modeling of active and passive devices.
Using relatively simple lumped circuit compact models of transistors and electrical models of transmission
lines, communication building blocks such as amplifiers, mixers, and oscillators have been demonstrated
in CMOS technology operating in the mm-wave band.
With further technology scaling, the performance of
these building blocks will continue to improve and the
power consumption will continue to drop, enabling a
host of new communication and imaging applications
to be realized with inexpensive CMOS technology.
Acknowledgements
This research was done in collaboration with the faculty of The Berkeley Wireless Research Center
(BWRC) , including Robert Brodersen. Moreover, two
generations of talented graduated students have contributed tremendously to the research, including
Chinh Doan, Sohrab Emami, Mounir Bohsali, Babak
Heydari, Ehsan Adabi, Bagher Afshar, and David
Sobel. This research would not have been possible
without the funding from the DARPA TEAM project
and BWRC member companies.
[1] K. Ohata, K. Maruhashi, M. Ito, S. Kishimoto, K.
Ikuina, T. Hashiguchi, N. Takahashi, S. Iwanaga,
“Wireless 1.25Gb/s transceiver module at 60GHz
Band,” ISSCC 2002, p. 298-299, 467.
[2] M. W. Pospieszalski, “On the measurement of
noise parameters of microwave two-ports,” IEEE
MTT-S IMS Digest, pp. 456-458, April 1986.
[3] C.H. Doan, S. Emami, A.M. Niknejad, R.W.
Brodersen, “Design of CMOS for 60GHz applications,” ISSCC 2004, pp. 440-538.
[4] H. Doan, S. Emami, A.M. Niknejad, R.W. Brodersen, “A 60GHz CMOS Front-End Receiver,” ISSCC
2007, pp. 190-191.
[5] B. Heydari, M. Bohsali, E. Adabi, A.M. Niknejad,
“Low-Power mm-Wave Components up to
Spring 2007
104GHz in 90nm CMOS,” ISSCC 2007, pp.200201,597.
About the Author
Ali M. Niknejad received the B.S.E.E.
degree from the University of California,
Los Angeles, in 1994, and the M.S. and
Ph.D. degrees in electrical engineering
from the University of California, Berkeley,
in 1997 and 2000. From 2000-2002 he
worked at Silicon Laboratories in Austin,
TX, where he was involved with the design and research
of CMOS RF integrated circuits and devices for wireless
communication applications. Presently he is an associate professor in the EECS department at UC Berkeley.
He is a co-director of the Berkeley Wireless Research
Center (BWRC) and also the co-director of the BSIM
Research Group. He served as an associate editor of
the IEEE Journal of Solid-State Circuits and is currently serving on the TPC for CICC and ISSCC. His current
research interests lie within the area of analog integrated circuits, particularly as applied to wireless and
broadband communication circuits. His interests also
include device modeling and numerical techniques in
electromagnetics.
See it on web TV.
Excerpts from Ali Niknejad’s CICC presentation on 60GHz
chips developed by the Berkeley Wireless Research Center can be watched on IEEE.tv using your IEEE web
account. From this URL www.ieee.org/web/membership/IEEEtv/about.html
select launch IEEE.tv from the right. The broadcast
appliance will request your IEEE web account.
After logging in select the program under CONFERENCE HIGHLIGHTS, Custom Integrated Circuits
Conference.
IEEE SSCS NEWS
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Letters to the Editor continued from page 4
technology would support a million transistors on a chip
there was some question about the usefulness of such
complexity. Among other things it was pointed out at that
conference that a single chip Doppler radar processor
would require 25 million gates. We should recall that Gordon’s more recent comments are in the context of massive
financial investments in the manufacture and distribution
of what amounts to a single “legacy” architecture. This has
been accompanied by comparable investments by others
to develop robust applications software to run on this
architecture. With 20/20 hindsight one might argue we
would have been better off starting with a multi-processor
architecture, but that ship has sailed. There is plenty of
room to develop and use a lower power per gate implementation and exploit distributed processor architectures,
but not at the low unit cost of the legacy X86. That ship
has sailed. On the other hand, all the work that Gordon
and others have done opens the way for a variety of
processor architectures and programming paradigms,
including self-organizing networks. There are, at the minimum end, fabrication resources such as MOSIS, which
support work on new circuits, structures, and architectures, again at higher unit cost.
P. P. S. Thank you for the work you are doing on this
publication.
Robert H. Norman
PO Box 1301
West Chatham, MA 02669
rhnorman@comcast.net
*Founders of Fairchild Semiconductor, Division of
February 21, 2007
Fairchild Camera and Instrument Co.
the aluminum interconnects. (We changed to a different
type of gross leak test.)
Scratches of the aluminum interconnects made during the assembly process adversely impacted reliability.
The only screen we could find was to optically inspect
the assembled devices. We later developed a glass coating to protect these interconnects.
The test-to-failure lessons immediately fed back to
transistor production. (The information from this testing
made it possible to deliver transistors to NASA Ames
Laboratory to be used in telemetry from projectiles
which were literally shot from guns into a supersonic
wind tunnel to examine the effects of hypersonic flight.)
As happens so often in the semiconductor industry,
the incredible teamwork of Jay Last*, Jean Hoerni*, Jim
Nall and Isy Haas, under Gordon Moore*, and myself,
Don Farina, Helmut Wolf and later Al Wesolowski,
Orville Baker, Dick Anderson, and Howard Bogert
under Vic Grinich*, led and inspired by Bob Noyce,
resulted in the first successful manufacture of Micrologic prior to its introduction at the February, 1960 ISSCC.
P. S. I don’t recall Gordon saying complexity would
double every two years. Recall that in the original paper,
Gordon’s curve rounded off because he could not conceive any use for such massively complex chips. In fact,
this was the subject of an Asilomar Conference shortly
afterwards. Gordon had made the statement that while the
ABET Accreditation Criteria and Procedures Now
Available in Spanish
T
he IEEE recently teamed with ABET, Inc., the recognized accreditor for college and university programs in applied science, computing, engineering,
and technology, to provide 2006-2007 accreditation criteria and procedures in Spanish. The translated documents are now available online. ABET, Inc. is a federation
of 28 professional and technical societies.
IEEE commissioned the translations, oversaw the
work and collaborated on the project with the Instituto
de la Calidad en la Acreditacion de Carreras de Ingenieria y Tecnolgogia (ICACIT), a university-level Peruvian accrediting body in the process of being established
10
IEEE SSCS NEWSLETTER
and chartered. IEEE will have the translated documents
updated when ABET updates the originals to ensure the
most current information is available to individuals
working on accreditation in Central and South America.
The translated ABET criteria and procedures were
used during a 2006 IEEE workshop held for educators
and practitioners on education in Lima, Peru.
The project was supported by the Educational Activities Board and the IEEE Peru Section. For access to the
translated documents, visit dfl.ece.drexel.edu/icacit/
index.php?PAGE=DOCUMENTS, or for more information on ICACIT visit dfl.ece.drexel.edu/icacit/.
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“Out-of-the-Park Home Runs”
Legendary Digital Circuits that Tracked Technology
Scaling
Kerry Bernstein, Senior Technical Staff Member, IBM T. J. Watson Research Center,
Yorktown Heights, NY, kbernste@us.ibm.com
F
ew people will argue that we enjoy today an
abundance of electronic capability enabled by
successive generations of technology scaling.
Transistor device technologies have evolved in material
and structure to circumvent limitations arising from
power consumption, variability, and fundamentally,
atomistic-level physics. What has been less apparent
however is the circuit design response to these device
changes. Each of the major “home runs” in high performance Field Effect Transistor technology (PMOS,
NMOS, CMOS, and SOI) has ushered in with it novel
circuit topologies and changes in the way logic functions are realized. Further, as whole new applications
(such as low power, handheld portable devices)
became enabled by improving transistor devices, entirely new circuits had to also be developed. Much is written about transistor scaling; this article will provide a
glimpse at what’s happened over the years in circuit
design, “the other dugout”. Let’s look at some major
league digital circuit styles which have quietly tracked
scaling.
NMOS
The PMOS technology used in the world’s first DRAM
chip, the 1K Intel 1103 in 1972, was among the first
marketed MOSFET applications. It was NMOS technology, however, that began the era of high performance MOSFET-based logic, seeing popular usage in
the 70s and 80s in applications like the HP 9800
series, the first truly modern consumer desktop calculators. NMOS provided the designer the use of
“enhancement-mode” (positive Vt) and “depletionmode” (negative Vt) FETs. They were of common
polarity, i.e. the drain-to-source current in both
increased monotonically as gate voltage increased.
The depletion-mode device
was used predominantly as
a current source load with
its gate tied to its source.
Enhancement devices provided the switchable path
to ground. The on-current
capability of the load
device to the switching FET
was selected so that the
enhancement-mode device
could sink the load
device’s
current
well
enough to produce an
acceptably low output voltage (low Vout), recognizable as a “Logical 0” by the
next stage. The circuit dissipates static power only in Fig. 1 NMOS NAND2
the low Vout state. However, the load current was the source of charge available
to pull up the output capacitance to the high “Logical 1” Vout level when the enhancement device was
switched off. Therein lies the rub with NMOS: larger
depletion devices increased the load current available to the output which sped up the rising transitions, but at the cost of increased static power in the
ON state power. This reduced NMOS’ power advantage over its bipolar transistor predecessor. The
NMOS realization of the common NAND2 is shown
in Figure 1.
The more complex “Push-pull” or clocked logic circuits (see below) turn off the load current when the
path to Ground is on, eliminating the static power.
Sizing a depletion-mode load device large enough
Table 1 Circuit topologies reviewed in this article
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to quickly drive large loads such as word lines would
have presented prohibitive power consumption when
coupled to Ground. Alternately, using an enhancement-mode load device, which could be turned off to
save power would’ve reduced the output voltage by
one threshold (“VTE”), and so was equally unacceptable. “Bootstrapping” avoided the one-VTE -drop in
output voltage occurring when an output is driven
through an enhancement-mode device with a positive
VTE [Hardee81]. A precharged inversion-layer-capacitor, inserted between gate and drain of the given
drive device, (Figure 2) elevated the drive device’s
drain to a voltage in excess of VDD+VTE as the drivedevice’s gate was driven high.
bipolar logic circuits), and because either NFET or
PFET devices are turned off for a given input logic
level; the only static current is leakage (which has
become an increasing problem as devices are scaled).
Although logic circuits built with CMOS devices were
first described in 1963 by Wanlass [Wanlass63] (see
Figure 3), it was not until the late 80’s that CMOS
became VLSI’s “designated hitter”.
Fig. 3. NOR3, the First CMOS Circuit Description, from the
1963 ISSCC Digest
Initially, CMOS chips comprised static combinatorial CMOS logic circuits. Soon, pinch-hitters such as
cascode voltage switching, pass gates / transmission
gates, and dynamic logic circuits began appearing.
Fig. 2
NMOS Bootstrap Circuit
As the device turned on, it passed the now-boosted signal to the output node, reduced by VTE. Since
bootstrapping elevated the drain of the enhancementmode drive device above VDD by at least VTE, the
resulting output still achieved a full “high” level. An
isolation device above the drive device prevented the
bootstrapped drive device drain from discharging up
into the lower voltage supply, by reverse-biasing as
bootstrapping occurred.
Depletion load devices were later clocked in an
attempt to eliminate static power.
Eventually, in NMOS logic circuits, this “Push-Pull”
circuit style became the preferred approach to manage power [Streetman80]. The next improvement,
however, would come from the ability to gate individual loads completely on or off to save power.
CMOS
The advent of CMOS finally provided designers with
FET devices of complementary polarities, allowing the
same transient input to simultaneously turn on the
pull-up transistors and turn off the pull down transistors (or vice-versa), instantly eliminating static power
and the power-delay trade-off of the NMOS circuits.
The fundamental power consumption is the CV2f
dynamic switching power. The circuit has no static
current or power because of the infinite resistance of
the MOSFET gate (in contrast to the base current of
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Static Combinatorial CMOS Logic
Because static combinatorial CMOS circuits are quite
noise-immune, easy to design, reliable, relatively low
power, and fully testable, unclocked static logic will continue to be a mainstay of microprocessors. Many superb
textbooks provide insight into circuit design using this
modern fundamental circuit family [e.g., Chandrakasan01].
Static CMOS circuits are given to formulaic design, allowing designers understanding only cursory device physics
to produce robust circuits. Ivan Sutherland described a
“cookbook” approach to setting CMOS device dimensions
which he called “Logical Effort”, or “design on the back of
an envelope”. A popular paperback later written by
Sutherland, Sproull, and Harris has made this approach an
engineering curriculum standard [Sutherland99].
A downside of static CMOS is that the pull-up structures use the lower-transconductance PFET, requiring
larger devices and costing area and power from the
increased gate size and capacitance. Idiosyncratic
power is also lost to short-circuit (or “crowbar”) current
flowing from Vdd to Ground during the switch interval
when both PFET and NFET devices are on [Hirata96].
Alternative circuit styles addressed improved power
and/or delay, as we’ll see in a minute.
Ironically, in logically wide NORs, high resistance
resulting from stacking multiple PFETs in series for
the pull-up function (i.e. the 3 series PFETs in Figure
3) is sometimes circumvented by substituting a sole
PFET. The gate of this device is then tied to ground in
an arrangement called “Pseudo-NMOS” [Subba00], a
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throw-back to the use of a depletion load device in
“ratioed circuits” from the old NMOS days.
pass-gate based circuit libraries (“Lean Integration”)
with substantial performance advantages as shown in
Figure 5 [Yano94].
Cascode Voltage Switching
Differential Cascode Voltage-Switched Logic (DCVSL),
first described at the ISSCC in 1984 by Larry Heller,
[Heller84], is the foundation of later higher-speed circuit structures. DCVSL influenced subsequent differential innovations appearing in industrial applications.
The author was privileged to work with Dr. Heller.
A number of DCVSL variations exploit the benefit of
using pairs of differential logic inputs to flip a static
cross-coupled device pair and store an output state.
DCVS is noise immune and logically complete. Trees
of stacked evaluation devices potentially couple the
circuit’s output node to ground, conditional upon the
result of the evaluation. Referring to Figure 4, with
input B high and input B-not low, transitioning high
input A and transitioning low input A-not are fed to
the differential evaluate tree, latching node Q-not low,
and node Q high. DCVSL improves logic den-sity by
evaluating complex trees of logic in one delay stage.
Fig. 4
CMOS Differential Cascode Voltage Scheme (DCVS)
Differential-pair logic trees may easily be 4 devices
tall, and process (24-1) inputs. The stacks of large
PFETS in the evaluate path are now gone. Boolean
functions are implemented in NFETs only; the PFETs
serve solely as pull-up devices. Static DCVS logic
offers implicit noise immunity at each stage, due to its
cross-coupled nature. Performance can be compromised, however by “hysteresis”, caused by the intrinsic difficulty associated with switching a latch. The
PFET load devices must be small enough that its oncurrent is easily overcome by the switching logical
pull-downs, but large enough to drive high out-puts
with acceptable delays.
Because true or complement outputs are not
always needed yet always provided by DCVS, and
because noise immunity was achieved in other ways,
the ‘need-for-speed’ eventually took DCVS out of the
circuit line-up.
Pass Gates and Transmission Gates
FET devices configured as pass transistors appeared
historically as an integral component of a fundamental MOS circuit, the one-device DRAM cell. Pass gates
are also indispensable in SRAM memory. It is no surprise then, that their versatility is exploited in CMOS
logic. Hitachi, in the mid 90s, proposed circuits using
Spring 2007
Fig. 5 CMOS LEAP/LEAN Pass-transistor Logic
The style required a “lean inverter” as shown in the
inset. This half-latch restored signals which had been
reduced by one VTE to full high voltage levels. Other
companies employed alternative pass-based circuit families such as Complementary Pass Logic (CPL) [Yano90]
and Double Pass Transistor Logic (DPL) [Suzuki93]. See
the references for explanations of their operation.
Although quite fast, pass gate structures have intrinsically more vulnerabilities than static. Vulnerabilities
include fan-out limitations, noise, body effect/source
follower action, and decode exclusivity [Bernstein98].
A variant of the pass gate, the transmission gate,
added a PFET in parallel with the NFET pass gate,
driving it with the complement of the NFET’s gate signal [Dillinger88]. The PFET avoids the NFET source
follower behavior, insuring that the output signal will
achieve the full Vdd output level, but at the cost of
additional devices and power.
As chip device counts reached into the hundreds of
millions in the late 90s, pass gate based logic use
declined, mainly due to (a) the added design attention
they required compared to slower but simpler combinatorial structures, and (b) the above sensitivity to
devices characteristics, which have increased with
CMOS scaling.
CMOS Dynamic Logic
Dynamic circuits use the presence or absence of
charge rather than voltage to evaluate logical inputs.
Dynamic Dominos are the most common form of
CMOS Dynamic logic, enjoying a 20-50% performance
advantage over static circuitry. Single-ended dynamic
domino, first proposed in 1982 [Krambeck82],
implicitly eliminates race conditions between competing logic paths, and was seen in the highest speed
logic designs, including the DEC Alpha Microprocessor family [Williams96].
Dynamic Dominos are composed of precharge,
evaluate, and buffer functional blocks.
The single-ended dynamic domino realization of a
two-way AND function is shown in Figure 6.
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Fig. 6
Dynamic Domino Realization of 2AND
During precharge, clock PC is low. PFET device 1
charges node N1 to VDD, driving output Q to ground
and turning on “keeper” PFET device 2. “Foot switch”
NFET device 5 is off, interrupting the path to ground
during precharge of the evaluate block. The evaluate
block is represented by devices 3 and 4. When PC
transitions high, the circuit switches from precharge to
evaluate mode. With logic inputs A and B high, node
N1 is coupled to ground, switching the output of
inverter buffer I1 high and turning off keeper PFET
device 2.
Single ended dominos can contain a substantial
amount of logic “width” in the NOR direction, and
“depth” in the NAND direction. This enables significant “logic gain” along a path of dominos. PFET
device 2 is an optional device which provides
replacement charge for leakage loss from node N1.
This keeper, with the output inverter/buffer, forms a
“half-latch,” introduces some hysteresis. If the circuit
is pre-charged every clock cycle, and if the clock
never quiesces the domino stage in it’s evaluate
mode, then the keeper is often omitted. As power
became precious in CMOS, Domino had a strike
against it because of the precharge clock power every
cycle. Strike two came from poor fail diagnosability,
since internal nodes can’t be interrogated. Leakage
variability impacts Domino’s noise margin in deeply
scaled CMOS; Domino ultimately struck out for all but
a few important remaining logic applications.
The body or substrate node of the MOSFET is
the long-neglected 4th device terminal. While it is
well-known that the potential of the body directly
influences the threshold voltage of the device,
until recently little was done to actively manage
device threshold. The advent of the triple-well
bulk CMOS [Kontos06] and the isolated-body partially-depleted SOI CMOS [Shahidi99] processes
provide opportunities for contacting groups of
bodies and controlling threshold. Many schemes
have been proposed to vary body voltage to trade
off active performance with standby power
[Tschanz02]. These schemes are used (a) to collectively put unused resources into low-power sleep
mode; (b) to dynamically adjust for across-chip
variability; or (c) to simply improve performance.
As overdrive becomes more precious at low voltage operation, body-biasing will sustain reduced
supply voltage performance [Park06]. Dynamic
Threshold CMOS (“DTCMOS”) connects the SOIMOSFET’s gate to its body and operates the device
at voltages less than Vdiode [Assaderaghi94]. The
structure, shown schematically in Figure 7, may be
useful if key problems are fixed: solutions have
yet to come forward.
Fig. 7 Dynamic Threshold CMOS ties the gate to the floating body
Wrap-up
Who’s on deck?
Novel FET structures have been proposed to keep
field effect transistors scaling for a few more innings.
For the most part, these devices are “evolutionary”
rather than “revolutionary:” FinFETs [Nowak03], and
Carbon Nanotubes [Javey03] schematically and logically may be treated as MOSFETs by circuit designers. The references have the details. A few noteworthy emerging design practices, however, have the
potential of disrupting the design of future products.
Techniques include body biasing and reduced-voltage operation. Let’s take a closing look at these
rookies.
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IEEE SSCS NEWS
Just as many generations have enjoyed the game of
baseball [Baseball06], generations of CMOS scaling
have provided us with higher and higher speed transistors. The technical marvels which enhance our
lives come directly from the innovative ways we
arrange and connect these “players”. It’s safe to say
that if we can keep improving our “roster”, we’ll
continue to fill the ballpark [Leventhal06] with happy
VLSI fans!
Acknowledgments
The author thanks Lewis Terman for important
insights and suggestions.
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References
[Abidi87] A. Abidi, et al., “An analysis of bootstrapped
gain enhancement techniques” IEEE Journal of
Solid-State Circuits, Volume 22, Issue 6, Dec 1987
pp. 1200 - 1204
[Assaderaghi94] F. Assaderaghi, et al, “A Dynamic
Threshold Voltage MOSFET (DTCMOS) for Ultralow Voltage Operation”, 2004 (IEDM), Dec. 2004,
pp. 809-812
[Baseball06] Editors of Sports Illustrated, “The Baseball Book”, Sports Illustrated Publishing, Oct 2006
[Bernstein98] K. Bernstein, et al, “High Speed CMOS
Design Styles”, Kluwer Academic Publishers, 1998
[Chandrakasan01] A. Chandrakasan, et al, “Design of
High Performance Microprocessor Circuits”, IEEE
Press, 2001, pp. 119-139
[Dillinger88] T. Dillinger, “VLSI Engineering,” PrenticeHall Publishing, 1988, pp. 433-435
[Hardee81] K.C.Hardee, et al, “A fault-tolerant 30
ns/375 mW 16K/spl times/1 NMOS static RAM”,
IEEE Journal of Solid State Circuits, Oct 1981, pp.
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[Heller84] L. Heller, et al, “ Cascode Voltage Switch
Logic: A Differential CMOS Logic Family”, 1984
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[Hirata96] A. Hirata, et al., “Estimation of short-circuit
power dissipation and its influence on propagation
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[Javey03] A. Javey et al., “Advancements in complementary carbon nanotube field-effect transistors”,
2003 IEEE (IEDM), Dec. 2003, pp. 31.2.1 - 31.2.4
[Kontos06] D. Kontos, et al, “Investigation of External
Latchup Robustness of Dual and Triple Well
Designs in 65nm Bulk CMOS Technology”, Proceedings of the 2006 IEEE International Reliability
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[Krambeck82] R.H. Krambeck, et al, “High Speed
Compact Circuits with CMOS”, IEEE Journal of
Solid-State Circuits, No. 3, June 1982, pp. 614-619
[Leventhal06] J. Leventhal, “Take Me out to the Ballpark: An Illustrated Tour of Baseball Parks Past and
Present”, Black Dog Publishers, Feb 2006
[Nowak03] E.J. Nowak, et al., “Scaling Beyond the
65nm Node with FinFET-DGCMOS”, Proceedings
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[Park06] D. Park, et al, “An Adaptive Body-Biased
VCO with Voltage-Boosted Switched Tuning in 0.5V Supply”, 2006 European Solid-State Circuits Conference, pp. 444 - 447
[Shahidi99] Shahidi, G.G, et al, “Partially-depleted SOI
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[Streetman80] B.G. Streetman, “Solid State Electronic
Devices”, Prentice Hall, 1980
[Subba00] N. Subba, et al., “Pseudo-nMOS revisited:
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impact of SOI on low power, high speed circuit
design” 2000 IEEE International SOI Conference,
pp. 26 - 27
[Sutherland99] I. Sutherland, et al., “Logic Effort:
Designing Fast CMOS Circuits”, Morgan Kaufmann
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[Suzuki93] M. Suzuki, et al, “A 1.5ns 32-b CMOS ALU
in Double Pass-Transistor Logic”, IEEE Journal of
Solid-State Circuits, November 1993, pp. 1145-1151
[Tschanz02] J. Tschanz, et al., “Adaptive body bias for
reducing impacts of die-to-die and within-die
parameter variations on microprocessor frequency
and leakage”, IEEE Journal of Solid State Circuits,
Nov. 2002, pp. 1396 - 1402
[Wanlass63] F. Wanlass, et al, “Nanowatt logic using
field-effect metal-oxide semiconductor triodes”,
Digest of Technical Papers, 1963 ISSCC, pp. 32 - 33
[Williams96] T. Williams, “Dynamic Logic: Clocked
and Asynchronous”, 1996 ISSCC, Tutorial Proceedings #4
[Yano90] K. Yano, et al, “A 3.8 ns CMOS 16 x 16 multiplier using complementary pass transistor logic”,
IEEE Journal of Solid-State Circuits, Vol. 25, No. 2,
April 1990, pp. 388-395
[Yano94] K. Yano, et al, “Top-Down Pass-Transistor
Logic Design”, IEEE Journal of Solid-State Circuits,
Vol. 31, No. 6, June 1996, pp. 792-803
About the Author
Kerry Bernstein is a Senior Technical
Staff Member at the IBM T.J. Watson
Research Center, Yorktown Hts, NY.
He currently is Principal Investigator
for 3D integration technology at IBM
Research, exploring 3D microprocessor and memory architectures, and 3D
circuits. Mr. Bernstein received the B.S. degree in
electrical engineering degree from Washington University in St.Louis, and joined IBM in 1978.
Mr. Bernstein’s work has bridged technology and
circuit design, exploring the technology sensitivities
of high performance CMOS circuit topologies; the mitigation of delay variability in design; and the circuit
responses to single-event upsets. He served as lead
technologist for IBM’s POWER Server series and for
IBM’s PowerPC microprocessor family. He also supervised technology application for IBM’s highest performance external foundry customers. Mr. Bernstein
has had the privilege of participating in the teams
developing and introducing fundamental device and
interconnect technologies to the industry throughout
his career, including NMOS, CMOS, Partially-Depleted
Silicon-On-Insulator devices, and copper/Low-K interconnects.
Mr. Bernstein holds 50 U.S. patents in the areas of
high performance circuits and technology. He coauthored 2 college textbooks with colleague and
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friend Norman Rohrer, and approximately 100
papers or book chapters on high speed / low power
CMOS. He attributes any success he has enjoyed to
be due in large part to working with wonderful, talented people. Mr. Bernstein has served on the program committees for IEEE ISSCC and Symposium on
VLSI Design. He derives fulfillment as an industrial
mentor for students and research at SEMATECH,
SRC/MARCO, DARPA, and for high schoolers interested in math/science/engineering careers. Mr. Bernstein is a staff instructor on Computational Neuroscience at RUNN/Marine Biological Laboratories,
Woods Hole, MA, and a commanding officer in the
HQ Battalion of the Vermont State Guard. He and
his family live in Northern Vermont. Mr. Bernstein is
an IEEE Fellow.
History Center adds 75 New Oral Histories to Web Site
T
he IEEE History Center has added 75 new oral histories to its online archive. The oral histories are
organized into nine different collections and
include interviews with Gordon Moore, the developer of
Moore’s law and co-founder of Intel Corporation, Robert
Noyce, one of the inventors of the integrated circuit and
Wilson Greatbatch, who helped develop the implanted,
cardiac pacemaker. All oral histories are in PDF format
and include an abstract and an index.
To view the list of collections, visit www.ieee.org/
web/aboutus/history_center/oral_history/oral_history.h
tml; for an alphabetical listing, visit www.ieee.
org/web/aboutus/history_center/oral_history/oh_a_f
o.html.
TECHNICAL LITERATURE
The (Pre-) History of the Integrated Circuit:
A Random Walk
By Thomas H. Lee, Center for Integrated Systems, Stanford University, Stanford, CA,
tomlee@stanford.edu
T
he half-century of the integrated circuit has
witnessed so many technical miracles that perhaps engineers can be forgiven for being a little blasé. But a little reflection should astonish even
the most jaded: The silicon we use comes as giant
monocrystals weighing hundreds of kilograms, and
whose impurities are denominated in sub-parts per
billion. On the wafers cut from these boules we regularly inscribe features with lateral dimensions of
tens of nanometers (using light whose free-space
wavelength is several times larger), and routinely
grow layers with controlled thicknesses of only a
few atoms. If those technical facts are too familiar,
then perhaps a biological comparison will impress:
The aggregate number of transistors produced annually exceeds the number of ants on Earth. For each
of an estimated 170dB ants, the IC industry fabricates
about ten transistors each year, and that number is
increasing exponentially. These remarkable achieve-
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ments beg several questions: How did we get to this
point, and how long can this continue? And what
comes next?
Attempting to predict the future is often foolish and
fruitless, but perhaps looking backwards is a useful
way to discern at least the outlines of possible futures.
The history of the IC is not at all the neat, linear and
logical narrative found in many textbooks and press
articles. In truth, there were false starts, dead ends, Uturns, titanic egos, geopolitics, frustrating failures,
ideas that were ahead of their time, and ideas that will
never be of any time. The story of the chip is, after
all, a human story.
The standard capsule history of the integrated circuit usually goes something like this: Vacuum tubes
dominate the first half of the 20th century, but their
limitations stimulate a search for alternatives. The
development of solid-state PN junction diodes leads
naturally to transistors in 1947, and then to the planar
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process and inevitably to the IC about a decade later.
Moore’s law gets established, and exponential scaling
continues beyond expectations, thanks to a vast, sustained multidisciplinary effort. Ultimately the gigascale era arrives on schedule, allowing every ant to
have a transistor radio.
Pre-vacuum tube semiconductors
As a counterpoint to the truncated standard version, consider that the first solid-state rectifiers
were built by accident, out of materials other than
silicon, long before there were any compelling
applications for semiconductors, and well before
the physics necessary for understanding them had
been developed. Future Nobelist Ferdinand Braun,
working at the University of Würzburg as an assistant shortly after receiving his doctorate, was
investigating the validity of Ohm’s law. After finding violations of Ohm’s conjecture in electrolytic
solutions, he discovered in the early 1870s that certain naturally-occurring metallic sulfides could
exhibit asymmetrical conduction as well [Braun,
1874]. Among the minerals he studied were chalcopyrites (sulfides of copper and iron), as well as
galena (lead sulfide). His inability to provide an
operative theory compounded the lack of any
practical use for these crude rectifiers, assuring the
relative obscurity of this work for decades.
The dawn of the wireless age provided the
necessary stimulus for engineers to revisit
Braun’s work thirty years later. The need for sensitive detectors was particularly acute. An early
device introduced primarily by Edouard Branly
(based on an accidental discovery by one Temistocle Calzecchi-Onesti) and developed further by
Marconi was the coherer [Scott, 1955]. Consisting
of metallic filings loosely packed within a glass
tube, the resistance of a coherer is initially high.
When triggered by a sufficiently strong electromagnetic signal, the resistance can drop several
orders of magnitude. Shaking the coherer
restores the high-resistance state. Frustration with
the coherer’s erratic nature and low sensitivity
impelled an aggressive search for better detectors. Without a suitable theoretical framework as
a guide, however, this search sometimes took
macabre turns. In one case, a human brain from
a fresh cadaver was even tested as a coherer,
with the flamboyant, and soon-to-be convicted
felon, A. Frederick Collins, claiming remarkable
sensitivity for his carbon-based apparatus
[Collins, 1902].
Most detector research was guided by the vague
notion that the coherer’s operation depends on
some mysterious property of imperfect contacts.
Haphazard, but determined experimentation with
a vast combination of materials eventually led a
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variety of researchers to stumble, virtually simultaneously, on the point-contact detector. The first
patent for such a device was awarded in 1904 to
the remarkable J.C. Bose for a detector that used
the galena identified by Braun thirty years earlier
[Bose, 1904]. This patent appears to be the first
awarded for a semiconductor detector, although it
was not recognized as such (indeed, the word
semiconductor had not yet been coined, as semiconductors were not yet acknowledged as a distinct class of materials). Soon after, Henry Harrison
Chase Dunwoody filed a patent application for a
detector using silicon carbide (carborundum), a
material that had been produced accidentally a
decade earlier during attempts by Edward Acheson to create artificial diamonds. On Dunwoody’s
heels was Greenleaf Whittier Pickard (whose
great-uncle was the poet John Greenleaf Whittier),
who applied for a patent on a silicon detector
[Dunwoody, 1906; Pickard, 1906]. Although Dunwoody actually applied for his patent first,
Pickard’s was granted a month sooner. The simplicity and excellent performance of galena, carborundum, silicon and other semiconductor detectors (collectively called crystal detectors by
George W. Pierce of Harvard) rapidly drove coherers into obsolescence.
One electrical connection to a crystal detector is
usually made with a small wire (whimsically
known as a catwhisker) that contacts the crystal
surface rather lightly at a single point. It is at this
interface that rectification occurs. Too high a contact pressure produces an ohmic contact; too light
a pressure results in excessive series resistance.
Adjustment is typically delicate and tenuous. The
other connection is a large-area ohmic contact typically formed by a clamp to the body of the crystal, or through the use of a low-melting-point conductive alloy (e.g. Wood’s metal) in which the crystal is embedded. In modern parlance, one might
call a device made this way a point-contact Schottky diode, although measurements are rarely quantitatively reconciled with such a description. Certainly, no two point-contact devices are alike; the
cathode may or may not correspond consistently
with either the catwhisker or the large-area contact, for example. Even for a given device, there is
enormous variability over the surface, and one
must hunt for a good spot, with no assurance that
one will be found.
The origin of the modern schematic symbol for a
diode is apparent from Pickard’s patent drawing
(fig. 1). The element labeled “TJ” is the point-contact diode.
This symbol originally depicted the physical structure, without regard for polarity. In short order, the
drawing gave way to a simpler schematic, with an
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Fig. 1. J. W. Pickard and drawing from his 1906 patent
arrow representing the point contact, and a rectangle
representing the semiconductor bulk. The arrow
eventually took on the additional responsibility of
identifying the direction of forward current, and the
rectangle ultimately collapsed to a single line representing the cathode terminal.
Pickard worked harder than anyone else to
develop crystal detectors, eventually trying over
30,000 combinations of wires and crystals [Douglas, 1981]. Among these are iron pyrites (fool’s
gold) and rusty scissors, in addition to silicon.
Galena came to be widely used because no bias is
needed for good results. However, adjustment of
the catwhisker is particularly tricky (lore has it that
argentiferous galena – “steel galena” – isn’t as
fussy). Silicon detectors are less exacting about
contact pressure, but can require a small (order of
100mV) bias for best results. Carborundum detectors typically need a bias of several volts, but operate satisfactorily with a relatively high contact pressure (indeed, many were packaged in cartridges
that one adjusted by slamming against a hard surface). They found wide use aboard ships as a consequence. By around 1907 semiconductors had
become important in wireless technology, despite
the fact that no one could explain how they
worked. This First Age of Semiconductors lasted
about a decade, fading into history only after the
vacuum tube had evolved to a reasonable state
around World War I.
The first semiconductor amplifiers
Although this First Age had practically come to an
end in the West by around 1920 or so, individual
researchers elsewhere soldiered on with the solid
state. One of the most remarkable (and virtually
unknown) stories from this era is that of self-taught
Soviet engineer Oleg Losev and his solid-state amplifiers and oscillators [Losev, 1922]. Vacuum tubes
were expensive then, particularly in the Soviet
Union so soon after the Revolution, so there was
naturally a great desire to find more economical
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alternatives. Losev chose to investigate the mysteries
of crystals.
His foray into semiconductor research resulted in
his independent rediscovery of blue electroluminescence from point-contact carborundum diodes [Loebner, 1976]. Although Henry J. Round had first published on this phenomenon in 1907 [Round, 1907],
Losev studied these blue LEDs in great detail. His
findings supported Round’s contention that the light
was not due to incandescence. Armed with insights
informed by a young quantum mechanics, Losev ultimately concluded that the cold light emission he was
observing was the direct inverse of the photoelectric
effect. He could not go any further than that, and the
absence of a market for tiny, low-efficiency blue lights
eventually led him to set aside this work.
Even more impressive than his insights into the
behavior of LEDs was his discovery of the negative
resistance that can be obtained from biased pointcontact zincite (ZnO) crystal diodes. Although sporadic reports of oscillation with galena, carborundum
and other materials populate the literature starting
soon after this class of detectors was patented [e.g.,
Eccles, 1909], the poor repeatability and poor performance of these devices kept them mere curiosities.
Losev discovered that the limitations of zincite are less
serious. Thanks to zincite’s superior performance, he
was able to construct fully solid-state RF amplifiers,
detectors and oscillators at frequencies beyond 5MHz
a quarter century before the invention of the transistor. He set about realizing a variety of classical radio
architectures in solid-state form, including tuned-RF,
heterodyne and regenerative receivers. He eventually
abandoned the “crystadyne” technology after about a
decade of work though, because of difficulties with
obtaining zincite (it’s found in commercially significant quantity in only two mines, and they’re both in
New Jersey), as well as the problem of interstage
interaction inherent in using two-terminal devices to
get gain, to say nothing of having to adjust more than
one point contact.
The reason almost no one in the U.S. has heard of
Losev is simple. First, it seems that there isn’t much
interest in preserving the names and stories of engineering pioneers in general (e.g., few know who Ohm
was, aside from having had a law famously named
after him). Plus, nearly all of Losev’s papers are in German and Russian, limiting readership. Add the generally poor relations between the U.S. and the U.S.S.R
over much of the 20th century, and it’s actually a wonder that anyone knows who he was. Losev himself
was unable to advocate for his place in history
because he was one of an estimated million people
who starved to death during the terrible Siege of
Leningrad, breathing his last in January of 1942. His
colleagues at the Nizhegorod Radio Laboratory had
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TECHNICAL LITERATURE
advised him to leave the city before the blockade was
complete, but he was just too interested in finishing up
“promising experiments with silicon.” Sadly, all
records of those experiments have apparently been
lost. [Loebner, 1976].
History is not monotonic
Around the same time that Losev was beginning his
work with zincite, Lars Grondahl of the Union Switch
and Signal Company in the U.S. was studying failure
mechanisms in switch contacts and became curious as
to why tarnished copper behaves as it does. He and a
colleague, Paul Geiger, discovered that cuprous oxide
(Cu2O) is a semiconductor (although, again, we are
using modern language and concepts that they did not
use). By around 1922 they had developed a rectifier
based on disks of copper abutting disks of cuprous
oxide [Grondahl and Geiger, 1927]. In contrast with
the point-contact devices that preceded it, these are
large-area rectifiers. As a result, these copper-disk
devices found use as high-power rectifiers, the first
solid-state devices capable of doing so (fig. 2).
semiconductor devices follow the same historical
progression?
Scarcely had Grondahl and Geiger announced the
copper oxide rectifier when Julius Lilienfeld began filing patent applications for three-terminal solid-state
amplifiers, some of which seem to anticipate the MESFET and MOSFET in many respects. Although there is
no evidence that Lilienfeld ever actually built working
devices, the basic concepts are sound. Indeed, Shockley’s patent application for a MOSFET was rejected
because of Lilienfeld’s patents.
An example is Lilienfeld’s first of three related
patent applications (fig. 3). Some sources refer to it as
a MOSFET, others as a MESFET. In truth, it’s not quite
either. Rather, it’s a literal reinterpretation of a triode
vacuum tube in solid-state form.
Fig. 3. J. J. Lilienfeld, method and apparatus for controlling electronic currents
Fig. 2. Copper-disk devices found use as high-power
rectifiers
The Bell System eventually adopted them as well,
to act as modulators for carrier-based telephony.
Researchers were mystified as to why copper of
seemingly equal purity produced rectifiers of vastly
different quality. For example, copper from certain
mines in Chile were found to be best, and so AT&T
obtained control over the copper supply from these
sources. Spectroscopic analysis was unable to identify the reasons for the differences in quality, and this
mystery persists to the modern day. Nonetheless, considerable developmental effort was expended
because of the commercial importance of copper disk
rectifiers. By the late 1930s, cuprous oxide was the
most highly developed semiconductor in use.
Pre-transistor transistors
The growing number of useful phenomena observed
in the solid state encouraged more widespread thinking about what else could be done. Vacuum tube
diodes had given way to triodes, so why shouldn’t
Spring 2007
The jagged structure down the middle is produced
by cracking the transistor in two, and interposing a
2.5μm thick electrode (analogous to a vacuum tube
grid) in the space produced. The two halves are then
reassembled. In an echo of Braun, Lilienfeld suggests
using copper sulfide as the semiconducting material
that makes up the bulk of the device [Lilienfeld, 1930].
Rudolf Hilsch and Robert Pohl have the distinction
of having published the first experimental data for a
three-terminal solid-state amplifier. In 1938 they
reported their results on an alkali halide-based device
[Hilsch and Pohl, 1938]. Although the large dimensions (necessitated by the requirement that the spacecharge layer accommodate a grid-like control electrode) guaranteed sub-Hz frequency response, the
fact that it worked at all provided important encouragement to those following the field.
The story of point-contact devices begins anew
around this same period, thanks to the demands of
microwave technology. During his research into
waveguide propagation of microwave signals, George
Southworth of Bell Labs was frustrated by the poor
performance of vacuum tube detectors at microwave
frequencies. In desperation, Southworth decided to
test some ancient point-contact detectors. He reasoned that the tiny point contact might have a correspondingly low capacitance, and thereby enable
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TECHNICAL LITERATURE
operation at the higher frequencies desired. A trip to
the surplus shops of New York‘s Cortlandt Alley was
all it took to find some crystal detectors. After cleaning up the dusty relics, he discovered to his relief and
delight that they indeed worked extremely well. This
conspicuous success encouraged others to reconsider
the utility of point-contact devices specifically, and
semiconductors in general.
Southworth’s success had far-ranging consequences.
Indeed, the modern age of silicon traces directly back
to that achievement. The development of radar in
World War II was made possible by the point-contact
silicon detector (fig. 4). In turn, the vast resources dedicated to the development of semiconductors during
the war set the stage for all that was to come.
Fig. 4. Polysilicon microwave diodes, c. 1945
The late-1930s saw a lively debate about what
made a given sample of semiconductor n-type or ptype. Spectroscopic analysis with the best instruments
available was unable to provide definitive answers.
One day Jack Scaff and Henry Theuerer of Bell Labs
happened to saw through an n-type portion of a silicon ingot. As the saw cut through the material, they
both smelled an odor that was familiar to these two
expert chemists. They had smelled something similar
in their youth, when cars had headlamps fueled by
acetylene. Trace amounts of phosphorus-bearing
compounds gave off a characteristic odor as the
lamps burned. Realizing the implications of phosphorus in their n-type ingot, they understood what was
likely making their sample n-type. Their highly
trained nostrils had provided a solution to a longstanding mystery, and pointed researchers toward a
new understanding of doping [Riordan and Hoddeson, 1997].
At almost the same time as Scaff and Theuerer’s
noses were putting spectrographic analysis to shame,
their colleague Russell Ohl discovered both the photovoltaic effect and the PN junction in silicon, in that
order. By chance, an ingot had been processed in a
way that left it n-type at one end and p-type at the
other. Somewhere near the middle was a PN junction.
Ohl found it by dutifully making resistance measure-
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ments along the ingot. He noticed erratic readings
near the middle and, after investigating, discovered
that it was due to the modulation of his laboratory
lighting by a spinning fan blade. He was astonished
to measure nearly half a volt across the junction, for
the copper-oxide photocells then in use typically generated only a tenth of that. Investigating further, he
discovered the rectifying properties of the same structure [Riordan and Hoddeson, 1997]. By about 1940,
then, doping was understood, the PN junction had
been discovered, and a good body of phenomenological knowledge was being gathered.
Sometimes, obsessive behavior is a good thing
The early history of semiconductors is one of making
do with naturally-occurring polycrystalline materials,
for the most part. Shockley didn’t feel that the lack of
monocrystalline starting materials was a serious
impediment to progress, and even went as far as discouraging others at the Labs from undertaking any
large-scale efforts dedicated to growing single crystals. After all, as Shockley noted, polycrystalline pointcontact detectors had served wartime radar quite well.
Fortunately for the history of electronics, Gordon Teal
was undaunted by Shockley’s opposition. Teal knew
that early vacuum tubes were erratic because of poor
vacuum technology, and was well aware that the electrical characteristics of tubes improved markedly, as
did their predictability and repeatability, as better
vacua were obtained. He saw in that history lesson an
analogy with semiconductors. He was certain that the
messiness of polycrystalline substances was likely
responsible for the poor performance and high variability exhibited by early semiconductor devices. He
felt strongly that the availability of more-perfect materials was essential to moving the field forward. Without his near-obsession with material perfection, semiconductor technology would have had a much
rougher time at a critical period. Teal was clearly the
right man for the job, for this is the same person who
had chosen for his doctoral thesis the study of germanium because “its complete uselessness fascinated
and challenged” him [Teal, 1976].
Discovering the transistor
As described beautifully in the companion article by
Riordan and Hoddeson in this issue, Bardeen and
Brattain discovered the transistor, in much the same
manner as Ohl had discovered the PN junction diode.
Shockley had first assigned his team the task of constructing a MOSFET, but they met only repeated failure. Switching from a messy compound semiconductor, copper oxide, to an elemental one, germanium,
didn’t help. It was during the course of a series of
ingenious diagnostic experiments that Bardeen and
Brattain accidentally created a solid-state amplifier. It
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wasn’t the MOSFET that Shockley had been hoping
for. Indeed, how it worked was still a topic of hot
debate. Shockley’s delight at his group having made
something that worked was balanced by his frustration at having been a mere spectator. He withdrew
socially, and worked madly to understand what they
had built, and then use those insights to design something better still that he could call his own. His work
paid off, for he was the first to understand explicitly
the role of minority carrier injection. That understanding in turn allowed him to invent the junction
transistor. In a first for semiconductors, he correctly
described the terminal characteristics of the bipolar
junction transistor several years before one was built
[Shockley, 1976].
Bell Labs began to manufacture the point-contact
transistor in 1948, using polycrystalline germanium.
Not far behind was Raytheon, which managed to
develop its own point-contact transistor, the CK703, in
a crash program less than six months after engineer
Norman Krim witnessed a demonstration at Bell Labs
in July of 1948 [Goldstein, 2003]. In 1951 Krim happened to room with Shockley while the two spent a
week serving on a government committee. Krim took
careful mental notes as Shockley spoke freely about
transistor developments. Realizing the growing importance of quartz tubes and germanium, the crafty Krim
arranged for Raytheon to corner the market on quartz
tubing as well as to buy up all the germanium produced by Eagle-Picher, a Missouri firm whose output
accounted for over 90% of the world’s supply of
device-grade germanium [Goldstein, 2003].
For engineers who have worked with junction bipolar transistors, point-contact devices seem exotic. The
parameter alpha can exceed unity (sometimes by an
order of magnitude), implying a negative beta! It is
possible to make a single-transistor latch, thanks to this
property. Although many theories have been advanced
over the years to explain this odd behavior, Shockley’s
explanation fits the largest range of data. During the
manufacture of a point-contact transistor, a brief surge
of current is passed through the collector in a somewhat mysterious process called “forming.” The energies
are high enough to cause local diffusion of atoms from
the catwhisker into the semiconductor, and perhaps
produce what amounts to a PNPN-like structure. This
model is the only published one that can explain the
very high alpha values occasionally encountered at
voltages low enough to preclude impact ionization and
avalanche multiplication. With or without a model, the
point-contact transistor was simply too unreliable to
compete seriously with the vacuum tube. This limitation is hardly surprising, considering the unreliability of
its point-contact diode ancestors. That’s why Bell Labs
expended so much effort to realize Shockley’s bipolar
junction transistor in a practical way. By the early to
mid-1950s, they had succeeded.
Spring 2007
Despite Shockley’s numerous technical achievements, his inability to get along with many of his colleagues did not go unnoticed at the Labs, and he was
frustrated to find his path to promotion blocked. He
eventually decided it was time to move back to his
hometown of Palo Alto, California, where his aged
mother still lived. Proximity to Stanford University,
with its pool of students as potential employees for the
company he planned to found, was an added lure.
He assembled a remarkably talented founding
group for the Shockley Semiconductor Laboratory,
but was unable to manage them well. His idiosyncratic (indeed, often paranoid) style led to a famous
mass resignation by eight gifted employees on 18
September 1957. In business as in comedy, timing is
everything. The “Traitorous Eight,” as Shockley
referred to them thereafter, went on to found Fairchild
Semiconductor, just as the launching of Sputnik by the
Soviet Union on October 4 immediately created a
demand for compact, lightweight and low-power
electronics to help win the Space Race.
A year later, a recently hired Jack Kilby found himself nearly alone at Texas Instruments when most of
the company took a two-week vacation. Rather than
sitting idle while his boss was away, Kilby considered
the engineering challenges associated with miniaturized electronics, and realized that the IC was possible.
On 12 Sept. 1958, he successfully demonstrated a
1.3MHz integrated RC oscillator (fig. 5). Because TI
had not yet mastered the art of diffusion in silicon, the
first IC was built out of germanium bits. Bondwires
interconnected the various components because Kilby
had not solved that problem yet. He was preoccupied
with proving the basic IC concept.
Fig. 5. First IC: 1.3MHz RC oscillator
At Fairchild, Bob Noyce had been thinking along
similar lines. Rumors of TI’s achievement spurred him
into action, and he quickly combined the planar
process ideas invented by his colleague, Jean Hoerni,
with his own ideas about photolithographicallydefined interconnect and junction isolation. Later, he
discovered that Kurt Lehovec at Sprague had already
anticipated junction isolation. Nonetheless, Fairchild
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Fig. 6. First IC: 1.3MHz RC oscillator
was the first to describe explicitly a complete flow for
building a practical integrated circuit. After protracted
litigation between TI and Fairchild, the two companies decided to declare a draw, and call Noyce and
Kilby (and thus their respective companies) co-inventors of the integrated circuit.
Today the IC is so valuable and ubiquitous that it is
hard to imagine a time before the chip. As obviously
good an idea as it may appear to be today, the IC was
not warmly greeted at its birth. Many engineers
thought of it as an expensive stunt. Others thought
that yields would never be high enough to be practical (and would plummet anyway if you were foolish
enough to increase the number of components).
Fairchild first described their IC at the 1960 IRE-AIEE
Conference on Transistor Circuits (later to become
ISSCC). The polite interest expressed by attendees
stood in stark contrast to the near mania for the tunnel diode, a device that all the experts were certain
would change the face of technology. Fortunately,
Noyce and others in the fledgling industry pressed
onward (perhaps because they had no practical alternative), and put us finally on the path that we continue to travel today.
Ultimately, Shockley’s company changed hands a
couple of times, finally disappearing within the bowels of ITT, never having turned a profit. Shockley gave
up his entrepreneurial ambitions and became a Stanford professor. His insistence on turning nearly every
conversation into a debate on race made him a pariah on campus.
Fairchild went on to establish Moore’s law, but
eventually Moore and Noyce left to found Intel.
As we’ve seen, the path to the present was anything but linear. Even if one were to argue that the
endpoint – planar silicon technology – was all but
inevitable, there were so many forks in the road along
the way that the path to the present was by no means
unique. Given how the past unfolded, it is likely that
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the future will evolve in a similarly random walk.
Over the short term, the future will look like a sensible extension of the present. Over a longer period,
however, there will be nonlinear changes of a type
that are hard to predict. But even if we can’t say what
those changes will be, we can assert with confidence
that they’ll happen.
Every generation seems to worry that “all the good
stuff has already been invented.” As an antidote to that
sort of thinking, consider that technology has by no
means wrung out all that nature has to offer. Leadingedge microprocessors today consume on the order of
100 watts, but have yet to compose anything as sublime
as, say, the Brahms piano trio, Op. 8, no.1. The human
brain consumes about 20-25 watts, and is capable of the
rich array of creative (and destructive) behaviors characteristic of our species. The gap in performance
between carbon and silicon is made all the more stark
when we compare the picosecond-level switching
speeds of electronics to the microsecond speeds of biology. Yet, despite the apparent performance deficit at
the device level, biology wins by an enormous margin
at a great many tasks. Nature has thus provided ample
evidence that we have only scratched the surface. If
engineers are given the “will to think” about doing
more, more will get done. As rocket scientist Wernher
von Braun famously noted, “Man is the only computer
that can be mass-produced by unskilled labor.” There is
still plenty of room to grow.
Addendum
Kilby definitely was preoccupied with the devices
themselves, and didn’t focus at all on the interconnect
problem. With Noyce, it was a bit the other way
around. His choice of aluminum was considered curious at the time, because conventional wisdom held
that, as an acceptor material, using aluminum was a bad
idea. Some lore (from Bell Labs) also suggested that aluminum didn’t adhere well to oxide. So, when Gordon
Moore sought to implement Noyce’s interconnect idea,
he tried just about every metal *but* aluminum. After
reporting to Noyce that all of these presented serious
problems of one kind or another, Noyce suggested trying aluminum because it was about the only thing left.
Moore was pessimistic, but dutifully tried it. The rest is
history.
References
Bose, Jagadish Chandra (Jagadis Chunder), “Detector
for electrical disturbances,” U.S. Patent 755,840,
filed 30 September 1901, issued 29 March 1904.
Braun, Ferdinand, “Ueber die Stromleitung durch
Schwefelmetalle (On current flow through metallic
sulfides).” Annalen der Physik und Chemie, v.153,
1874, pp. 556-563. He was christened Karl Ferdinand Braun, but never used his first name or first
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initial. His doctoral thesis is signed simply ‘Ferdinand Braun,’ for example. Some academics started
adding ‘Karl’ about 10 years ago, a practice that
Braun’s descendants find odd and somewhat irksome.
Collins, A. Frederick, “The effect of electric waves on
the human brain,” Electrical World and Engineer,
v.39, 1902, p. 335. He started out with brains of
other species and worked his way up to humans.
Douglas, Alan, “The crystal detector,” IEEE Spectrum,
pp. 64-67, April 1981.
Dunwoody, H. H. C., “Wireless telegraphy system,”
U.S. Patent 837,616, filed 23 March 1906, issued 4
December 1906.
Eccles, William H., “On an oscillation detector actuated solely by resistance-temperature variations,”
Proc. Phys. Soc. London, v.22, 1909, pp.360-368.
Goldstein, Harry, “The Irresistible Transistor,” IEEE
Spectrum, March 2003, v.40, pp. 42- 47.
Grondahl, Lars and Geiger, Paul H., “A new electronic rectifier,” Trans. AIEE, vol. 46, 1927, pp. 357-366.
Also see “Unidirectional Current-Carrying Device,”
U.S. patent 1,640,335, filed 7 January 1925, issued
23 August 1927.
Hilsch, Rudolf and Pohl, Robert W., “Steuerung von
Elektronenströmen mit einem Dreielektrodenkristall und ein Modell einer Sperrschicht (Control of electron flow with a three-electrode crystal
and a model of a barrier layer),” Zeitschrift für
Physik, v.111, May 1938, pp.399-408.
Kilby, Jack St. Clair, “Miniaturized Electronic Circuits,”
U.S. patent 3,138,743, filed 6 February 1959, issued
23 June 1964.
Lilienfeld, Julius E., “Method and apparatus for controlling electric currents,” U.S. patent 1,745,175,
filed 8 October 1926, issued 28 January 1930. Also
see 1,877,140 and 1,900,018.
Loebner, Egon, “Subhistories of the light-emitting
diode,” IEEE Trans. on Electron Devices, ED-23, no.
7, pp. 675-699, July 1976.
Losev, Oleg, “Detector-Generator; Detector-Amplifier,” Telegrafia i Telefonia bez Provodov, v.14, 1922,
pp. 374-386. German-language publications render
his name as Lossev, with the double-s corresponding to an unvoiced consonant in that language.
We have chosen a transliteration that is closer to
the original spelling.
Pickard, G. W., “Means for receiving intelligence communicated by wireless waves,” U.S. Patent
836,531, filed 30 August 1906, granted 20 November 1906.
Riordan, Michael and Hoddeson, Lillian, Crystal Fire:
The Birth of the Information Age. New York: W. W.
Norton & Company, 1997.
Round, Henry J., “A note on carborundum,” Electrical
Spring 2007
World, 1907, v. 49 p. 308.
Scott, T. R., Transistors and other crystal valves, MacDonald and Evans, Ltd., 1955. Scott’s references
reveal that the coherer was discovered independently several times between 1835 and 1890.
Shockley, William B., “The path to the conception of
the junction transistor,” IEEE Trans. on Electron
Devices, ED-23, no. 7, pp. 597-620, July 1976.
Teal, Gordon K., “Single crystals of germanium and
silicon – Basic to the transistor and integrated circuit,” IEEE Trans. on Electron Devices, ED-23, no.
7, pp. 621-639, July 1976.
Additional reading:
The story of early crystal detectors is well told by D.
Thackeray in “When tubes beat crystals: early radio
detectors,” IEEE Spectrum, pp. 64- 69, March 1983.
Material on other early detectors is found in a delightful and comprehensive volume by V. Phillips, Early
Radio Wave Detectors, Peter Peregrinus, 1980.
About the Author
Thomas H. Lee received the S.B., S.M.
and Sc.D. degrees in electrical engineering, all from the Massachusetts
Institute of Technology in 1983, 1985,
and 1990, respectively.
He joined Analog Devices in 1990
where he was primarily engaged in
the design of high-speed clock recovery devices. In
1992, he joined Rambus Inc. in Mountain View, CA
where he developed high-speed analog circuitry for
500 megabyte/s CMOS DRAMs.
He has also contributed to the development of
PLLs in the StrongARM, Alpha and AMD K6/K7/K8
microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University
where his research focus has been on gigahertzspeed wireline and wireless integrated circuits built
in conventional silicon technologies, particularly
CMOS.
He has twice received the “Best Paper” award at
the ISSCC, co-authored a “Best Student Paper” at
ISSCC, was awarded the Best Paper prize at CICC, and
is a Packard Foundation Fellowship recipient.
He is an IEEE Distinguished Lecturer of both the
Solid-State Circuits and Microwave Theory and Technology Societies. He holds 43 U.S. patents and
authored “The Design of CMOS Radio-Frequency
Integrated Circuits” (now in its second edition), and
“Planar Microwave Engineering”, both with Cambridge University Press. He is a co-author of four
additional books on RF circuit design. He is a founder
of Matrix Semiconductor (now part of Sandisk) and
ZeroG Wireless.
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Crystal Fire: The Invention, Development and
Impact of the Transistor
Adapted from Chapter 1 of Crystal Fire: The Birth of the Information Age, by Michael
Riordan and Lillian Hoddeson, published in 1997 by W. W. Norton & Company.
By Michael Riordan, University of California, Santa Cruz and Lillian Hoddeson,
University of Illinois, Urbana-Champaign
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IEEE SSCS NEWS
he switched the odd-looking device in and out of the circuit using a toggle switch. From the height of the jump,
they could easily tell it was amplifying the input signal
many times when it was included in the loop. And yet
there wasn’t a single vacuum tube in the entire circuit!
Photo courtesy of Alcatel - Lucent
I
n mid-December 1947 John Bardeen and Walter
Brattain, physicists at Bell Telephone Laboratories
in Murray Hill, New Jersey, solved a problem that
had been vexing their boss William Shockley for nearly a decade. They succeeded in making a solid-state
amplifier from germanium. A close cousin of silicon,
this semiconductor element had been employed in
crystal rectifiers at the heart of radar receivers during
World War II. Bardeen and Brattain’s revolutionary
device consisted of two closely spaced metal points
pressing onto a thin sliver of high-purity germanium
about the size of a small fingernail, to the back of
which was attached a third lead. A positive bias of a
few volts on one point dramatically increased the
conductivity just beneath the other one, boosting the
current through it by almost a hundredfold.
On the afternoon of December 23, Bardeen and
Brattain were scheduled to demonstrate their promising new electronic device to executives at Bell Labs.
Soft-spoken and cerebral, Bardeen had come up with
the key ideas for this gizmo, which Brattain quickly
and skillfully implemented. Working shoulder-toshoulder for most of the prior month, day after day
except on Sundays, they had finally gotten their Rube
Goldberg contraption to work as intended. [Riordan
and Hoddeson, 1997b; Hoddeson and Daitch, 2001]
That morning, while Bardeen completed a few calculations, Brattain was in his laboratory making lastminute checks. Around one edge of a triangular plastic
wedge, he had glued a small strip of gold foil, which he
carefully slit along this edge with a razor blade. He then
pressed both wedge and foil down into the steel-grey
germanium surface with a makeshift spring fashioned
from a heavy-duty paper clip. Barely an inch high, this
delicate device was clamped clumsily together by a Ushaped piece of plastic resting upright on one of its two
arms. Two copper wires soldered to edges of the foil
snaked off to batteries, transformers, an oscilloscope,
and other equipment needed to power the device and
assess its performance. [Brattain, 1968, 1976; Hoddeson,
1981; Riordan and Hoddeson, 1997b, pp. 115–141]
Shortly after lunch, Bardeen joined Brattain in his laboratory. Shockley arrived about ten minutes later, accompanied by the department head, acoustics expert Harvey
Fletcher, and research director Ralph Bown. After a few
words of explanation, Brattain powered up the equipment. The others watched the luminous spot racing
across the oscilloscope screen jump and fall abruptly as
William Shockley (at lab bench), John Bardeen and Walter
Brattain, the physicists who invented the first transistors.
They shared the 1956 Nobel Prize in Physics for this work.
Then, borrowing a page from the Bell history
books, Brattain mumbled a few impromptu words
into a microphone. A sudden look of surprise came
over Bown’s bespectacled face as he reacted to the
sound of Brattain’s gravelly voice booming in his ears
through a pair of headphones. Bown passed them to
Fletcher, who shook his head in wonder shortly after
putting them on. [Brattain, 1974]
For Bell Labs, it was an archetypal moment. More
than 70 years earlier, a similar event had occurred in
the attic of a boarding house in Boston, Massachusetts,
when Alexander Graham Bell uttered the words, “Mr.
Watson, come here! I want you!” [Fagen, 1975, p. 12]
I
n the following weeks, however, Shockley was torn
by conflicting emotions. The invention of the transistor, as Bardeen and Brattain’s solid-state amplifier soon came to be called, had been a “magnificent
Christmas present” for his group and especially for Bell
Labs, which had staunchly supported their program of
basic research in solid-state physics. But he was chagrined that he had not had a direct role himself in this
crucial breakthrough. “My elation with the group’s suc-
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Photo courtesy of Alcatel - Lucent
cess was tempered by not being one of the inventors,”
he wrote 25 years later. “I experienced frustration that
my personal efforts, started more than eight years
before, had not resulted in a significant inventive contribution of my own.” [Shockley, 1976, p. 612]
The first, point-contact transistor invented by John
Bardeen and Walter Brattain in December 1947.
Shockley had been hired in 1936 by Mervin Kelly,
then Bell Labs research director, specifically to apply
his expertise in solid-state physics to the invention of
new electronic devices. Having previously served as
the director of vacuum-tube development, Kelly recognized the limitations of these bulky, power-hungry
devices and of the balky electromechanical switches
in the Bell Telephone System. And he could foresee
that solid-state devices might provide much better and
more reliable alternatives. With Kelly’s blessing,
Shockley began searching for ways to fashion rugged
new solid-state devices that could amplify and switch
electrical signals. His familiarity with the quantum
mechanics of solids gave him a decided advantage in
this quest. In late 1939 he thought he had come up
with a good idea and built a crude gizmo with Brattain’s help, but it proved a complete failure. [Hoddeson, 1980; Shockley, 1974, 1976]
Far better insight into the subtleties of solids was
needed — and much purer semiconductor materials,
too. World War II interrupted Shockley’s efforts, but
the advances stimulated by wartime research and
development set the stage for major breakthroughs in
electronics and communications once the war ended.
Stepping in as Bell Labs Vice President, Kelly recognized these opportunities and organized a solid-state
physics group, installing his ambitious protegé as one
of its two leaders. [Hoddeson, 1981; Riordan and
Hoddeson, 1997a; 1997b, pp. 115-122]
Soon after returning to the Labs in early 1945,
Shockley came up with yet another design for a semi-
Spring 2007
conductor amplifier, what is now known as a fieldeffect transistor. But again, it didn’t work when Brattain and others fabricated and tested a few such prototype devices using silicon. And Shockley couldn’t
understand why. Discouraged, he turned to other
projects, leaving to Bardeen and Brattain the task of
figuring out why it had failed. In the course of this
research, they stumbled upon a completely different
— and successful — way to make a solid-state amplifier. [Shockley, 1976]
Their invention quickly spurred their headstrong
boss into a bout of feverish activity. Galled that he had
been upstaged by members of his own group, in what
was obviously a landmark discovery worthy of a Nobel
Prize, Shockley could think of little else besides semiconductors for the next month. He spent almost every
free moment trying to design a better solid-state amplifier that would be a lot easier to manufacture and use.
[Riordan and Hoddeson, 1997b, pp. 142–151; 1997c]
By late January 1948 Shockley had figured out the
important details of his own design. His approach
would use a three-layer sandwich of semiconductor
material — silicon or germanium — with wires attached
at each end and in the middle, to an inner “base” layer.
He eliminated the two fragile “point contacts” of
Bardeen and Brattain’s unwieldy contraption, which
would make manufacturing difficult and lead to quirky
performance. Based on the boundaries or “junctions”
between the layers, to be established within the semiconductor material itself, his amplifier should be much
easier to mass-produce and far more reliable. [Ibid.]
It still took more than two years before other Bell
researchers perfected the techniques needed to grow
ultrahigh-purity germanium crystals with just the right
characteristics to act as transistors and amplify electrical signals. On the 4th of July, 1951, Bell Labs
announced the production of the first “bipolar junction
transistors,” which had been successfully fabricated by
chemists Morgan Sparks and Gordon Teal based on
Shockley’s designs. [Teal, 1976; Goldstein, 1993]
But it was awhile before these junction transistors
could be produced in quantity. Meanwhile, a crack
team of Bell Labs engineers led by Jack Morton forged
ahead with development of point-contact transistors
based on Bardeen and Brattain’s ungainly invention,
for which the two physicists were awarded a patent
in 1950. By the middle of that decade, millions of dollars worth of new equipment based on these devices
was about to enter the Bell System. And in 1956
Bardeen, Brattain and Shockley received the Nobel
Prize in physics for their invention of the transistor.
[Riordan and Hoddeson, 1997b, pp. 168–194]
B
y the mid-1950s physicists and electrical engineers may have recognized the significance of
this invention, but the general public was still
mostly oblivious to it. Millions of radios, television
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sets and other electronic devices were produced
every year by such giants of American industry as
General Electric, RCA and Sylvania, but they came in
large, cumbersome boxes powered by balky vacuum
tubes that took a minute or so to warm up before anything else could happen. In 1954 the transistor was
widely perceived to be an expensive laboratory
curiosity with a few specialized applications, such as
in hearing aids and military communications.
That year things started to change dramatically,
however. A small, innovative company in Dallas
began producing germanium junction transistors for a
portable radio, which hit U.S. stores in October at
$49.95. Texas Instruments abandoned this market,
only to watch it be cornered by a little-known Japanese company that called itself SONY. Transistor radios
you could carry around in your shirt pocket rapidly
became a status symbol for teenagers in the suburbs
that were sprawling across the American landscape.
And after SONY started manufacturing television sets
powered by transistors in the early 1960s, U.S. leadership in consumer electronics began to be seriously
threatened. {Riordan and Hoddeson, 1997b, pp.
195–224; Morita, 1986]
Bell Labs and Texas Instruments had already turned
their R&D backs on germanium to focus research
efforts on the much more promising but challenging
semiconductor element silicon. With a bigger energy
gap (1.1 electron volts for silicon versus 0.67 eV for
germanium) between its valence and conduction
bands, silicon made far better electronic switches with
almost no leakage current in the “off” condition. And
they continued to amplify signals reliably at high temperature, while germanium quit working above about
75°C. But molten silicon reacts with just about everything it comes in contact with, which made it far more
difficult to purify and grow large crystals from it. These
problems began to be solved in 1954, when Bell Labs
and Texas Instruments fabricated the first successful
silicon transistors. The following year Bell Labs
chemist Morris Tanenbaum fashioned the first silicon
junction transistor using diffusion of trace impurities to
grow ultra-thin base layers hardly a micrometer thick.
Such transistors can operate at high frequencies above
100 MHz, as used in FM radio and television broadcasting. A new semiconductor industry based on silicon instead of germanium was about to emerge. [Riordan, 1998, 2005J; Tanenbaum and Thomas, 1956]
Vast fortunes would eventually be made in a serene
valley south of San Francisco then full of apricot
orchards. Dissatisfied with his lack of advancement
and eager to profit from this research, Shockley left
Bell Labs in 1955 for California. Intent on making millions, he founded the very first semiconductor company in the San Francisco Bay area. He lured topnotch scientists and engineers to the valley, ambitious
26
IEEE SSCS NEWS
men like himself who two years later jumped ship to
start their own firm, the Fairchild Semiconductor Corporation. What eventually became famous around the
world as Silicon Valley had begun with Shockley
Semiconductor Laboratory, which could trace its own
roots directly back to Bell Labs. [Riordan and Hoddeson, 1997b, pp. 224–253; 1997d]
But it was Texas Instruments and Fairchild Semiconductor that took the next giant steps in the history of the semiconductor industry. Using diffusion
technology pioneered by Bell Labs, electrical engineer
Jack Kilby figured out how to fabricate the world’s
first integrated circuit at Texas Instruments in 1958.
Like Bardeen and Brattain’s clumsy point-contact transistor, his first device was a delicate prototype; it used
diffused junctions in a single chip of germanium.
Prodded by physicists Jean Hoerni, Robert Noyce and
Jay Last, Fairchild took the lead in silicon, getting the
first successful integrated circuits to market. Its
approach used the far superior “planar” processing
technique conceived by Hoerni, in which impurities
are diffused into the silicon from a single side of the
wafer, and the resulting junctions are protected by a
glassy layer of silicon dioxide. Noyce figured out how
to employ this technique in making integrated circuits, and Last headed the development team that succeeded in producing them by early 1961. [Kilby, 1976;
LeCuyer, 2006, pp. 127–167]
Use of the silicon dioxide layer to protect and pattern the semiconductor material beneath it had been
discovered in 1955 and pioneered by two Bell Labs
chemists, Carl Frosch and Link Derick, who published
their work in 1957. But the Labs did not pursue the
use of this technique in making integrated circuits,
largely because Morton and other engineers thought
yields would be unacceptably low. So it took “outsiders” at Sun Belt companies to make the big leap
into IC production. [Riordan and Hoddeson, 1997d;
Riordan, 2006]
In 1960 M. M. Atalla and Dawon Khang succeeded
in using the oxide layer to fashion the first successful
field-effect transistor at Bell Labs. Their basic structure
was strikingly reminiscent of the one Shockley had
conceived 15 years earlier, to which Bardeen later
contributed major ideas. Voltage on a thin metal strip
(called the “gate”) above the oxide layer modulated
the current flowing in a semiconductor channel
beneath it, from the “source” to the “drain.” This structure soon became known as the metal-oxide-semiconductor, or MOS, transistor (also as the MOSFET,
for MOS field-effect transistor). Because of its initially
poor reliability and far lower frequency response, Bell
Labs did not pursue MOS technology further in 1961,
and cast its lot initially with bipolar junction transistors. This left the door wide open to RCA and
Fairchild, which perceived the potential this technol-
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TECHNICAL LITERATURE
ogy held for making microchips densely packed with
components. By the time Bell Labs returned to MOS
technology in the late 1960s, Fairchild researchers had
solved its difficult problems, and the company had a
commanding lead. [Bassett, 2002, pp. 22–56]
T
he transistor has indeed proved to be what
Shockley in 1949 called the “nerve cell” of the
electronic computers that were just then
emerging. [Shockley, 1949] And he made this comment at a time when the only working transistors had
two tungsten contacts sticking into a germanium sliver! Today, almost no electronic equipment can be
made without transistors, more than 99 percent of
which are MOS transistors. Millions and even billions
of them are routinely packed with other microscopic
specks onto chips that control everything from toys
and cell phones to automobiles, aircraft and supercomputers, serving as the binary “on-off” switches in
digital logic. Bipolar junction transistors have largely
been relegated to the roles of amplifying signals and
boosting power levels.
The initial impact of transistors came in portable
electronics. During the mid-1950s, they began to be
used extensively in hearing aids and transistor radios,
which liberated music and contributed to the explosion of rock-and-roll over the following decade. Walter Brattain often marveled about the use of transistor
radios by African tribesmen, but railed at the raucous
noise they produced. By 1961 transistors were the
foundation of a billion-dollar semiconductor industry
whose sales were almost doubling annually, finding
new applications every year in consumer electronics,
computers, and military hardware.
It took the invention and development of the
microchip, however, to realize the full potential of this
revolutionary electronic device to utterly change modern life. Computers had been built using transistors
since the mid-1950s, but that feat still involved soldering together thousands of discrete components.
With the advent of the microchip in the 1960s, this
could be done on a single silicon chip using what was
essentially a printing process. Early microchips quickly found application in the Minuteman intercontinental ballistic missile and the Apollo guidance system,
where every ounce came at a premium.
By 1965, when Gordon Moore published his
famous article in Electronics establishing what
became known as “Moore’s Law,” they were beginning be used in CDC and IBM computers aimed at the
academic, business and government markets. [Moore,
1965] Three decades later, as the transistor was nearing fifty, he observed that there were more of them
made every year than raindrops falling on California.
And more recently, he claims that the number of transistors produced annually exceeds the number of
characters printed in all publications the world over!
Spring 2007
Today the computing power that had once
required rooms full of bulky, fault-prone electronic
equipment is easily loaded into sturdy, reliable units
that sit on desktops, are lugged around in briefcases
and can even sit in the palm of one’s hand. Words,
numbers, sounds and images flash around the globe
via transistor-powered satellites, fiber-optic networks,
cell phones and fax machines. Teen-agers swap photographs over the Internet, play video games on
Xboxes, and carry many albums worth of music
around on iPods. Unusual new terms such as “to
google” and “podcast” have become part of everyday
language.
Through their landmark efforts, Bardeen, Brattain
and Shockley had struck the first glowing sparks of a
tremendous technological fire, which has raged ever
since and shows no signs of abating. Cheap, portable,
reliable electronic equipment based on transistors is
now found in almost every town, village and hamlet.
This tiny invention has made the world far smaller
and more intimate than ever before, bringing every
corner of the globe into almost instantaneous contact.
Nations that embraced the new information technologies based upon the transistor have flourished,
while one that did not has collapsed. China, Japan,
South Korea and Taiwan increasingly set communications standards, manufacturing much of the electronic equipment. Television signals penetrate a growing
fraction of the globe via communications satellite,
while financial transactions occur via veritable rivers
of ones and zeroes flashing through electronic networks all over the world.
The dystopian society envisioned by George
Orwell in the aftermath of World War II, at about the
same time the transistor was invented, has completely failed to materialize—in large part because transistorized electronic devices have empowered creative
individuals and nimble entrepreneurs far more than
Big Brother. A man or woman today can easily purchase the computing and communications power that
only governments, armed forces or major companies
could afford in that gloomy postwar decade, when
vacuum tubes dominated electronics and two superpowers braced for nuclear war.
The birth of an artifact of such tremendous significance had gone largely unnoticed amidst the clamor
of worldly events, until its impacts became thoroughly woven throughout the fabric of global society and
culture. In the sixty years since then, the transistor has
essentially redefined the very meaning of power,
which is today based more upon the control and
exchange of information than on iron or oil. At the
throbbing heart of this global transformation is the
tiny solid-state device invented by Bardeen, Brattain
and Shockley. The raging crystal fire they ignited has
radically reshaped the world and the way we now go
about our daily lives.
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References
Bassett, Ross Knox, 2002. To the Digital Age:
Research Labs, Start-Up Companies, and the Rise
of MOS Technology. Baltimore, MD: Johns Hopkins University Press.
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archives (AIP).
, 1968. “Genesis of the Transistor.” The Physics
Teacher, March, pp. 109–114.
, 1974. Interview by Charles Weiner, 28
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, 1976. “Walter Brattain: A Scientific Autobiography.” Adventures in Experimental Physics 5, pp.
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Fagen, M. D., ed., 1975. A History of Science and
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, 2006. “How Bell Labs Missed the Microchip.” IEEE
Spectrum, December, pp. 36–41.
Riordan, Michael and Lillian Hoddeson, 1997a. “The
Origins of the p-n Junction,” IEEE Spectrum, June,
pp. 42–47.
, 1997b. Crystal Fire: The Birth of the Informa-
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tion Age. New York: W. W. Norton & Company.
, 1997c. “Minority Carriers and the First Two
Transistors,” In A. Goldstein and W. Aspray, eds.,
Facets: New Perspectives on the History of Semiconductors. New Brunswick, NJ: IEEE Center for
the History of Electrical Engineering, pp. 1–33.
, 1997d. “The Moses of Silicon Valley,” Physics
Today, December, pp. 46–51.
Shockley, William, 1949. Text of interview titled “The
Transistor,” on radio station WGYN, Schenectady,
NY, 21 December, Shockley Papers, Stanford
Archives.
, 1974. Interview by Lillian Hoddeson, 10
September, AIP.
, 1976. “The Path to the Conception of the
Junction Transistor.” IEEE Transactions on Electron Devices ED–23:7, July, pp. 597–620.
Tanenbaum, M. and D. E. Thomas, 1956. “Diffused
Emitter and Base Silicon Transistors.” Bell System
Technical Journal 35, pp. 1–22.
Teal, Gordon K., 1976. “Single Crystals of Germanium and Silicon—Basic to the Transistor and Integrated Circuit.” IEEE Transactions on Electron
Devices, ED–23:7, July, pp. 621–39.
About the Authors
Michael Riordan serves as Lecturer in
the History Department at Stanford
University and as Adjunct Professor
of Physics at the University of California, Santa Cruz, where he teaches
the history of physics and technology. He is author of The Hunting of
the Quark: A True Story of Modern Physics (Simon
& Schuster, 1987), for which he won the 1988 Science Writing Award of the American Institute of
Physics (AIP). He is also coauthor of The Solar
Home Book: Heating, Cooling and Designing with
the Sun (Cheshire Books, 1977), The Shadows of
Creation: Dark Matter and the Structure of the Universe (W. H. Freeman, 1991), and Crystal Fire: The
Birth of the Information Age (W.W. Norton, 1997)
— for which he shared (with Lillian Hoddeson) the
1998 Sally Hacker Prize of the Society for the History of Technology.
Riordan has published many articles, essays and
reviews in The New York Times, The Los Angeles
Times, San Francisco Chronicle and Washington
Post, as well as in New Scientist, Physics Today, Science, Scientific American and Technology Review.
He has written extensively about the history of
semiconductor devices in IEEE Spectrum and other
periodicals.
Riordan is a Guggenheim Fellow and a Fellow
of the American Physical Society. In 2002 he
received the AIP’s prestigious Andrew W. Gemant
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TECHNICAL LITERATURE
Award in recognition of his many efforts communicating physics and its relationship to the wider
culture.
Lillian Hoddeson is an historian of
twentieth-century science and technology. As a Professor of History at the
University of Illinois at Urbana-Champaign, she teaches courses on the history of science and technology, oral
history, and memory. She is author or
editor of eight books and over 50 articles in the history of science or technology.
Her general book with Michael Riordan on the history of the transistor (Crystal Fire: the Birth of the
Information Age, 1997) won the first Sally Hacker prize
of the Society for the History of Technology for the best
book on technology aimed at popular as well as academic audiences. Her biography of John Bardeen
(True Genius: the Life and Science of John Bardeen,
2002, coauthored with Vicki Daitch) was recognized as
one of the best intellectual reads of 2002 by the Times
Higher Education Supplement, and it was the “Silver
Winner 2002 For Biography” in ForeWard Magazine’s
Book of the Year Awards. She is presently at work on
five other books. A history of “megascience,” as it
evolved at Fermilab, coauthored with Adrienne Kolb
and Catherine Westfall, is in press with the University
of Chicago Press. In preparation are: a biography of an
independent American inventor of alternative energy
technologies, a monograph on oral history and human
memory, a books of essays on memory and the construction of identity and culture, and, with Michael
Riordan and Adrienne Kolb, a history of the discontinued Superconducting SuperCollider.
Hoddeson’s professional honors include: Fellow of
the American Physical Society, Fellow of the Center
for Advanced Study at the University of Illinois; and
Fellow of the John Simon Guggenheim Memorial
Foundation.
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IEEE SSCS NEWS
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Semiconductor Amplifier Patent
W. SHOCKLEY
Publisher Item Identifier S 0018-9219(98)01000-7.
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SHOCKLEY: SEMICONDUCTOR AMPLIFIER PATENT
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Semiconductor Device-and-Lead Structure
Reprint of U.S. Patent 2,981,877 (Issued April 25, 1961. Filed July 30, 1959)
Robert N. Noyce, Fairchild Semiconductor Corporation
This invention relates to electrical circuit structures
incorporating semiconductor devices. Its principal
objects are these: to provide improved device-andlead structures for making electrical connections to
the various semiconductor regions; to make unitary
circuit structures more compact and more easily fabricated in small sizes than has heretofore been feasible; and to facilitate the inclusion of numerous semiconductor devices within a single body of material.
In brief, the present invention utilizes dished junctions extending to the surface of a body of extrinsic
semiconductor, an insulating surface layer consisting
essentially of oxide of the same semiconductor
extending across the junctions, and leads in the form
of vacuum-deposited or otherwise formed metal strips
extending over and adherent to the insulating oxide
layer for making electrical connections to and
between various regions of the semiconductor body
without shorting the junctions.
The invention may be better understood from the
following illustrative description and the accompanying drawings.
Figure 1 of the drawings is a greatly enlarged plan
view of a transistor-and-lead structure embodying
principles of this invention;
Figure 2 is a section taken along the line 2—2 of
Figure 1;
Figure 3 is a greatly enlarged plan view of a multidevice semiconductor-and-lead structure embodying
principles of this invention;
Figure 4 is a section taken along the line 4—4 of
Figure 3;
Figure 5 is a simplified equivalent circuit of the
structure shown in Figures 3 and 4, with additional
circuit elements external to said structure represented
by broken lines;
Figure 6 is a greatly enlarged plan view of another
transistor-and-lead structure embodying principles of
the invention;
Figure 7 is a section taken along the line 7—7 of
Figure 6.
Figures 1 and 2 illustrate one example of a structure according to this invention. A single-crystal body
of semiconductor-grade silicon, represented at 1, has
a high-quality surface 2, prepared in accordance with
known transistor technology. Within the body 1 there
are high-resistivity regions, designated I in the drawing, composed either of high-purity silicon having so
few donor and acceptor impurities that it is a good
insulator at ordinary temperatures and an intrinsic
semiconductor at elevated temperatures, or of some-
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IEEE SSCS NEWS
what less-pure silicon containing a trace of a material
such as gold that diminishes the effect of donor and
acceptor impurities by greatly reducing the carrier
concentrations.
Elsewhere within body 1, there are extrinsic N-type
and extrinsic P-type regions, designated N and P
respectively, formed in the well-known manner by
diffusing N-type and P-type dopants through surface
2 into the crystal, with appropriate masking to limit
the dopant to the desired areas. The smallest and
uppermost N-type region constitutes an emitter layer
of the transistor. This emitter layer overlies a somewhat larger P-type region which consitutes the base
layer of the transistor. The base layer, in turn, overlies
a still larger N-type region which constitutes the collector layer of the transistor. Between the emitter and
base layers there is a dished, P-N junction 3, having a
circular edge which extends to surface 2 and there
completely surrounds the emitter. Between the base
and collector layers there is a dished, P-N junction 4,
having a circular edge that extends to surface 2 and
there completely surrounds the base. The thickness of
the emitter and base layers has been exaggerated in
the drawings: in actual practice each of these layers is
but a few microns thick. The collector layer generally
is considerably thicker, and in the example illustrated
extends completely through the body 1 so that contact thereto may be made from the back side. Thus,
the three extrinsic semiconductor layers described
form a transistor equivalent to previously known
types of double-diffused junction transistors.
During diffusion of the donor and acceptor impurities into the semiconductor, at elevated temperature
in an oxidizing atmosphere, the surface of the silicon
oxidizes and forms an oxide layer 5, often one micron
or more in thickness, congenitally united with and
covering surface 2. This layer may consist chiefly of
silicon dioxide, or of disproportionated silicon suboxide, depending upon the temperature and conditions
of formation. In any event, the oxide surface layer is
durable and firmly adherent to the semiconductor
body, and furthermore it is a good electrical insulator.
According to common prior practice in manufacturing diffused-junction transistors, the semiconductor
body was deoxidized by chemical etching prior to
deposition of metal contacts on the semiconductor
surface. According to the present invention, only
selected portions of the oxide layer are removed, as
illustrated in Figures 1 and 2, for example, while other
portions of the oxide layer are left in place to serve as
insulation for electrical leads used in making connec-
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tions to and between the several semiconductor
regions.
In particular, portions of the remaining oxide film
extend across the edges of the P-N junctions at the
surface of the semiconductor body, to facilitate the
making of electrical connections from one side of a
junction to another without shorting the junction.
Thus, as illustrated in Figures 1 and 2, the remaining
oxide film comprises a tongue 5 that crosses the edge
of junction 4, and another tongue 5 that crosses the
edges of both junctions 3 and 4. On the other hand,
at least a portion of the surface over each of the emitter and base layers must be cleared to permit the formation of base and emitter contacts.
A convenient and highly accurate way to remove
only selected portions of the oxide film is to use photoengraving techniques. The photoengraving resist is
placed over the oxide-coated surface, and this is then
exposed through a master photographic plate having
opaque areas corresponding to the areas from which
the oxide is to be removed. In the usual photographic developing, the unexposed resist is removed; and
chemical etching can then be employed to remove
the oxide layer from the unexposed areas, while the
exposed and developed resist serves as a mask to prevent chemical etching of the oxide areas that are to be
left on the semiconductor surface.
A discoid, metal, emitter contact 6 is adherent to
surface 2, wholly within the edge of junction 3, cen-
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tered upon and in electrical connection with the emitter region of the transistor. Electrical connections to
this emitter contact are made through a metal strip 7
extending over and adherent to oxide layer 5. The
strip 7 extends over the tongue 5 of the insulating
oxide layer across the junctions 3 and 4, and thus provides an electrical connection extending from one
side of the composite structure inward to the central
emitter contact, without shorting any of the transistor
junctions.
The base contact is a C-shaped, metal strip 8,
adherent to surface 2 wholly between the edges of
junctions 3 and 4, substantially concentric with the
emitter contact 6 and substantially encircling the junction 3. It will be noted that tongue 5 and lead 7
extend between the two ends of the C-shaped contact
8, so that lead 7 and the emitter contact are effectively insulated from the base contact even though the
base contact substantially surrounds the emitter junction. Electrical connection to contact 8 is made
through a metal strip 9 extending over and adherent
to the insulating oxide layer 5. Strip 9 extends over
tongue 5 across the collector junction 4, and thus
provides an electrical connection from one side of the
composite structure into the base layer, which in this
embodiment is completely surrounded by the collector layer at the surface 2, without shorting the collec-
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tor junction 4.
Various methods may be employed for forming the
base and emitter contacts and leads. By way of example, the contacts and leads can be deposited in the
configuration shown by direct vacuum evaporation of
aluminum, or other suitable contact metal, through a
mask of suitable size and shape. Alternatively, a metal
coating may be deposited over the entire upper surface of the composite structure, and the unwanted
metal then removed by known photoengraving techniques to leave only the contact-and-lead configuration shown. After the contacts have been deposited
upon surface 2 of the semiconductor, the structure is
usually heated to form an alloy at the metal-silicon
interface so that good, ohmic contact between the
metal and the silicon is obtained.
It will be noted that regions of high-resistivity silicon are made to underlie portions of the leads 7 and
9. The principal purpose in this is to reduce the shunt
capacitance between the leads and the semiconductor
body. Otherwise, an undesirably high shunt capacitance may exist in some cases since the extrinsic
semiconductor regions are fairly good conductors,
and the insulating layer 5 has a thickness of only one
to two microns. The high-resistivity regions act essentially as insulators rather than as conductors, and thus
reduce the area of closely spaced conductors that lead
to high shunt capacitances. Of course, in cases where
the shunt capacitance is not excessive for the purposes desired, use of high-resistivity regions as disclosed
is not required.
The transistor structure is completed by an electrical contact to the collector layer, which may take the
form of a metal coating 10 plated over the entire back
side of the silicon body.
Even in a single transistor, as illustrated in Figures
1 and 2, the composite semiconductor-and-lead
structure provided by this invention has significant
advantages. According to prior practice, electrical
connection to the base and emitter contacts had to be
made by fastening wires directly to the contact areas.
This led to certain manufacturing difficulties, particularly in the case of small devices wherein, for exam-
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IEEE SSCS NEWS
ple, the emitter region might be only a few mils in
diameter and a few microns in thickness. Merely to
position the emitter lead on the emitter contact in
such small structures required the use of microscopes
and micro-manipulators; and the use of any considerable pressure or considerable heat in making the
joint permanent could cause sufficient damage to
destroy the transistor.
By means of the present invention, the leads 7 and
9 can be deposited at the same time and in the same
manner as the contacts themselves. Furthermore,
leads 7 and 9 can be made as large as may be desired
at the point where wires or other external circuit elements are to be attached; and such attachments can
be made at a distance from the active elements of the
transistor proper, so that the chances of damage to the
transistor are significantly reduced.
Further advantages accrue when it is desired to
incorporate more than one circuit device into a single
body of semiconductor. In this way exceptionally
compact and rugged circuits can be constructed. One
example of such a multi-device structure is illustrated
in Figures 3 and 4.
A single-crystal body 11 of silicon, largely P-type,
has a high-quality surface 12 prepared in accordance
with well known transistor technology. The other side
of body 11 is plated with a metal coating 13, which
serves as an electrical contact to the largest P-type
region and as a ground plane for the electrical circuit.
Various circuit elements may be formed within and on
this body of silicon. N-type and P-type dopants,
restricted to specific areas by known masking techniques, are diffused through surface 12 to form a plurality of N-type and P-type extrinsic semiconductor
regions, separated from the underlying P-type region
and from each other by a plurality of dished, P-N
junctions of various diameters and depths, all having,
in this particular example, circular edges extending to
surface 12 and there surrounding the overlying semiconductor regions.
Toward the left end of the structure illustrated in
Figures 3 and 4, there will be found an N-type region
overlying a small P-type region and separated there-
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from by a dished junction 14. The small P-type region
overlies another N-type region; and the underlying Ntype region in turn overlies the large, grounded Ptype region and is separated therefrom by a dished
junction 15. The junction between the two intermediate layers is shorted by contact 17. Consequently, this
structure provides two rectifying junctions connected
in series, each equivalent to a crystal diode.
Electrical connection to the upper N-type region is
made through a discoid, metal contact 16, adherent to
surface 12, wholly within junction 14 and substantially centered upon the N-type region. Electrical contact
to the two regions between junctions 14 and 15 is
made through a C-shaped metal contact 17, adherent
to surface 12, wholly between the edges of junctions
14 and 15, concentric with contact 16 and substantially encircling the edge of junction 14, which extends
to the surface 12.
Proceeding toward the right in the drawings, there
will be found another N-type region, separated from
the underlying, grounded, P-type region by a dished
junction 18. Electrical connection to the N-type region
in this case is made through a discoid, metal contact
19, adherent to surface 12 and substantially centered
inside the edge of junction 18, which extends to the
surface of the semiconductor.
Toward the right end of the structure illustrated,
there will be found a small N-type region overlying a
P-type region and separated therefrom by a dished
junction 20. The last-mentioned P-type region in turn
overlies a larger N-type region and is separated therefrom by a dished junction 21. The N-type region
below junction 21 in turn overlies the grounded
P-type region and is separated therefrom by a dished
junction 22. In this case, the width of the P-type
region between junctions 20 and 21 is less than a diffusion length, so that a substantial proportion of the
electrons that cross junction 20 are collected by junction 21. The result is an N-P-N junction transistor, in
which the small N-type region overlying junction 20
acts as the emitter, the P-type region between junctions 20 and 21 acts as the base, and the N-type
region between junctions 21 and 22 acts as the collector. The width of the last-menttioned N-type region
is greater than a diffusion length, and consequently
there is little interaction between junctions 21 and 22.
As will be explained hereinafter, junction 22 is normally reversebiased and acts much as a capacitor in
the overall circuit. It serves the important function of
isolating the collector of the transistor from the
grounded, underlying, P-type region.
Electrical connections to the three active regions of
the transistor are made as follows: A discoid, metal
contact 23 is adherent to surface 12, wholly within the
edge of junction 20, centered upon and in electrical
connection with the emitter layer of the transistor. A
C-shaped contact 24 is a metal strip adherent to sur-
Spring 2007
face 12 between junctions 20 and 21, substantially
surrounding the circular edge of junction 20 that
extends to the surface of the semiconductor body.
This contact overlies and is in electrical connection
with the base layer of the transistor. Another and larger C-shaped contact 25, which overlies and is in electrical connection with the collector layer, is likewise in
the form of a metal strip, adherent to surface 12
between junctions 21 and 22, and surrounding the circular edge of collector junction 21 that extends to the
surface.
Still another contact is provided upon and adherent
to surface 12. This is the discoid, metal contact 26,
directly upon and in electrical connection with the
grounded P-type layer, for the purpose of providing a
ground terminal at the upper surface of the composite structure.
Except for the contacts described above, the entire
surface 12 is covered with an insulating layer 27 of
oxidized silicon, generally about one micron thick.
This insulating layer may be formed upon the
exposed surface of the silicon during diffusion of the
N-type and P-type dopants into the silicon, at elevated temperatures and in an oxidizing atmosphere. The
presence of water vapor will enhance oxidation of
the silicon. Preferably, in accordance with this invention and contrary to prior practice, after diffusion is
completed the oxide layer is never removed from the
silicon, except for the areas to be covered by the
contacts herein described. The contact areas are
cleared by photoengraving, after which the contact
metal can be deposited by various known processes,
e.g., by the vacuum deposition of an aluminum film
covering both the cleared and oxide-coated areas.
Afterwards, unwanted metal can be removed from
the oxide-coated areas by photoengraving. The aluminum contacts may be alloyed to the silicon to
make ohmic contacts in a known manner.
The circuit structure is completed by providing
metal strips extending over and adherent to the insulating oxide layer 27 and making electrical connections to and between the various contacts heretofore
described. These metal strips may be deposited by
vacuum evaporation and deposition, and may conveniently be parts of the deposited film from which contacts are made. The leads come from portions of the
film that are deposited onto the oxide film and are
thereby insulated from the semiconductor body. As
hereinbefore explained, photoengraving can be used
to remove the unwanted metal, leaving only the leads
and contacts.
In the structure illustrated, there is an input lead 28
electrically connected to contact 17, and an output
lead 29 electrically connected to contact 25. A lead 30
interconnects contacts 16 and 19; if desired, lead 30
can be made sufficiently thin and narrow to have an
appreciable resistance, and thereby serve as a resist-
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ance element in the circuit. A similar lead 31 interconnects contacts 19 and 24, and still another lead 32,
which may be made to have an appreciable resistance
if desired, interconnects contacts 23 and 26.
The solid lines in Figure 5 represent the simplified,
equivalent circuit for the structure shown in Figures 3
and 4, while the broken lines in Figure 5 represent
typical external circuit components added for purposes of explanation. The solid-line parts are identified
by reference numbers identical to the reference numbers of corresponding parts in the structure of Figures
3 and 4, with the addition of a prime to the reference
numbers in Figure 5.
Any desired source of an amplitude-modulated,
A.-C. signal is represented at 34 in Figure 5. This
A.-C. signal is applied between the input lead 28 and
the ground, connection 13 , corresponding to lead 28
and ground plane 13 of the physical structure shown
in Figures 3 and 4. Lead 28 conducts the signal
through contact 17 into the two layers between junctions 14 and 15. As hereinbefore explained, each of
the junctions 14 and 15 performs essentially the functions of a crystal diode rectifier, as schematically represented at 14 and 15 , Figure 5.
Thus, as is evident from the equivalent circuit
shown in Figure 5, the input signal is rectified or
detected by the junctions 14 and 15, to provide at
contact 16 a signal essentially corresponding to the
modulation envelope of the input signal. Because of
its appreciable resistance, lead 30 acts as a circuit
resistor, represented in Figure 5 as 30 . It will be noted
that the polarity of rectifying junctions 14 and 15 is
such that the signal supplied to contact 19 has a D.C. component of the polarity required to reverse-bias
junction 18. Hence, the voltage across junction 18 is
always in the high-resistance direction of the junction,
and there is no appreciable current flow across this
junction. However, there are charge layers on both
sides of the junction which form a capacitance, as is
well known, and therefore the circuit function of junction 18 is to provide a capacitance, represented in
Figure 5 at 18 . The value of this capacitance can be
made greater or less, as desired, by increasing or
decreasing the area of junction 18.
Lead 31 has an appreciable resistance and therefore
acts as a circuit resistor, represented at 31 , Figure 5.
This leads to the base contact 24 of the transistor,
shown at 24 in Figure 5. The emitter contact of the
transistor is connected through lead 32 and contact 26
to the grounded P-type semiconductor region. This is
represented in Figure 5 by the emitter terminal 23
connected through resistor 32 to the ground line 13 .
The value of the resistor 32 is the sum of the resistances of contacts 23 and 26, lead 32, and the current
path through the P-type layer between contact 26 and
ground plane 13.
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IEEE SSCS NEWS
Normal operation of the N-P-N transistor requires
that the N-type collector be supplied with a relatively
positive voltage, as is accomplished in the equivalent
circuit illustrated in Figure 5 by the external voltage
supply 36 connected to the collector terminal 25
through any appropriate load 35. It is evident that this
supply voltage reverse-biases junction 22, and therefore, for reasons already explained, the junction 22
acts essentially as a capacitor, represented at 22 of the
equivalent circuit shown in Figure 5.
It should now be apparent that the structure shown
in Figures 3 and 4 comprises, within a single, rugged,
compact unit, detector, filtering, and transistor-amplifier stages. It is believed to be evident that the principles of this invention make feasible the construction
of an endless variety of circuit combinations, including combinations much more elaborate and complex
than the simple circuit employed for purposes of illustration, all within a highly compact and rugged,
essentially unitary, solid body.
Figures 6 and 7 show an example in which the
emitter and base contacts are parallel strips. A singlecrystal body 37 of silicon contains a P-type, emitter
layer overlying an N-type, base layer and separated
therefrom by a dished junction 38, which extends to
the upper surface of the semiconductor and there surrounds the P-type, emitter layer. In this case, the edge
of junction 38 does not form a circle at the surface,
but forms an elongated, closed figure. The N-type,
base layer overlies a P-type, collector layer and is separated therefrom by a flat junction 39.
The emitter contact 40 is a straight strip of metal,
vacuum-deposited or otherwise placed upon the
upper surface of the silicon, and preferably alloyed
thereto to form an ohmic contact. The base contact 41
is a similar strip of metal, parallel to contact 40. The
edge of junction 38 extends between the two contacts, and around contact 40, as shown. The collector
contact 42 may be a metal layer plated onto the bottom surface of the silicon.
Except for the areas covered by contacts 40 and
41, the upper surface of the silicon is covered by an
insulating oxide layer, congenitally united with the
silicon and actually formed by heating the silicon in
an oxidizing atmosphere. The oxide layer completely covers the edge of junction 38, and protects the
junction against accidental shorting in addition to
providing insulation between the electrical leads and
the silicon.
Electrical connection to contact 40 is made by a
metal strip 43, extending over and firmly adherent to
the oxide layer. Electrical connection to contact 41 is
made by a metal strip 44, similarly extending over and
firmly adherent to the oxide layer. These metal strips
can be formed by vacuum deposition through a mask,
or by plating the entire surface and then removing
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unwanted metal by photoengraving, or by any other
method providing metal strips that adhere securely to
the oxide surface.
The invention in its broader aspects is not limited
to the specific examples illustrated and described.
What is claimed is:
1. A semiconductor device comprising a body of
semiconductor having a surface, said body containing adjacent P-type and N-type regions with a
junction therebetween extending to said surface,
two closely spaced contacts a adherent to said surface upon opposite sides of and adjacent to one
portion of said junction, an insulating layer consisting essentially of oxide of said semiconductor
on and adherent to said surface, said layer extending across a different portion of said junction, and
an electrical connection to one of said contacts
comprising a conductor adherent to said layer,
said conductor extending from said one contact
over said layer across said different portion of the
junction, thereby providing electrical connections
to both of the closely spaced contacts.
2. A semiconductor device comprising a body of
extrinsic semiconductor having a surface, said
body containing adjacent P-type and N-type
regions, one overlying the other, with a junction
therebetween extending to said surface and there
completely encircling said overlying region, the
underlying one of said regions extending to said
surface and there surrounding said junction, a first
metal contact adherent to said surface in ohmic
electrical connection with said overlying region,
an insulating layer consisting essentially of oxide
of said semiconductor united with said surface
and extending across said junction, a metal strip
adherent to said layer, said strip being electrically
connected to said first contact and extending
therefrom over said layer across said junction, and
a second metal contact adherent to said surface in
ohmic electrical connection with said underlying
region, said second contact substantially encircling said junction from one side of said strip to
the other.
3. A semiconductor device comprising a body of
extrinsic semiconductor having a surface, said
body containing adjacent P-type and N-type
regions with a dished junction therebetween having a substantially circular edge at said surface, a
discoid metal contact adherent to said surface
wholly within and substantially concentric with
said edge, a C-shaped metal contact adherent to
said surface and substantially concentric with said
discoid contact, said C-shaped contact being wholly outside of and substantially encircling said edge,
said C-shaped contact having two ends defining a
gap there-between, an insulating layer consisting
of oxide of said semiconductor on said surface
Spring 2007
extending through said gap and across said junction, and a metal strip over and adherent to said
layer extending through said gap and across said
junction to said discoid contact, said contacts being
in direct electrical connection with respective ones
of said regions, and said metal strip being in direct
electrical connection with said discoid contact but
spaced and insulated from the ends of said Cshaped contact.
4. A diffused junction transistor comprising a body of
extrinsic silicon having a surface, said body containing adjacent base and emitter regions, with a discoid
emitter junction therebetween having a substantially
circular edge at said surface encircling said emitter
region, a discoid metal contact to said emitter region
adherent to said surface wholly within said edge, a
C-shaped metal contact to said base region adherent
to said surface and substantially encircling said edge,
said C-shaped contact having two ends defining a
gap therebetween, an insulating layer of oxidized
silicon on said surface, said layer being congenitally
united with said body and extending across said
junction, and a metal strip adherent to said layer,
said strip extending from said discoid contact over
said layer across said junction and between said
ends forming an electrical connection to said emitter region.
5. A semiconductor device comprising a single-crystal body of semiconductor material having a surface, said body containing a high-resistivity region
and extrinsic P-type and extrinsic N-type regions
with a P-N junction therebetween extending to
said surface, a metal contact to one of said extrinsic regions adherent to said surface, an insulating
layer consisting essentially of oxide of said material on said surface, said layer being congenitally
united with said body and extending across said
junction, and an electrical connection to said contact comprising a metal strip adherent to said
layer, said strip extending from said contact over
said layer across said junction, said high-resistivity region underlying a portion of said strip, reducing the shunt capacitance between said strip and
said body.
6. A semiconductor device comprising a body of
semiconductor having a surface, said body containing adjacent P-type and N-type regions, one
overlying the other, with a junction therebetween
extending to said surface, a first metal contact
adherent to said surface in electrical connection to
said overlying region, a second metal contact in
electrical connection with the underlying one of
said regions, an insulating layer consisting essentially of oxide of said semiconductor on said surface, said layer being congenitally united with said
body and extending across said junction, an electrical connection to said first contact comprising a
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metal strip adherent to said layer, said strip
extending from said first contact over said layer
across said junction, and circuit means for applying between said strip and second contact a D.C.
voltage of the polarity that reverse-biases said
junction, so that said junction acts as a capacitor
connected between said strip and said second
contact.
7. A semiconductor device comprising a body of
extrinsic semiconductor having a surface, said
body containing adjacent, first, second and third
regions, one overlying the other, P-type and Ntype alternately, with a first, dished, P-N junction
between said first and second regions having an
edge extending to said surface and there surrounding said first region, and a second, dished,
P-N junction between said second and third
regions extending to said surface and there surrounding said second region, a first metal contact adherent to said surface in electrical connection with said first region, a second metal
contact adherent to said surface in electrical connection with said second region, a third metal
contact in electrical connection with said third
region, an insulating layer consisting essentially
of an oxide of said semiconductor on said surface, said layer being congenitally united with
said body and extending across both of said
junctions, an electrical connection to said first
contact comprising a first metal strip adherent to
said layer, said first strip extending from said first
contact over said layer across both of said junctions, and an electrical connection to said second contact comprising a second metal strip
adherent to said layer, said second strip extending from said second contact over said layer
across said second junction.
8. A semiconductor device as in claim 7, wherein
said second contact is a C-shaped metal strip substantially encircling said first junction, and said
third contact is a larger C-shaped metal strip
adherent to said surface and substantially encircling said second junction.
9. A semiconductor device comprising a body of
extrinsic semiconductor having a surface, said
body containing a plurality of dished, P-N junc-
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tions each having an edge extending to said surface and there surrounding and defining an
enclosed region of said semiconductor, a plurality
of metal contacts adherent to said surface in electrical connection with respective ones of said
enclosed regions, an insulating layer consisting
essentially of oxide of said semiconductor on said
surface, said layer being congentially united with
said body and extending across a plurality of said
junctions, and electrical interconnections between
said contacts comprising metal strips adherent to
said layer and extending over said layer across a
plurality of said junctions.
10. A semiconductor device comprising a body of
extrinsic semiconductor having a surface, said
body containing adjacent P-type and N-type
regions with a dished junction therebetween, said
junction having an edge that extends to said surface and there forms an elongated, closed figure,
first and second contacts in the form of parallel
metal strips adherent to said surface, said first contact being wholly within and said second contact
wholly without said edge of the junction, an insulating layer consisting of oxide of said semiconductor on said surface and extending across said
junction, and a metal strip adherent to said insulating layer and extending thereover across said
junction to connect physically and electrically
with said first contact.
References Cited in the file of this patent
UNITED STATES PATENTS
2,813,326
Liebowitz
Nov, 19, 1957
2,836,878
Shepard
June 3, 1958
2,842,723
Koch et al.
July 8, 1958
2,849,664
Beale
Aug. 26, 1958
United States Patent Office
2,981,877
Patented Apr. 25, 1961
Semiconductor Device-and-Lead Structure
Robert N. Noyce, Los Altos, Calif., assignor to
Fairchild Semiconductor Corporation, Mountain View,
Calif., a corporation of Delaware
Filed July 30, 1959, Ser. No. 830,507 10 Claims.
(Cl. 317–235)
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Miniaturized Electronic Circuits
Reprint of U.S. Patent 3,138,743 (Issued June 23, 1964. Filed Feb. 6, 1959)
Jack S. Kilby, Dallas, Tex., assignor to Texas Instruments
This invention relates to miniature electronic circuits,
and more particularly to unique integrated electronic
circuits fabricated from semiconductor material.
Many methods and techniques for miniaturizing
electronic circuits have been proposed in the past. At
first, most of the effort was spent upon reducing the
size of the components and packing them more closely together. Work directed toward reducing component size is still going on but has nearly reached a
limit. Other efforts have been made to reduce the size
of electronic circuits such as by eliminating the protective coverings from components, by using more or
less conventional techniques to form components on
a single substrate, and by providing the components
with a uniform size and shape to permit closer spacings in the circuit packaging therefor.
All of these methods and techniques require a very
large number and variety of operations in fabricating
a complete circuit. For example, of all circuit components, resistors are usually considered the most simple to form, but when adapted for miniaturization by
conventional techniques, fabrication requires at least
the following steps:
(a) Formation of the substrate.
(b) Preparation of the substrate.
(c) Application of terminations.
(d) Preparation of resistor material.
(e) Application of the resistor material.
(f) Heat treatment of the resistor material.
(g) Protection or stabilization of the resistor.
Capacitors, transistors, and diodes when adapted
for miniaturization each require at least as many steps
in the fabrication thereof. Unfortunately, many of the
steps required are not compatible. A treatment that is
desirable for the protection of a resistor may damage
another element, such as a capacitor or transistor, and
as the size of the complete circuit is reduced, such
conflicting treatments, or interactions, become of
increasing importance. Interactions may be minimized
by forming the components separately and then
assembling them into a complete package, but the
very act of assembly may cause damage to the more
sensitive components.
Because of the large number of operations
required, control over miniaturized circuit fabrication
becomes very difficult. To illustrate, many raw materials must be evaluated and controlled even though
they may not be well understood. Further, many testing operations are required and, even though a high
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yield may be obtained for each operation, so many
operations are required that the over-all yield is often
quite low. In service, the reliability of a circuit produced by methods of such complexity may also be
quite low due to the tremendous number of controls
required. Additionally, the separate formation of individual components requires individual terminations
for each component. These terminations may eventually become as small as a dot of conductive paint.
However, they still account for a large fraction of the
usable area or volume of the circuit and may become
an additional cause of circuit failure or rejection due
to misalignment.
In contrast to the approaches to miniaturization that
have been made in the past, the present invention has
resulted from a new and totally different concept for
miniaturization. Radically departing from the teachings of the art, it is proposed by the invention that
miniaturization can best be attained by use of as few
materials and operations as possible. In accordance
with the principles of the invention, the ultimate in
circuit miniaturization is attained using only one material for all circuit elements and a limited number of
compatible process steps for the production thereof.
The above is accomplished by the present invention by utilizing a body of semiconductor material
exhibiting one type of conductivity, either n-type or
p-type, and having formed therein a diffused region
or regions of appropriate conductivity type to form a
p-n junction between such region or regions and the
semiconductor body or, as the case may be, between
diffused regions. According to the principles of this
invention, all components of an entire electronic circuit are fabricated within the body so characterized by
adapting the novel techniques to be described in
detail hereinafter. It is to be noted that all components
of the circuit are integrated into the body of semiconductor material and constitute portions thereof.
In a more specific conception of the invention, all
components of an electronic circuit are formed in or
near one surface of a relatively thin semiconductor
wafer characterized by a diffused p-n junction or junctions. Of importance to this invention is the concept
of shaping. This shaping concept makes it possible in
a circuit to obtain the necessary isolation between
components and to define the components or, stated
differently, to limit the area which is utilized for a
given component. Shaping may be accomplished in a
given circuit in one or more of several different ways.
These various ways include actual removal of portions of the semiconductor material, specialized con-
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figurations of the semiconductor material such as long
and narrow, L-shaped, U-shaped, etc., selective conversion of intrinsic semiconductor material by diffusion of impurities thereinto to provide low resistivity
paths for current flow, and selectve conversion of
semiconductor material of one conductivity type to
conductivity of the opposite type wherein the p-n
junction thereby formed acts as a barrier to current
flow. In any event, the effect of shaping is to direct
and/or confine paths for current flow thus permitting
the fabrication of circuits which could not otherwise
be obtained in a single wafer of semiconductor material. As a result, the final circuit is arranged in essentially planar form. It is possible to shape the wafer
during processing and to produce by diffusion the
various circuit elements in a desired and proper relationship. Certain of the resistor and capacitor components described herein have utility and novelty in and
of themselves although they are completely adaptable
to and perhaps find their greatest utility as integral
parts of the semiconductor electronic circuit hereof.
It is, therefore, a principal object of this invention
to provide a novel miniaturized electronic circuit fabricated from a body of semiconductor material containing a diffused p-n junction wherein all components of the electronic circuit are completely integrated into the body of semiconductor material.
It is another principal object of this invention to
produce desired circuits by appropriately shaping a
wafer of semiconductor material to obtain the necessary isolation between components thereof and to
define the areas utilized by such components.
It is a further object of this invention to provide a
unique miniaturized electronic circuit fabricated as
described whereby the resulting electronic circuit will
be substantially smaller, more compact, and simpler
than circuit packages heretofore developed using
known techniques.
It is a still further object of this invention to provide
novel miniaturized electronic circuits fabricated as
described above which involve less processing than
techniques heretofore used for this purpose.
It is a primary object of the invention to provide a
miniaturized electronic circuit wherein the active and
passive circuit components are integrated within a
body of semiconductor material, the junctions of such
components being near and/or extending to one face
of the body, with components being spaced or electrically separated from one another as necessary in
the circuit. These features permit a versatility in
design of integrated circuits not heretofore available.
The foregoing and other objects and features of the
invention will become more readily apparent from the
following detailed description of preferred embodiments of the present invention when taken in conjunction with the appended drawings, in which:
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FIGURES l–5a illustrate schematically various circuit
components fabricated in accordance with the principles of the present invention in order that they may
be integrated into, or as they constitute parts of, a single body of semiconductor material;
FIGURE 6a illustrates schematically a multivibrator
circuit fabricated in accordance with the present
invention;
FIGURE 6b shows the wiring diagram for the multivibrator circuit of FIGURE 6a laid out in the same
relationship;
FIGURE 7 illustrates the wiring diagram of the multivibrator circuit of FIGURE 6a in a more conventional presentation;
FIGURE 8a illustrates schematically a phase shift
oscillator fabricated in accordance with the principles
of the present invention;
FIGURE 8b shows the wiring diagram for
FIGURE 8a with the components laid out in the same
relationship; and
FIGURE 8c portrays the wiring diagram of the
phase shift oscillator.
As will be apparent to one skilled in the art, circuit
components can be classified according to their circuit functions. Thus, circuit elements may be thought
of as being active or passive in nature. According to
“The Encyclopedic Dictionary of Electronics and
Nuclear Engineering,” edited by Sarbacher, and published by Prentice-Hall, active elements are those
which in an impedance network act as current generators; whereas passive elements do not so act.
Examples of active elements are photocells and transistors; examples of passive elements are resistors,
capacitors and inductors. Diodes, while most often
employed as passive elements, may if suitably biased
and energized, function in an active capacity. Varactor diodes and tunnel diodes are examples of diodes
operating in an active capacity. The term “circuit” (or
“network”) means two or more discrete circuit elements electrically connected together; and by “discrete circuit element” is meant a resistor, capacitor,
inductor, diode, transistor or the like that is formed
separately or purposely as distinguished from existence as a function incidentally, accidentally or
inherently as a part of some other circuit element, as,
for example, every transistor may be said to exhibit
some resistance and capacitance along with its transistor action.
Referring now to the drawings in detail, preferred
embodiments of the present invention will now be
described in detail in order that a better understanding of the principles of the invention and the various
forms and embodiments of the invention will be better understood.
As noted previously, the invention is primarily con-
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cerned with miniaturization of electronic circuits.
Also, as noted, the invention contemplates the use of
a body of semiconductor material appropriately
shaped, electrically and physically and having formed
therein a p-n junction or junctions and the use of
component designs for the various circuit elements or
components which can be integrated into or which
constitute parts of the aforesaid body of semiconductor material.
FIGURES 1–5 inclusive illustrate in detail circuit elements formed in accordance with the principles of
this invention which can be integrated into a body of
semiconductor material. It is noted at this point that
the body of semiconductor material is of single crystal structure, and can be composed of any suitable
semiconductor material. There may be mentioned as
examples of suitable materials germanium, silicon,
intermetallic alloys such as gallium arsenide, aluminum antimonide, indium antimonide, as well as
others.
Referring particularly to FIGURE 1, there is shown
a typical design for a resistor which may be embodied or integrated into a body of single crystal semiconductor material. As noted in FIGURE 1, the design
contemplates utilizing the bulk resistance of a body
10 of semiconductor material of any conductivity
type. Contacts 11 and 12 are made ohmically to one
surface of the body 10, spaced apart a sufficient distance to achieve a desired resistance. As will be
apparent to one skilled in the art, ohmic connections
are those which exhibit symmetry and linearity in
resistance to flow of current therethrough in any
available direction. If two resistors are to be connected together, it is not necessary to provide separate terminations for the common point. The resistance may
be calculated from
R = ρL/A
where L is the active length in centimeters, A is the
cross sectional area, and ρ is the resistivity in ohm-cm.
of the semiconductor material.
In addition to the resistor shown in FIGURE 1, a
resistor may be provided as shown in FIGURE la for
integration into and as forming a part of a body of
semiconductor material. In FIGURE la, there is shown
a body 10a of p-type semiconductor material with an
n-type region 10b formed therein. Of course,
between the body 10a and region 10b there is a p-n
junction which is designated by the numeral 13. Contacts 11a and 12a are made to one surface of the
region 10b, spaced apart from each other in order to
achieve a desired resistance. As in FIGURE 1, the
contacts 11a and 12a are ohmic contacts to the region
10b. A resistor formed in the manner of
FIGURE la has several important advantages. First,
the p-n junction 13 provides a barrier to current flow
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from the n-type region 10b into the p-type body 10a
and, thus, the current flow is confined to a path in
the n-type region 10b between the contacts thereto.
The second advantage is that the total resistance
value thereof can be controlled to a large degree. The
total resistance value may be controlled by etching
very lightly over the entire surface to remove the
uppermost portion of the n-type region 10b, being
very careful to not etch through the p-n junction, and
as well by selectively etching to or through the p-n
junction 13 thereby effectively to increase the length
of the path traveled by the current between the contacts. The third, and perhaps major, advantage in
forming a resistor according to FIGURE la is in that,
by controlling the doping level or impurity concentration in the n-type region 10b, lower and more
nearly constant temperature coefficients may be provided for the resistor. The above description has
been in terms of a p-type body 10a and an n-type
region 10b but it is obvious that the body 10a could
be equally as well of n-type conductivity and the
region 10b of p-type conductivity. Resistors according to FIGURE la may be formed as separate circuit
elements or components.
Capacitor designs may be obtained by utilizing the
capacitance of a p-n junction, as shown in FIGURE 2,
wherein a semiconductor wafer 15 of p-type conductivity is shown containing an n-type diffused layer 16.
Ohmic contacts 17 are made to opposite faces of the
wafer 15. The capacitance of a diffused junction is
given by
qa 1/3
C = A
12 V
where A is the area of the junction in square cm., is
the dielectric constant, q is electronic charge, where a
is the impurity density gradient, and V is the applied
voltage.
Instead of the capacitor of FIGURE 2, capacitance
in a body of single crystal of semiconductor material
may be provided as shown and described in connection with FIGURE 2a. FIGURE 2a shows a body 15a of
semiconductor material, of either n- or p-type conductivity, which constitutes one plate of the capacitor.
Evaporated onto the body 15a is a layer 18 providing
a dielectric layer for the capacitor. It is necessary that
the layer 18 have a suitable dielectric constant and be
inert when in contact with the semiconductor body
15a. Silicon oxide has been found to be a suitable
material for dielectric layer 18 and may be applied by
evaporation or thermal oxidation techniques onto
body 15a. Plate 19 forms the other plate of the capacitor and is provided by evaporating a conductive
material onto layer 18. Gold and aluminum have been
found to be satisfactory materials for the plate 19.
Ohmic contact 17a is made to the body of semiconductor material 15a and contact to plate 19 may be
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made by any suitable electrical contact (not shown).
Capacitors formed in the manner described in connection with FIGURE 2a have been found to exhibit
much more stable characteristics than pure junction
capacitors, that is, p-n junction capacitors, and, of
course, may be fabricated as separate elements or
components.
Capacitors produced in the manner of FIGURE 2
are also diodes, and must therefore be properly polarized in the circuit. Non-polar capacitors may be made
by connecting two such areas back-to-back. Although
junction capacitors have a marked voltage dependence, such dependence is present to a lesser degree
for low voltages in the non-polar configuration.
Resistor and capacitor designs may be combined
to form a distributed R-C network. Such is shown in
FIGURE 3, wherein a wafer 20 of p-type conductivity
having an n-type conductivity diffused layer 21
formed therein is provided with a broad area contact
22 on the face and spaced contacts 23 on the opposite face. These networks are useful for low passfilters, phase shift networks, coupling elements, etc.
Their parameters may be calculated from the equations above. Other configurations of this general type
are also possible.
Transistors and diodes may be formed on a wafer,
as described by Lee in “Bell System Technical Journal,” vol. 35, p. 23 (1956). This reference describes a
transistor, as shown in FIGURE 4, which has a collector region 25, a diffused p-n junction 26, a base layer
27, an emitter contact 28 for a rectifying connection
with base layer 27 and base and collector contacts 29
and 30, respectively. The base layer 27 is formed as a
mesa of small cross section. A diode of similar design
is shown in FIGURE 5, and consists of a region 35 of
one type conductivity, a mesa region 36 of opposite
conductivity type with a p-n diffused junction formed
therebetween and contacts 37 and 38 to each region.
Small inductances, suitable for high frequency use,
may also be made by shaping the semiconductor as
evidenced by FIGURE 5a which shows a spiral of
semiconductor material. It is also possible to prepare
photosensitive, photoresistive, solar cells and other
like components utilizing the considerations outlined
above.
Although all of the circuit elements have been
described in terms of a single diffused layer, it is quite
possible to use a double diffused structure. Thus,
double diffusion may be employed to form both
n-p-n and p-n-p structures. Moreover, any suitable
substances can be used for the semiconductor materials, conductivity producing impurities, and contact
materials; and suitable and known processing can be
exploited in producing the above circuit designs.
Because all of the circuit designs described above
can be formed from a single material, a semiconduc-
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tor, it is possible by physical and electrical shaping to
integrate all of them into a single crystal semiconductor wafer containing a diffused p-n junction, or junctions, and to process the wafer to provide the proper
circuit and the correct component values. Junction
areas for the transistors, diodes, and capacitors are
formed by properly shaped “mesas” on the wafer.
A specific illustration of an electronic circuit
embodying the principles of the invention is shown in
FIGURE 6a. As shown, a thin wafer of single crystal
semiconductor material containing a diffused p-n
junction has been processed and shaped to include a
complete and integrated multivibrator electronic circuit formed essentially in one surface of the wafer.
The regions of the wafer have been marked with symbols representative of the circuit element functions
that are performed in the various regions. FIGURE 6b
shows a wiring diagram of the various circuit functions in the relationship which they occupy in the
wafer of FIGURE 6a. A more conventionally drawn
circuit diagram is shown in FIGURE 7 with the circuit
values actually used. The multivibrator circuit shown
in FIGURES 6a, 6b and 7 will be described as illustrative of the processing techniques employed. First,
a semiconducting wafer, preferably silicon or germanium, of the proper resistivity is lapped and polished
on one side. For this design, 3 ohm-cm, p-type germanium was used. The wafer was then subjected to
an antimony diffusion process which produced an ntype layer on the surface about 0.7 mil deep. The
wafer was then cut to the proper size, 0.200 inch ×
0.080 inch and the unpolished surface was lapped to
give a wafer thickness of 0.0025 inch.
Gold plated Kovar leads 50 were attached by alloying to the wafer in the proper positions (as shown).
Kovar is a trade name for an iron-nickel-cobalt alloy.
Gold was then evaporated through a mask to provide
the areas 51–54 which provide ohmic contact with the
n region, such as the transistor base connections and
the capacitor contacts. Aluminum was evaporated
through a properly shaped mask to provide the transistor emitter areas 56, which form rectifying contacts
with the n layer.
The wafer was then coated with a photosensitive
resist or lacquer, such as Eastman Photo Resist, supplied by Eastman Kodak Company, and exposed
through a negative to a light. The lacquer image
remaining after development was used as a resist
for etching the wafer to the proper shape. In particular, this etching forms a slot through the wafer
to provide isolation between R1 and R2 and the rest
of the circuit and also shapes all of the resistor
areas to the previously calculated configuration.
Either chemical etching or electrolytic etching may
be used, although electrolytic etching appears to be
preferable.
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After this step, the photoresist was removed with a
solvent and the mesa areas 60 masked by the same
photographic process. The water was again immersed
in etchant and the n layer completely removed in the
exposed areas. A chemical etch is considered preferable. The photoresist was then removed.
Gold wires 70 were then thermally bonded to the
appropriate areas to complete the connections and a
final clean-up etch given. Instead of using the gold
wires 70 in making electrical connections, connections may be provided in other ways. For example,
an insulating and inert material such as silicon oxide
may be evaporated onto the semiconductor circuit
wafer through a mask either to cover the wafer completely except at the points where electrical contact
is to be made thereto, or to cover only selected portions joining the points to be electrically connected.
Electrically conducting material such as gold may
then be laid down on the insulating material to make
the necessary electrical circuit connections.
After testing, the circuit may be hermetically sealed,
if required, for protection against contamination. The
finished device was smaller by several orders of magnitude than any others which have previously been
proposed. Because the fabrication steps required are
quite similar to those now used in manufacturing transistors and because of the relatively small number of
steps required, these devices are inherently inexpensive and reliable, as well as compact.
A further illustration of the process hereof is shown
in FIGURES 8a–8c. Each area of the single crystal
semiconductor wafer has been marked with a symbol
for the circuit element which it represents. This unit
illustrates the use of resistors, transistors, and a distributed R-C network to form a complete phase shift
oscillator.
It must be emphasized that the two embodiments
described above are merely two of innumerable circuits which can be fabricated by the techniques of the
present invention. There is no limit upon the complexity or configuration of circuits which can be made
in this manner. While there is a limit upon the types
and values of components which can be made in a
limited space, the invention hereof nevertheless represents a remarkable improvement over the prior art.
As evidence of the advance in the art accomplished
by the present invention, it is possible using the techniques described above to achieve component densities of greater than thirty million per cubic foot as
compared with five hundred thousand per cubic foot
which is the highest component density attained prior
to this invention.
Although the invention has been shown and
described in terms of specific embodiments, it will be
evident that changes and modifications are possible
which do not in fact depart from the inventive concepts taught herein. Hence, such changes and modi-
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fications are deemed to fall within the purview of the
invention.
What is claimed is:
1. In an integrated circuit having a plurality of electrical circuit components in a wafer of single-crystal semiconductor material, a plurality of junction
transistors defined in the wafer, each transistor
including thin layers of semiconductor material of
opposite conductivity-types adjacent one major
face of the wafer providing a base and an emitter
region which overlie a collector region, the baseemitter and base-collector junctions of each of said
transistors extending wholly to said one major
face, a plurality of thin elongated regions of the
wafer exhibiting substantial resistance to provide
semiconductor resistors, the elongated regions
being spaced on said one major face from the
transistors, and conductive means connecting
selected ones of the elongated regions to regions
of selected ones of the transistors.
2. In a semiconductor device which includes a
single-crystal semiconductor wafer: a junction
transistor provided adjacent one major face of the
wafer by thin layers of semiconductor material of
opposite conductivity types overlying one another
and extending to said one major face with the
emitter-base and base-collector junctions of the
transistor extending wholly to said one major face;
and a resistor provided in the wafer by a discrete
elongated region of the semiconductor material
which is spaced from the transistor on said one
major face.
3. An integrated circuit comprising a wafer of semiconductor material containing a plurality of electrical circuit components including at least one
active circuit component and at least one passive
circuit component, the active circuit component
including at least two thin layers of semiconductor
material of opposite conductivity-types extending
to one major face of the wafer with p-n junctions
of the active circuit component extending wholly
to said one major face, the passive circuit component including at least one discrete region of the
semiconductor material of the wafer which is
spaced on said one major face away from the thin
layers of the active component, substantial electrical impedance being exhibited between the semiconductor material contiguous to the at least one
discrete region of the passive component and
semiconductor material immediately underlying
said thin layers of the active component.
4. An integrated circuit according to claim 3 wherein
said active circuit component is a junction transistor, said passive circuit component is an elongated
resistor region, and said semiconductor material
immediately underlying said thin layers of the
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active component defines the collector region of
the junction transistor.
5. An integrated circuit according to claim 3 which
further comprises: at least one other active circuit
component provided in the wafer and including at
least two thin layers of semiconductor material of
opposite conductivity-types extending to said one
major face with p-n junctions of such other active
circuit component extending wholly to said one
major face; and at least one other passive circuit
component provided in the wafer and including at
least one discrete region of the semiconductor
material which is spaced on said one major face
away from the thin layers of the at least one other
active component.
6. An integrated circuit according to claim 5 wherein
said discrete regions of said passive circuit components include thin surface-adjacent regions at
said one major face of the wafer.
7. An integrated circuit according to claim 3 wherein
the at least one discrete region of the passive circuit component includes a thin surface-adjacent
layer of semiconductor material.
8. An integrated circuit according to claim 7 wherein
the passive circuit component is a resistor.
9. An integrated circuit according to claim 3 wherein
at least one of said circuit components includes a
thin layer of dielectric material overlying said one
major face of the wafer with a thin layer of conductive material overlying the dielectric material.
10. A semiconductor device comprising: a body of
single-crystal semiconductor material; an active
circuit component provided adjacent one major
face of the body and including thin regions of the
semiconductor material which extend to said one
major face, each of such regions being of different
conductivity than adjoining semiconductor material with the interface between each such region
and other of the semiconductor material of the
body extending wholly to said one major face; a
passive circuit component provided in the body
by a discrete portion of the semiconductor material which is spaced from the active circuit component on said one major face, substantial electrical impedance existing through the body between
said thin regions of the active circuit component
and the discrete portion of the passive circuit
component.
11. A semiconductor device according to claim 10
wherein at least part of said substantial electrical
impedance is exhibited by at least one p-n junction within the wafer.
12. An integrated circuit comprising a wafer of
single-crystal semiconductor material having a
plurality of electrical circuit components therein,
the components including an active circuit com-
Spring 2007
ponent which comprises thin regions of semiconductor material of opposite conductivity-types
closely adjacent one major face of the wafer with
p-n junctions between such thin regions extending wholly to said one major face, the components further including a semiconductor resistor
provided by a discrete elongated region of the
wafer which is spaced on said one major face
from the active circuit component, and a conductive lead connecting an end of the elongated
region to one of the thin regions of the active circuit component.
13. In an integrated circuit having a plurality of circuit
components in a wafer of single-crystal semiconductor material, a pair of junction transistors
defined in the wafer with each transistor including
thin layers of alternate conductivity type adjacent
one major face of the wafer providing a base and
an emitter region which overlie a collector region,
the base-emitter and collector-base junctions of
each of said transistors extending wholly to said
one major face, elongated semiconductor means
defined in the wafer and exhibiting substantial
resistance to provide load resistor means for the
pair of transistors, first conductive means connected to the collector region of one of the transistors and to an end of the elongated semiconductor means, second conductive means connected to the collector region of the other one of the
transistors and to an end of the elongated semiconductor means, means including contacts to the
emitter regions of the transistors and to the elongated semiconductor means for applying operating bias to the transistors and means including
separate contacts on said base regions for applying inputs to said pair of transistors.
14. In an integrated circuit according to claim 13 first
and second elongated semiconductor regions
defined in the wafer and exhibiting substantial
resistance to provide base resistors for the pair of
transistors, and conductive means separately connecting an end of the first elongated region to the
base region of one of the transistors and an end
of the second elongated region to the base region
of the other of the transistors.
15. An integrated circuit ahving a plurality of electrical
circuit components in a wafer of single-crystal semiconductor material, at least one of the components
being an active circuit component which includes
thin layers of semiconductor material of alternate
conductivity types defined in the wafer adjacent one
major face thereof with p-n junctions of such active
circuit component extending wholly to said one
major face, at least one of the components being a
passive circuit component which includes at least
one discrete region defined in the wafer, the passive
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circuit component being spaced on said one major
face from the active circuit component, substantial
electrical impedance being exhibited through the
wafer between the active circuit component and the
passive circuit component, a plurality of interconnections between selected ones of the electrical circuit components, the circuit components and interconnections being so arranged and constructed as
to allow, upon the application of electrical power,
the performance within the structure of an electrical
function equivalent to the function performed by a
plural element electrical network.
16. An integrated circuit comprising a wafer of
single-crystal semiconductor material containing a
plurality of electrical circuit components defined in
the wafer, the circuit components including an active
circuit component which comprises at least two thin
regions of the wafer of opposite conductivity-types
each extending to one major face with the junction
between each such thin region and other semiconductor material of the wafer extending to said one
major face, the circuit components further including
a passive circuit component which comprises at least
one discrete region of the semiconductor material,
the discrete region being spaced on said one major
face from the thin regions of the active circuit component, non-common regions of the active and passive circuit components being interconnected to
form at least part of an electrical circuit.
17. In a semiconductor device according to claim 2,
said thin layers of said junction transistor being
portions of a raised mesa-shaped part of said one
major face.
18. An integrated circuit according to claim 3 wherein said active circuit component is a junction transistor with said two thin layers being the base and
emitter regions of said junction transistor, the
emitter region being substantially smaller than the
base region on said one major face, a base contact being positioned on said base region spaced
from the emitter region.
19. An integrated circuit according to claim 18 wherein said discrete region of the passive circuit component includes a thin surface-adjacent layer of
semiconductor material of conductivity-type
opposite that of subjacent semiconductor material, an ohmic contact is provided on said surfaceadjacent layer, and a conductive lead connects
such ohmic contact to said base contact.
20. A semiconductor device according to claim 10
wherein said passive circuit component provided
in the body by said discrete portion of the semiconductor material includes a thin surface-adjacent portion of the semiconductor material at said
one major face of the body, such thin portion
being of conductivity differing from subjacent
semiconductor material.
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IEEE SSCS NEWS
21. A semiconductor device according to claim 20
wherein separate electrical contacts are provided on
at least two of said thin regions of the active circuit
component on said one major face, wherein a contact is provided on said thin surface-adjacent portion on said one major face, and wherein conductive means interconnects said contact on said surface-adjacent portion with one of said contacts on
said thin regions of the active circuit component.
22. In an integrated circuit according to claim 13 said
elongated semiconductor means being a single
elongated region of the semiconductor material
with said first and second conductive means being
separately connected to opposite ends of such
elongated region and with said means for applying operating bias being connected to a centrally
located portion of such elongated region.
23. In an integrated circuit according to claim 13 said
means for applying inputs to said pair of transistors
includes separate coupling means connecting the
first conductive means to the contact on the base
region of said one of the transistors and connecting
the second conductive means to the contact on the
base region of said other one of the transistors.
24. An integrated circuit according to claim 16 wherein said discrete region of the passive circuit component includes a thin surface-adjacent region of
conductivity type opposite to that of subjacent
semiconductor material.
25. An integrated circuit according to claim 24 wherein said passive circuit component is a P–N junction capacitor.
References Cited in the file of this patent
UNITED STATES PATENTS
2,493,199
Khouri
Jan. 3, 1950
2,748,041
Leverenz
May 29, 1956
2,816,228
Johnson
Dec. 10, 1957
2,817,048
Thuermel
Dec. 17, 1957
2,824,977
Pankove
Feb. 25, 1958
2,836,776
Ishikawa
May 27, 1958
2,878,147
Beale
Mar. 17, 1959
2,915,647
Ebers
Dec. 1, 1959
2,916,408
Freedman
Dec. 8, 1959
2,922,937
Hutzler
Jan. 26, 1960
2,935,668
Robinson et al.
May 3, 1960
2,995,686
Selvin
Aug. 8, 1961
2,998,550
Collins et al.
Aug. 29, 1961
United States Patent Office
3,138,743
Patented June 23, 1964
Jack S. Kilby, Dallas, Tex., assignor to Texas Instruments Incorporated, Dallas, Tex., a corporation of
Delaware
Filed Feb. 6, 1959, Ser. No. 791,602
25 Claims. (Cl. 317-101)
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Asad Abidi, Mark Horowitz and Teresa Meng
Elected to U.S. National Academy of Engineering
Asad Ali Abidi,
Professor, Electrical
Engineering
Department, University of California, Los Angeles
Mark A. Horowitz,
Professor of Electrical Engineering
and Computer Science, Stanford University, Stanford,
CA
Teresa H. Meng,
Reid Weaver Dennis Professor of
Electrical Engineering, Stanford
University, Stanford, CA
for contributions to the development
of integrated circuits for MOS RF communications.
for leadership in high-bandwidth
memory-interface technology and
in scalable cache-coherent multiprocessor architectures.
for pioneering the development
of distributed wireless network
technology.
Asad A. Abidi, an elected member of the SSCS AdCom from 19982003 and past secretary who has
also served the Society as a Distinguished Lecturer, received the B.Sc
degree with honors from Imperial
College, London in 1976 and the
M.S. and Ph.D. degrees in Electrical Engineering from the University of California, Berkeley in 1978
and 1981. He was at Bell Laboratories, Murray Hill, NJ from 1981 to
1984 as a Member of Technical
Staff in the Advanced LSI Development Laboratory. Since 1985, he
has been at the Electrical Engineering Department of the University of California, Los Angeles
where he is Professor.
His research interests are in
CMOS RF design, data high-speed
analog integrated circuit design,
conversion, and other techniques
of analog signal processing.
Dr. Abidi was the Program Secretary for ISSCC from 1984 to 1990,
and General Chairman of the Symposium on VLSI Circuits in 1992.
He was Secretary of the IEEE Solidstate Circuits Council from 1990 to
1991. From 1992 to 1995, he was
Editor of the IEEE Journal of Solidstate Circuits. He has received the
1988 TRW Award for Innovative
Teaching and the 1997 IEEE Donald G. Fink Prize Paper Award. He
was a corecipient of the Best Paper
Award at the 1995 European Solidstate Circuits Conference, received
the Design Contest Award at the
1998 Design Automation Confer-
ence, and received the 1996 Jack
Kilby Best Student Paper Award,,
the 1997 Jack Raper Award for
Outstanding Technology Directions Paper from ISSCC.. He is an
IEEE Fellow.
Mark Horowitz, an elected
member of the SSCS AdCom in
1999-2001, is the Yahoo! Founder's
Professor of Electrical Engineering
and Computer Science at Stanford
University. He received his BS and
MS in Electrical Engineering from
MIT in 1978, and his Ph.D. from
Stanford in 1984. Dr. Horowitz is
the recipient of a 1985 Presidential
Young Investigator Award, and an
IBM Faculty development award, as
well as the 1993 best paper award
at the International Solid State Circuits Conference. In 1990, he took
leave from Stanford to found Rambus, Inc., an IP company that has
focused on high-speed memory
interfaces. This has led to numerous
patents in the area of both highspeed interface technology, and
advanced memory interfaces. In
1999 he was a finalist for the World
Technology Award for his work on
developing the Rambus technology.
He is an IEEE Fellow
Dr. Horowitz’s past research
work has spanned a wide range of
areas in digital system design, from
working on CAD tools to highspeed and low-power circuit
design, to work in computer architecture. Recently his research
group has worked on the design of
processors, memories and IO
F
ormer SSCS officers and
AdCom members Asad Abidi,
Mark Horowitz, and Teresa
Meng were among 64 Americans
and nine foreign associates elected
in January to the National Academy
of Engineering Class of 2007.
Election to the National Academy
of Engineering is among the highest
professional distinctions accorded
to an engineer. Founded in 1964,
the NAE now has 2,217 peer-elected members and 188 foreign associates who are among the world’s
most accomplished engineers.
Academy membership honors
those who have made outstanding
contributions
to
engineering
research, practice, or education,
and to the pioneering of new and
developing fields of technology,
making major advancements in traditional fields of engineering, or
developing/implementing innovative approaches to engineering
education.
The National Academy of Engineering (NAE) is a private, independent, nonprofit institution
chartered to provide engineering
leadership in service to the nation.
In addition to its role as advisor to
the federal government, the NAE
also conducts independent studies
to examine important topics in
engineering and technology. NAE
members provide the expertise for
numerous projects focused on the
relationships between engineering, technology, and the quality
of life.
Spring 2007
IEEE SSCS NEWSL
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PEOPLE
devices. This work has lead to a
number of outstanding research
results, from the highest speed
CMOS IO (5Gb/s in a 0.5mm
CMOS technology), to the lowest
power SRAM memory design.
In addition to his work on VLSI,
Dr. Horowitz has led a number of
architecture programs, including
some of initial work in RISC
processor design. More recently he
co-directed the FLASH project with
John Hennessy. This program has
demonstrated the feasibility of creating a flexible memory controller
that can support both DSM and
message passing. His most recent
project was the design of a new
computing framework that could
support a larger class of applications, which led to the Smart
Memory project.
Teresa H. Meng, an elected
member of the SSCS AdCom in
2003-2005, is the Reid Weaver Dennis Professor of Electrical Engineer-
ing at Stanford University. Her
research activities during the first 10
years at Stanford included lowpower circuit and system design,
video signal processing, and wireless communications. She has
received many awards and honors
for her research work at Stanford: an
NSF Presidential Young Investigator
Award, an ONR Young Investigator
Award, an IBM Faculty Development Award, a Best Paper Award
and a Distinguished Lecturer Award
from the IEEE Signal Processing
Society, the Eli Jury Award from U.C.
Berkeley, and awards from AT&T,
Okawa Foundation and other industry and academic organizations.
In 1999, Dr. Meng took leave
from Stanford and founded Atheros Communications, Inc., which
provides leading wireless system
solutions for transparent connections of data, video, and voice
communications. As a result of this
effort, Dr. Meng was named one of
the Top 10 Entrepreneurs in 2001
by Red Herring, Innovator of the
Year in 2002 by MIT Sloan School
eBA, the CIO 20/20 Vision Award
in 2002, and the DEMO@15 WorldClass Innovator Award in 2005. She
returned to Stanford in 2000 to
continue her research and teaching
at the University.
Dr. Meng's current research
interests focus on circuit optimization, neural signal processing, and
computation architectures for
future scaled CMOS technology.
She has given plenary talks at
major conferences in the areas of
signal processing and wireless
communications. She is the author
of one book, several book chapters, and over 200 technical articles
in journals and conferences. Dr.
Meng is a Fellow of the IEEE. She
received her M.S. and Ph.D. in
EECS from the University of California at Berkeley and her B.S.
from National Taiwan University.
Yannis P. Tsividis and Hugo De Man Receive IEEE
Field Awards at ISSCC 2007
Katherine Olstein, SSCS Administrator, k.olstein@ieee.org
Y
According to a Tsividis
annis P. Tsividis
colleague,
said Terman, “Dr.
received the IEEE
Tsividis’
textbook,
‘OperaGustav Robert Kirchtion
and
Modeling
of the
hoff Award in a ceremony
MOS
Transistor,’
along
with
during the Plenary Session
his
constant
preaching
to
the
of ISSCC 2007 in San FranCAD
community
about
the
cisco on 12 February 2007.
inadequacy of MOSFET
In the same ceremony,
models for analog design,
Hugo De Man, Professor
was instrumental in the creEmeritus, Katholieke Univeration of the models such as
siteit Leuven, received the
the EKV and other compact
IEEE Donald O. Pederson
models. It is ironic that the
Award in Solid-State Circuits.
IEEE President-Elect Lewis Lewis Terman, IEEE President-Elect (right), presented best reference on MOS tranTerman presented the Kirch- the IEEE Gustav Robert Kirchhoff Award to Yannis P. sistor modeling was written
by a circuits guy.”
hoff award to Dr. Tsividis, Tsividis at the plenary session of the ISSCC 2007.
De Man was acknowlthe Charles Batchelor Memoedged
for
leadership in solid-state
wrote,
“Yannis
invented,
along
rial Professor of Electrical Engineercircuit
design
and integrated circuit
with
his
students,
the
MOSFET-C
ing at Columbia University, on
design
methodology.
filtering
approach
in
the
1980s.
…
behalf of the IEEE Board of DirecTerman reported that one nomitors for his contributions to circuits This work had significant commerand MOS device modeling.
cial impact as well as spurring on nator said, “In his leadership work
with the Esprit program, and then
Terman said one nominator new fields of research.”
56
IEEE SSCS NEWS
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Lewis Terman (right), presented the IEEE Donald
O.Pederson Award to Hugo De Man at the plenary session of the ISSCC 2007.
with the EDAC/DATE conferences,
just to name two, Professor De
Man has continued to push for a
strong European presence in
design and in design technology
for over three decades.”
Terman said an endorser
remarked, “Another aspect of Professor De Man’s contribution to
Solid State science concerns education. He played a leading role in
the development of a solid curriculum at Katholieke Universiteit,
Leuven that takes advantage of his
thorough background. Many generations of students owe their I.C.
system design and CAD education
profiles to Professor De Man.”
In his acceptance remarks, De
Man said, “This award has a very
deep and special meaning to me,
as Don Pederson together with
Roger Van Overstraeten, were my
great mentors. They have shaped
my professional and personal life.
Without them I would not be
“My thanks go to my wife for supporting this foolish
engineer spending day and night with technology and,
like a drunk, promising it would be better next week.
She has given up that illusion but not her support.
standing here. From Thanks Maria, and thanks to Annemie, my secretary for
them I learned that 25 years for keeping order in my otherwise chaotic
scientific and tech- administrative behavior.” Hugo De Man
nological research
only flourishes when you surround
yourself with creative people, better than yourself, and motivate
them to work as a team to make
the most ambitious dreams come
true. This award therefore is also
an award to the many fine people that I had the privilege to
work with.”
“Looking back at this, I feel that
there is no greater reward for a
professor than to see how your
students have become the technical leaders of tomorrow. So I am
deeply grateful to my 60 and more
Ph.D. students and hundreds of
master students who really did the
work and now are paving the way
to the future on all continents. I
can now retire without regret.”
The IEEE Gustav Robert Kirchhoff Award is sponsored by the
IEEE Circuits and Systems Society
and recognizes outstanding contributions to the fundamentals of any
aspect of electronic circuits and
systems that has a long-term significance or impact. The IEEE Donald
O. Pederson Award in Solid-State
Circuits is sponsored by the IEEE
Solid-State Circuits Society and recognizes outstanding contributions
to solid-state circuits.
“IEEE and its predecessor societies, the AIEE and the IRE, have
been recognizing outstanding contributions for over a century,” said
Terman. “With these awards, the
IEEE recognizes that these talented
and brilliant individuals also have
helped to further the mission of the
IEEE to promote the creation of
new technologies for the benefit of
humanity and the profession.”
SSCS Nominees Recognized at ISSCC Plenary for
Elevation to Fellow
17 SSCS Members Join IEEE Fellow Class of 2006
Katherine Olstein, SSCS Adminstrator, k.olstein@ieee.org
A
t the ISSCC Awards Ceremony on 12 February 2007 in
San Francisco, SSCS past
President and IEEE President-Elect
Lewis Terman congratulated mem-
Spring 2007
bers of SSCS whom the Society
nominated for elevation to IEEE Fellow in the Class of 2006: Kerry
Bernstein, Wanda Gass, Takayuki
Kawahara, Stefan Rusu, and
Masakazu Yamashina. Dr. Sehat
Sutardja was unable to attend.
“IEEE Fellows are an elite
group,” said Terman. “The IEEE
looks to the Fellows for guidance
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Bernstein is a staff instructor at
RUNN/Marine Biological Laboratories, Woods Hole, MA. He and his
family live in Northern Vermont.
Wanda Gass
Texas Instruments,
Inc.
From left, Lewis Terman IEEE President-Elect and 2006 Fellows Masakazu
Yamashina, Stefan Rusu, Takayuki Kawahara, Wanda Gass, and Kerry Bernstein.
Dr. Sehat Sutardja was unable to attend.
and leadership as the world of
electrical and electronic technology and information sciences continues to evolve.”
Eleven more members of the
Society attained the distinction of
Fellow on the recommendation of
other IEEE Societies:
Kenneth Kundert
Orly Yadid-Pecht
Athanasios Stouraitis
Luca Benini
Clark Nguyen
Jayasimha Prasad
Yuhua Cheng
David Plant
Stefan Heinen
John Wood
Bumman Kim
(CAS)
(CAS)
(CAS)
(CAS)
(ED)
(ED)
(ED)
(LEO)
(MTT)
(MTT)
(MTT)
The IEEE Fellow Class of 2007
comprises a total of 268 members.
The distinction, conferred by the
IEEE board of Directors, recognizes extraordinary contributions
to one or more fields of IEEE interest. No more than one-tenth of one
percent of the Institute membership may be elevated to Fellow in
a given year.
Kerry Bernstein
IBM
for contributions to
high performance
common metal
oxide semiconductor circuit design
Kerry Bernstein is a Senior Technical Staff Member at the IBM T.J.
Watson Research Center, Yorktown
Hts, NY. He currently is Principal
58
IEEE SSCS NEWS
Investigator for 3D integration
technology at IBM Research,
exploring 3D design and architecture. Mr. Bernstein received the
B.S. degree in electrical engineering degree from Washington University in St.Louis, and joined IBM
in 1978. Mr. Bernstein’s work has
bridged technology and circuit
design, and has explored the technology sensitivities of high performance CMOS circuit topologies,
the mitigation of delay variability,
and soft-error modeling. He served
as lead technologist for IBM’s server and PowerPC processor designs
and for IBM’s external foundry
customers. Mr. Bernstein has had
the privilege of participating in the
roll-out of fundamental device and
interconnect technologies throughout his career, such as CMOS, partially-depleted Silicon-On-Insulator
devices,
and copper interconnects. He holds 50 U.S. patents in
the areas of high performance circuits and technology. Mr. Bernstein co-authored 2 college textbooks with colleague and friend
Norman Rohrer, and approximately 100 papers or book chapters on
high speed / low power CMOS. He
attributes any success he has
enjoyed to be due in large part to
working with wonderful people.
Mr. Bernstein has served on the
program committees for IEEE
ISSCC and Symposium on VLSI
Design. He derives fulfillment as
an industrial mentor for students
and research at SEMATECH,
SRC/MARCO, DARPA, and for high
schoolers interested in math/science/engineering careers. Mr.
for contributions to
digital signal processors and circuits
Wanda Gass received a BSEE
degree in 1978 from Rice University and MS degree in Biomedical
Engineering from Duke University
in 1980. She has been with Texas
Instruments since 1980 where she
is a TI Fellow. She was a key contributor in the development of the
first programmable DSP at TI for
which she holds several strategic
patents. During her career she has
done work in VLSI design, algorithms for speech codecs, multiprocessor system design for
speech recognition and image processing, silicon compilers for DSP
functions, video compression VLSI
architectures, and W-CDMA hardware and software implementations. Currently she defines the
instruction set architecture for
high-performance DSP processors.
She is an active member in the
Signal Processing Society and the
Solid-State Circuits Society. In the
SSCS she has served as Member
(1995-1999) and Subcommittee
Chair (2000-2005) of ISSCC International Program Committee and
is serving as elected member of
SSCS Ad Com. In the SPS she has
served as Member (1990-1996)
and Chair (1997-1999) of Design
and Implementation of Signal Processing Systems Technical Committee. She was General Chair of
the Signal Processing System
Workshops in 2004.
She is a member of the
Founder’s Circle for the Women of
TI Fund that promotes the education of girls in the fields of science,
technology, engineering and math.
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She was inducted into the WITI
Hall of Fame in 2003 and is on the
Board of Directors for the nonprofit organization, Alliance of
Technology and Women. She is
married to Richard and has two
daughters in the 11th and 8th
grades.
Takayuki Kawahara
Central Research
Laboratory, Hitachi
Ltd.
for contributions to
low-voltage lowpower random
access memory circuits
Takayuki Kawahara received
B.S. and M.S. degrees in physics in
1983 and 1985, and Ph.D. degree
in electronics in 1993 from Kyushu
University, Fukuoka, Japan.
In 1985, he joined Central
Research Laboratory, Hitachi Ltd.
Since then, he has made fundamental contributions in many areas
in the field of low-voltage lowpower memories. As early as 1991,
as a pioneer, he invented and initiated research and development of
circuits to reduce the subthreshold
current of MOSFETs, a key issue
today in low-voltage CMOS LSI
designs. A distinctive circuit that he
and his team invented and developed was the gate-source selfreverse biasing circuit, which was
applied to the word-driver block in
the world’s first 256-Mb DRAM. He
also pioneered the charge-recycling scheme; it is now widely recognized to be applicable to various
logic circuits. His team’s recent
development is the back-gate-controlled thin BOX FD-SOI SRAM
technology, a strong candidate for
next-generation CMOS technology
that results in reduced variation
and dynamic control of the threshold voltage of MOSFET. Currently,
his mission is exploring a new concept memory. Especially, his intention is to develop the spin transfer
torque memory for low power,
high density universal memory.
Spring 2007
He was a visiting researcher at
Electronics Laboratory (LEG),
Swiss Federal Institute of Technology, Lausanne (EPFL) from 1997 to
1998. He was a guest editor of
Memory part of special issue of
JSSC, November 2002. He has been
a member of the ISSCC program
committee since 2000 (also executive committee member as FE officer since 2004), and a program
committee member of the Symposium on VLSI Circuits since 2003
(also a secretary/publicity chair of
2006/2007 JFE Circuits Symposium
Committee).
Stefan Rusu
Intel Corporation
for contributions to
high performance
microprocessor circuit technologies
Stefan Rusu (M’85-SM’01-F’07)
received the MSEE degree from the
Polytechnic University in Bucharest,
Romania. He first joined Intel Corp.
in 1984 working on data communications integrated circuits. In 1988
he joined Sun Microsystems working on microprocessor design with
focus on clock and power distribution, packaging, standard cell
libraries, CAD and circuit design
methodology. He re-joined Intel
Corp. in 1996 working on the global circuit technology for several Itanium® and Xeon® processors. He
is presently a Senior Principal Engineer in Intel's Enterprise Microprocessor Group leading the technology and special circuits design
team for the Xeon® MP Processors
Family. His technical interests are
high-speed clocking, power distribution, I/O buffers, power and
leakage reduction, and high-speed
circuit design techniques. Stefan
has authored or co-authored more
than 75 papers on VLSI design
methodology and microprocessor
circuit technology. He holds 30
U.S. patents with several more
pending. He is a member of the
Technical Program Committee for
the ISSCC, ESSCIRC and A-SSCC
conferences and an Associate Editor of the IEEE Journal of SolidState Circuits.
Sehat Sutardja
Marvell Semiconductor, Inc.
for leadership in
design and commercialization of
high-speed mixedsignal common metal oxide semiconductors integrated circuits
Dr. Sehat Sutardja has served as
President of Marvell Technology
Group Ltd. since its inception and
as Chairman of the Board and
Chief Executive Officer since 1995.
In addition, he has served as President, Chief Executive Officer and a
Director of Marvell Semiconductor,
Inc. since its inception. From 1989
until 1995, Dr. Sutardja served as a
manager and principal project
engineer at 8X8, Inc., a designer
and manufacturer of digital communications products. Dr. Sutardja
holds Master of Science and PhD
degrees in Electrical Engineering
and Computer Science from the
University of California at Berkeley.
Masakazu
Yamashina
NEC Electronics
Corporation
for leadership in high
performance microprocessor circuits
Masakazu Yamashina received
the B.S., M.S. and Ph.D. degrees
from the Tokyo Institute of Technology, Japan, in 1982, 1984 and
1993, respectively. In 1984 he
joined NEC Corporation in
Kawasaki, Japan, where he has
been a technical leader in the
research and the development of
high-performance microprocessor
circuits such as video signal
processors, high-speed microprocessors, dynamically reconfig-
IEEE SSCS NEWS
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urable processors, and low power
single-chip multiprocessors. From
1989 through 1990, he was a visiting researcher at Stanford University, where he worked on software to control autonomous
robot LSIs. Presently he is a general manager of the mobile LSI
division in NEC Electronics and
leading the development of the
low power microprocessors for
mobile devices.
Dr. Yamashina published 19
ISSCC papers from 1987 to 2000.
In 2003, he received a Top-10
ISSCC author award in terms of
number of ISSCC papers in the
ISSCC’s 50-year history. He has
worked in the semiconductor
industry for 22 years and published
246 technical publications, such as
the world’s first CMOS programmable video signal processor and low
power multi-threading microprocessor. He has also been a visiting professor for the Tohoku University and the Tokyo Institute of
Technology. He served IEEE as an
administrative committee member
of the IEEE Solid-State Circuits
Society, executive committee member of ISSCC, symposium chair and
program chair of the IEEE Sympo-
sium on VLSI Circuits, and guest
editor of IEEE Journal of Solid-State
Circuits.
SSCS members evaluated by
other IEEE societies within the
IEEE Fellow Class of 2006 are:
Huijsing, Makinwa, and Pertijs Receive JSSC 2005
Best Paper Award
D
rs. Michiel. A. P. Pertijs, Kofi
A. A. Makinwa, and Johan
H. Huijsing were honored
at the Plenary Session of the ISSCC
in San Francisco on 12 February for
the selection of their paper “A
CMOS Smart Temperature Sensor
With a 3σ Inaccuracy of ±0.1°C
from -55°C to 125°C” as the best in
the JSSC for the year 2005. It was
published the December issue, and
is available in IEEE XPlore. The editors of the Journal award this prize
every year.
K. Nagaraj, chief JSSC Editor
said, “This paper describes a fully
integrated CMOS temperature sensor achieving an accuracy of +/0.1 % over the temperature range
of -55 degrees C to 125 degrees C.
Such high precision is achieved by
60
IEEE SSCS NEWS
(From left) Richard C. Jaeger, SSCS President with Dr. Johan H. Huijsing, Dr.
Kofi A. A. Makinwa, Dr. Michiel A. Pertis and Laura Fujino, ISSCC Director of
Publications.
using several circuit techniques
including dynamic element matching, a chopped current gain independent PTAT bias circuit, and a
low-offset second-order sigma-
delta ADC that combines chopping and correlated double sampling. It will have applications in
instrumentation, measurement and
control.”
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Abstract—A smart temperature
sensor in 0.7 μm CMOS is accurate
to within ± 0.1° C (3σ ) over the
full military temperature range of 55° C to 125 ° C. The sensor uses
substrate PNP transistors to measure temperature. Errors resulting
from nonidealities in the readout
circuitry are reduced to the 0.01° C
level. This is achieved by using
dynamic element matching, a
chopped current-gain independent
PTAT bias circuit, and a low-offset
second-order sigma-delta ADC that
combines chopping and correlated
double sampling. Spread of the
base-emitter voltage characteristics
of the substrate PNP transistors is
compensated by trimming, based
on a calibration at one temperature. A high trimming resolution is
obtained by using a sigma-delta
current DAC to fine-tune the bias
current of the bipolar transistors.
Fig. 1. Operating principle of the
temperature sensor.
Fig.13. Chip micrograph of the temperature sensor.
Kofi Makinwa holds degrees from
Obafemi Awolowo University, IleIfe (B.Sc., M.Sc.), Philips International Institute, Eindhoven (M.E.E.),
and Delft University of Technology,
Delft (Ph.D.). From 1989 to 1999,
he was a research scientist at
Philips Research Laboratories,
where he designed sensor systems
for interactive displays, and analog
front-ends for optical and magnetic
Spring 2007
recording systems. In 1999 he
joined Delft University of Technology, where he is currently an Associate Professor at the Electronic
Instrumentation Laboratory.
Dr. Makinwa holds nine US
patents, and has authored or coauthored over 40 technical papers.
He has given tutorials at the
Eurosensors and IEEE Sensors conferences. He is on the program
committees of several international
conferences, including the International Solid-State Circuits Conference (ISSCC) and the International
Solid-state Sensors and Actuators
Conference (Transducers). His
main research interests are in the
design of precision analog circuitry, sigma-delta modulators and
smart sensors.
For his Ph.D. thesis, Dr. Makinwa
was awarded the title of ‘Simon
Stevin Gezel’ by the Dutch Technology Foundation (STW). In 2005, he
received a VENI award from the
Dutch Scientific Foundation (NWO).
He is a co-recipient of the ISSCC 2006
Jan van Vessem best paper award,
the ISSCC 2005 Jack Kilby best student paper award, and the Journal of
Solid-State Circuits 2005 best paper
award. In 2007, he became a Young
Fellow of the Royal Netherlands
Academy of Arts and Sciences.
Michiel Pertijs received the M.Sc.
and Ph.D. degrees in electrical
engineering from Delft University
Technology in 2000 and 2005,
respectively. From 1997 to 1999 he
worked part-time for EARS B.V.,
Delft, The Netherlands, on the
production and development of a
handheld photosynthesis meter.
From 2000 to 2005 he worked as a
research assistant at the Electronic
Instrumentation Laboratory of
Delft University, where he performed research on the subject of
precision smart temperature sensors. In context of this research, he
developed several precision temperature sensors in cooperation
with Philips Semiconductors, Sun-
nyvale, California. Since August
2005, he has worked for National
Semiconductor in Delft. His
research interests include analog
and mixed-signal interface electronics and smart sensors.
Johan H. Huijsing received the
M.Sc. degree in electrical engineering from Delft University of Technology, Delft, The Netherlands, in
1969, and the Ph.D.degree from
the same university in 1981 for his
thesis on operational amplifiers.
He joined the Faculty of Electrical
Engineering of Delft University of
Technology in 1969, became full
Professor in the chair of Electronic
Instrumentation in 1990, and has
been Professor Emeritus since 2003.
From 1982 to 1983, he was a Senior
scientist at Philips Research Laboratories, Sunnyvale, CA. After 1983, he
was a consultant for Philips Semiconductors, Sunnyvale and after
1998, a consultant for Maxim, Sunnyvale. His research work is
focused on the systematic analysis
and
design
of
operational
amplifiers, analog-to-digital converters, and integrated smart sensors. He is author or co-author of
some 200 scientific papers, 40
patents and nine books, and co-editor of 11 books.
Dr. Huijsing is a Fellow of IEEE
for contributions to the design
and analysis of analog integrated
circuits. He was awarded the title
of ‘Simon Stevin Meester’ for
Applied Research by the Dutch
Technology Foundation. He is
initiator and co-chairman of the
International Workshop on
Advances in Analog Circuit Design, which has been held annually since 1992 in Europe. He was a
member of the program committee of the European Solid-State
Circuits Conference from 1992 to
2002. He has been chairman of
the Dutch STW Platform on Sensor Technology and chairman of
the biennial National Workshop
on Sensor Technology from 1991
until 2002.
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Best Student Design Awards Presented at ISSCC 2007
Bruce Hecht, SSCS Membership Chair, bruce.hecht@analog.com, and Katherine Olstein, SSCS
Administrator, k.olstein@ieee.org
T
he winners of the DAC and ASSCC Student Design Contests
of 2006 presented their work
in two evening poster sessions at
ISSCC 2007 in San Francisco.
The A-SSCC prize winners were
honored at the conference in
November, 2006. The DAC awardees
will be formally acknowledged at
the 44th Design Automation Conference in San Diego, California in
June, 2007.
48 papers were submitted from
15 countries for the ten DAC
awards. “This was an excellent
year, “said Bill Bowhill, a Co-Chair
of the contest. “The winners have
outstanding designs. Many of the
students showed demonstrations
of their designs at the conference
which generated much interest
from the attendees.”
Award-winning projects were
not ranked for the first time this
year due to past difficulties in
comparing papers dealing with
very different topics and/or technologies. There was no clear outstanding paper for “best overall,”
said Kaushik Roy, DAC Design
Community Chair. “Since many
EMS/sensors and ADC papers
were submitted this year, more
support from Data Converters and
Sensor ISSCC committees will be
added next year,” he said. The
DAC student contest is restricted to
designs originating in university
undergraduate or graduate course
work or research.
CHIP/SYSTEM OPERATIONAL
62
CMOS technology and external
receiver are presented. The
implantable sensor and transponder design supporting load modulation demonstrated promising
performance: 132μA with 6bit
accuracy.
SYSTEM OPERATIONAL CATEGORY
HBS: a Handheld Breast Cancer
Detector Based on Frequency
Domain Photon Migration
Keun Sik No et al. University of
California, Irvine, USA
This paper presents a non-invasive handheld breast cancer detector using frequency domain photon migration spectroscopy. The
receiver is in heterodyne topology
and detects broadband-modulated
(10MHz – 1GHz) signal. A performance similar to that of laser
based system is demonstrated
Keun Sik No of UC Irvine explained
that his hand-held breast cancer
detector “can actually see the inside
contents of the tissue,” unlike xray
mammograms and MRI’s. In post-doc
work he plans to make the device
smaller and cheaper so it can be
used by patients at home as often as
every hour or half hour to monitor
the progress of chemotherapy. Mr.
No said he has been interested in
electronics “ever since I was a kid.”
A Wireless Implantable Microsystem for Continuous Blood Glucose Monitoring
Mohammad M Ahmadi, Graham A
Jullien, University of Calgary,
Canada
CHIP OPERATIONAL CATEGORY
An amperometric glucose sensor, transpondor chip in 0.18μm
Design of an Ultra-Low-Voltage
UWB Baseband Processor
Vivienne Sze, Anantha Chan-
IEEE SSCS NEWS
drakasan Massachusetts Institute of
Technology, USA
A 100Mbps throughput UWB
baseband processor operating at a
sub-threshold supply voltage of
0.4V is presented. This work
demonstrates the application of
sub-threshold design to high performance systems using parallelism.
An Energy-Efficient Reconfigurable Multiprocessor IC for
DSP Applications
Guichang Zhong, Alan N Wilson,
University of California, Los Angeles, USA
This work presents a low-power
reconfigurable multiprocessor with
a performance close to ASIC solutions while possessing a degree of
flexibility.
A 94dB SFDR 78dB DR 2.2MHz
BW Multi-bit Delta-Sigma Modulator with Noise Shaping DAC
Jianzhong Chen, Yong Ping Xu,
National University of Singapore,
Singapore
The works presents a multi-bit
low-pass delta-sigma modulator
employing a noise shaping dynamic matching technique that
improves both SFDR and SNR.
A 230mV-to-500mV 375KHz-to16MHz 32b RISC Core in
0.18µm CMOS
Chen Jian-Shiun, Yi-Ming Wang,
Yu-Juey Chang, Jinn-Shyan Wang,
Chingwei Yeh, Tien-Fu Chen,
National Chung-Cheng University
Taiwan R.O.C
This work presents a low supply
voltage, 230-500mV, RISC core with
375KHz-1MHz clock frequencies. The
ultra-low voltage CMOS technique
such as dynamic NP-swappable body
bias scheme is extensively studied.
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A 152mW/195mW Multimedia
Processor with Fully Programmable 3D Graphics and MPEG/
H.264/JPEG for Handheld Devices
Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo
Jeong, Suk Joong Lee, Hoi-Jun Yoo
KAIST, South Korea
dard video decoder supporting
JPEG, MPEG-1,2,4, and H.264 for
HD video applications. Active
hardware sharing scheme and techniques that can reduce memory
bandwidth are proposed. The chip
consumes 71.1mW at 120MHz/1V
and 7.9mW at 20MHz/0.8V.
This work presents a multimedia
SoC including MPEG4 codec,
H.264 decoder, JPEG codec, and
fully programmable 3D graphics
engine. The proposed JPEG/MPEG
hybrid design provides small area
and low power design. The SoC
consumes 152mW at 48MHz operating frequency.
A 152mW/195mW Multimedia
Processor with Fully Programmable 3D Graphics and MPEG/
H.264/JPEG for Handheld Devices
Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Jongcheol Jeong, Euljoo
Jeong, Suk Joong Lee, Hoi-Jun Yoo
KAIST, South Korea
A 252Kgates/4.9Kbytes SRAM/
71mW Multi-Standard Video
Decoder for High Definition
Video Applications
Chih-Da Chien, Chien-Chang Lin,
Yi-Hung Shih, He-Chun Chen,
Chih-Wei Wang, Cheng-Yen Yu,
Chih-Liang Chen, Ching-Hwa
Cheng, Jiun-In Guo
National Chung-Cheng University
Taiwan R.O.C.
Feng-chia University Taiwan R.O.C.
This paper presents a multi-stan-
This work presents a multimedia
SoC including MPEG4 codec,
H.264 decoder, JPEG codec, and
fully programmable 3D graphics
engine. The proposed JPEG/MPEG
hybrid design provides small area
and low power design. The SoC
consumes 152mW at 48MHz operating frequency.
CONCEPTUAL [functional silicon
shown at conference]
The Scale Vector-Thread Processor
Ronny Krashinsky, Christopher
Batten, Krste Asanovic, Massa-
chusetts Institute of Technology,
USA
This work presents the scale vector-thread processor as a complexity-effective solution for embedded
computing. An efficient design flow
and low power design techniques
are thoroughly explored. It demonstrates the potential performance of
the vector-thread unit.
The A-SSCC posters were:
A 1.5 MS/s 6-bit ADC with 0.5V
Supply
Simone Gambini, Jan Rabaey, UC
Berkeley
A TCAM-based Periodic Event
Generator for Multi-Node Management in the Body Sensor
Network
Sungdae Choi, Kyomin Sohn, Jooyoung Kim, Jerald Yoo, Hoi-Jun
Yoo, Kaist, Daejeon Korea
A 0.98 to 6.6 GHz Tunable Wideband VCO in a 180 nm CMOS
Technology for Reconfigurable
Radio Transceiver
Tusaku Ito, Hirotaka Sugarawa,
Kenichi Okada, Kazuya Masu
Tokyo Institute of Technology
“Vector-threaded architecture is able to exploit both data
parallel vector computation and act as a highly multithreaded engine,” said designer Ronny Krashinsky of MIT.
“We wanted to find a flexible architecture that could execute many different types of embedded applications like
graphics, network processing, and cryptography.”
“The basic interface to the architecture is virtual processors; each typically executes one iteration of a loop,” he
said. “If it’s a vectorizable loop, it’s executed purely with
vector instructions. But if the loop has conditional operations, then each of those virtual processors can take a
conditional branch to direct their own control flow. So the
overhead of repeatedly executing blocks of instructions
gets amortized.”
Christopher Batten, who created the high bandwidth memory system to support Krashinsky’s execution unit, said, “I
always wanted to do hardware - chip design. When I came to MIT, I thought we’d be doing chips right away. But it
took six years before we actually built a chip. That took about two years, but it was worthwhile because a lot of our
initial area and energy claims were validated by doing it.”
This was a small-scale project, Batten said. “Two students, less expensive, very hands on. We got to do everything. It
was a lot of fun.”
“One of the cool things about doing this is that I get to come to ISSCC,” he concluded. “It’s so different from the conferences I go to. There’s a whole lot more industry people here. It’s a whole different community.”
Spring 2007
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The body sensor processor devised by Sungdae Choi, an A-SSCC award winner, can be
used at home for monitoring and transmitting bio-signals to health care professionals. He envisions that with this device “even healthy people will be able to catch
symptoms of abnormal health conditions” and have them automatically forwarded for
follow-up.
“When I was very young, I was interested in making something work as I desired,” he
said. “So I decided in my mind to become a doctor, a kind of doctor. I wanted to contribute to human life. My dream came true. Now I have another dream, to make some
useful gadget for people and every person will use the gadget I made.”
Lanzerotti Honored by IEEE Women in Engineering
Society of New York
VLSI Designer Named Engineer of the Year 2006
D
r. Mary Yvonne Lanzerotti
received the Engineer of the
Year 2006 award from the
NY Section of the IEEE Women in
Engineering (WIE) Society at the
IEEE New York Section Annual Dinner Dance in New York City on February 10th. She received the award
“In recognition of her outstanding
technical and service contributions
to the engineering profession and
promotion of women in the science
and technology disciplines.”
Dr. Lanzerotti is a Research Staff
Member at the IBM T.J. Watson
Research Center in Yorktown
Heights, NY. She received an A.B.
degree from Harvard in 1989, an
M. Phil. Degree from the University of Cambridge in 1991, and the
M.S. and Ph.D degrees from Cornell in 1994 and 1997, respectively.
She joined IBM in 1996. She is
currently in the VLSI Design Department, where her research interests
include analysis of POWER6 timing-
critical paths and the design and
implementation of on-chip interconnections for the POWER4.
Dr.
Lanzerotti is a member of the IEEE
Spectrum Advisory Board and member of the IEEE Solid-State Circuits
Society, where she is the co-editor of
the society Newsletter, and has been
the driving force behind its current
makeover. She is also a member of
the IEEE Lasers and Electro-Optics
Society (LEOS), where she has been
an elected member of the Board of
Governors (2003-2005) and Executive Editor (2001-2006) and Associate
Editor (1995-2000) of the LEOS
Newsletter.
In addition to her technical work,
Dr. Lanzerotti has lectured on the
steps engineers and scientist can take
to improve their professional development at the NY Section of the IEEE
WIE. These steps been identified by
the American Physical Society (APS)
Committee on Careers and Professional Development and are given in
the first Professional Development
Resource Guide that list resources
identified as important for the professional development of today’s engineers and scientists. This guide is
posted on the APS website at
www.aps.org/careers/index.cfm. Dr.
Lanzerotti is also a member of the
APS Women Speakers List posted at
www.aps.org/programs/women/spe
akers/ and participates in National
Engineers Week, visiting local schools
with other IBM scientists attracting
female students to engineering, science, and information technology.
Congratulations New Senior Members
34 Elected in January and February
Khalid Abed
Lars Bengtsson
Paul Berndt
Lucien Breems
Michael Brooks
Arthur Cappon
Vivek De
Sher Fang
Roland Gesche
P Govindacharyulu
Mustafa Guvench
Nikos Haralabidis
64
Mississippi Section
Sweden Section
Seattle Section
Benelux Section
Buenaventura Section
Dallas Section
Oregon Section
Dallas Section
Germany Section
Hyderabad Section
Maine Section
Greece Section
IEEE SSCS NEWS
Ronald Hickling
Buenaventura Section
Joe Howell
Eastern Idaho Section
Cosmin Iorga
Buenaventura Section
Kannan Krishna
Oregon Section
J Marcos Laraia
Eastern Idaho Section
Ming-Kin Law
Toronto Section
See Lee
Dallas Section
Adrian Leuciuc
Baltimore Section
Wolf-Ekkehard Matzke Germany Section
Harry Mcintyre
Coastal Los Angeles Section
Makoto Nagata
Kansai Section
Robert Neidorff
New Hampshire Section
Takao Onoye
Gregory Pauls
Sameh Rehan
John Safran
Boon Eu Seow
David Standley
Simon Tam
Joseph Walsh
Kazuya Yamamoto
Kevin Zhang
Kansai Section
Pikes Peak Section
Egypt Section
Mid-Hudson Section
Malaysia Section
Buenaventura Section
Oakland-East Bay Section
Eastern Idaho Section
Kansai Section
Oregon Section
Spring 2007
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TOOLS:
How to Write Readable Reports and Winning
Proposals
Part 3: Save Readers and Yourself Precious Time
By Peter and Cheryl Reimold, www.allaboutcommunication.com
P
erhaps the most annoying
thing about reports is the way
they gobble up time. First,
writers spend hours sketching the
complex background of the project
and describing results in sufficient
detail to impress higher-ups with
the thoroughness of the work. (If
the facts aren’t impressive enough,
fancy wording must come to the
rescue, at further cost in writing
time.) Then readers groan as they
try in vain to find shortcuts through
the thicket of irrelevant or baffling
detail and convoluted language.
Nobody is happy, important information gets lost, and a lot of time
disappears into a black hole.
Some writers learn from such
mistakes and scratch out most of
the irrelevant and confusing things
they put into their draft before they
send it out. Now the writing takes
even longer for them, but at least
their readers are better off.
Isn’t there a way to avoid all the
waste of time from the start? Yes—
and it’s as simple as respecting
three commonsense laws:
1. Don’t make your readers read
any thing they don’t want to
know.
2. Don’t write down things you’ll
end up deleting.
3. Don’t make the reader read anything twice.
Reimolds’ Law #1: Don’t Make
Your Readers Read Anything
They Don’t Want To Know
No matter how much you’d like to
get upper-management readers to
appreciate the intricacies of your
work, they will only resent being
held up by technical details or puffy
language. So save them time by
including only significant information
and keeping the language simple.
Spring 2007
How do you achieve this? By
preparing an outline based on an
analysis of reader needs. The needs
analysis takes the form of an imaginary dialogue with each reader
group. Begin by noting the questions of the primary reader, then
those of other readers. Answer the
questions in list form and you have
an outline of the significant points.
Anything else you’re burning to
add doesn’t belong in the report.
Reimolds’ Law #2: Don’t Write
Down Things You’ll End Up Deleting
Many writers begin the drafting
process by expanding their data
tables into detailed results,
expanding those further in a discussion section, then adding some
detailed background as an introduction, and finally trying some
conclusions and a summary. At
that point, they may begin to spot
irrelevant details and start the
tedious cutting process.
Instead, begin the whole
process with the summary. This
answers the reader’s first question:
“What are you trying to tell me?”
(For instance: Our new teamwork
approach to the problem with
absenteeism has shown significantly better results than previous oneon-one confrontations.) Then
explain or back up that main message only as much as needed for
your readers. When did the absenteeism problem begin? How did
you try to solve it in the past? What
did you do differently with the
team approach? What do your
findings suggest? What obstacles
remain? What are the next steps for
you and the readers?
When your main message is in
place, you can judge easily which
details serve it and which detract
from it or add nothing important.
By contrast, when you start with
the details, you miss the yardstick
for measuring relevance, and overwriting is inevitable.
Reimolds’ Law #3: Don’t Make
the Reader Read Anything Twice
Readers don’t like having to reread
a sentence because it is unclear,
ambiguous, or deliberately constructed so as to require parsing
twice (that’s the drawback of
words like former, latter, and
respectively). Look at your style. Is
it more like A than B? Then it’s time
to work on clarity and simplicity!
A. From consideration of these facts,
the probability presents itself that
the unfavorable work environment on Project X, as opposed to
the more propitious circumstances surrounding the efforts on
Project Y, in no small way impeded the presence and effective
contributions of team members of
the former, leading inescapably to
the noticeable problem of absenteeism therein, versus the latter.
B. findings suggest that the poor
working conditions on Project X
contributed greatly to the problem of absenteeism on that project. Project Y, which had better
working conditions, did not
have this problem.
Cheryl and Peter Reimold have been
teaching communication skills to engineers, scientists, and businesspeople for
20 years. Their firm, PERC Communications (+1 914 725 1024, perccom@aol.com), offers businesses consulting and writing services as well as
customized in-house courses on writing, presentation skills, and on-thejob communication skills. Visit their
web site at www.allaboutcommunication.com.
IEEE SSCS NEWS
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CHAPTERS
New SSCS Chapters in Tainan and South Brazil
Seoul and Santa Clara Chapters Host Talks by S. Kang, M. Pedram, and M. Horowitz
W
ith the assistance of SSCS
Chapters Chair Jan Van
der Spiegel, Wilhelmus
Van Noije, a Professor in the Electronic Systems Engineering department at the Polytechnical School of
the University of Sao Paulo, spearheaded the formation of a new SSCS
Chapter in South Brazil.
Dr. Noije was one of 40 attendees at the Society’s Chapter Chair
Luncheon and Meeting in San
Francisco on 13 February 2007.
An SSCS Chapter in southern
Taiwan was founded by Prof.
Chua-Chin Wang of National Sun
Yat-Sen University in Kaohsiung.
His description of the circumstances that led to the formation of
the Society’s second Taiwanese
chapter, and his story of how he
gained local support for it, may be
found in this issue.
Seoul Chapter Hears S. Kang on
Bioelectronics and M. Pedram on
Charge-recycling MTCMOS
Chulwoo Kim, Korea University,
ckim@korea.ac.kr
IEEE/SSCS Seoul hosted two lectures by SSCS Distinguished Lecturers in 2006.
Prof. Steve Kang, University of
California, Santa Cruz presented an
interesting paper entitled, “Bioelectronics, Its Status and Prospectus” at
Korea University on 12 August 2006.
In this talk, the current status of
sitions in half while preserving the
wakeup delay and reducing the
ground bounce level in the target
circuit. At a chapter meeting after
his presentation, Prof. Pedram gave
several good tips to improve chapter activities such as DL seminars,
homepage management, organizing international conference, etc.
From left, Richard C. Jaeger, SSCS President, Jan Van der Spiegel, SSCS Chapters Chair and Wilhelmus Van Noije,
Chair of SSCS-South Brazil in conversation at the SSCS Chapter Luncheon.
biomimetic microelectronic systems, laboratory-on-a-chip (LoC),
and energy scavenging for
implantable devices were discussed
with development of CAD models
and simulation tools for biological
circuits, biomimetic systems, and
their hybrid structures. About 100
people attended the seminar. The
lecture was followed by a dinner
meeting to give chapter members a
chance to get together with the lecturer and to have extended conversations on selected topics.
Prof. Massoud Pedram, University of Southern California, presented
a talk entitled, "Charge-recycling
MTCMOS: Circuit Techniques and
Design Automation Algorithms” at
COEX, Seoul on 26 October 2006.
25 people attended the seminar. He
spoke about a charge recycling
MTCMOS technique that cuts the
energy consumption for mode tran-
SSCS-Seoul chapter members from left: Prof. Chulwoo
Kim, Prof. Suki Kim, Prof. Sung-Mo Kang, Prof. Sangsig
Kim, Prof. Cheol Jin Lee, and Prof. Jinyong Chung.
66
IEEE SSCS NEWS
Mark Horowitz Speaks in Santa
Clara on “Rethinking Analog”
Santa Clara Valley Chapter Host
10 Events in 2006
Dan Oprica, IEEE Santa Clara Valley Executive Committee Awards
Chair; IEEE SCV Solid State Circuits
Society Chapter Programs Chair,
opricad@ieee.org
On 27 March 2007, Dr. Mark
Horowitz of Stanford University
addressed the chapter on the topic
of Rethinking Analog: Digitally Driven Analog Design.
Abstract: As we continue to scale
CMOS technology, more chips integrate a small amount of mixed signal
circuitry on their large digital dies.
Since transistors are getting worse,
and the specs for the analog are getting tighter, all these blocks use
numerous cheap digital gates to
"improve" their analog performance.
This talk will discuss a new research
program we are starting at Stanford
University to try to rethink analog
design. The first step is to realize
that digital correction is here to stay,
From left: Seoul chapter Vice President Jeong-Taek Kong, Prof.
Jin-Ku Kang, Prof. Kwang Sub Yoon, Prof. Shin-Il Lim, Prof.
Massoud Pedram, Mr. Sung-Hoon Bae, Prof. Hong-June Park,
Mr. Young-Wook Yu and Prof. Chulwoo Kim at COEX, Seoul on
26 October 2006.
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and is pretty cheap. So the first
research question is can we build
mostly “digital” analog subsystems,
and are there power/design time
advantages in this approach. Since
there will be some analog circuitry
that remains, the second research
question is to try to create a design
system that makes using mixed-signal
blocks more like using digital macros
-- each cell comes with a validation
script, and a set electrical rules checkers that ensure the design assumptions are actively checked every time
it is used. Our goal in this section is to
create robust mixed signal cells that
can be used in many different
designs. More importantly this tool
should provide management feed-
back on when redesign of an analog
cell is really needed, and prevent simple chip errors from reappearing
when a new designer redesigns an
existing block.
A profile of Dr. Horowitz may be
found in the SSCS Newsletter of
November 2005: www.ieee.org/ portal/pages/sscs/05Nov/Horowitz.html
Santa Clara Solid-State Circuits
Chapter concluded another successful
year in 2006: We held ten well-attended technical meetings. As Programs
Chair, I always tried to bring topics of
great interest to our audience and to
invite the best speakers we can get.
We have been quite successful.
We held our officers election for
2007. I was able to convince Luiz
Franca-Neto, a very good professional and a friend of mine to volunteer
for our chapter as an officer. He
already serves in the MTT chapter. I
also had success as Santa Clara Valley IEEE Executive Committee
Awards Chair. One of my proposals
for IEEE Region 6 Awards was fulfilled: National Semiconductor
received the R6 Company of the Year
2006 Award for Community Service.
I organized a nice Ceremony and
granted the Award to the Company
designated VP of Engineering.
I speak for all our IEEE members in thanking you for supporting our Chapter.
Best wishes for 2007!
A Chapter Is Born in Southern Taiwan
Prof. Chua-Chin Wang, National Sun Yat-Set University, Kaohsiung, Taiwan, ccwang@hinet
Southern Taiwan a Growing Hub
of Semiconductor Activity
Although Taiwan has renown as
one of the power houses globally
in the semiconductor industry, the
major spotlight has focused on
northern Taiwan. The key factor is
the success of Science Park in
Hsinchu (eweb.sipa.gov.tw/en/
index.jsp); many heavy weight
semiconductor foundries are located in the Science Park or nearby.
Due to the magnetic effect of such
a success, a similar phenomenon
is found in the Taiwan academic
circle. The focal point of semiconductor research, including IC
design and process technology,
has long been dominated by
those universities located close to
the Science Park, e.g., NTU
(National Taiwan University),
NCTU (National Chiao Tung University), and NTHU (National
Tsing Hua University).
However, ever since the National
Si-Soft Project, propelled by the Taiwan authority, kicked off in 2002
and Southern Taiwan Science Park
(STSP, which is located in Tainan
County, www.stsipa.gov.tw/web/)
Spring 2007
was officially founded in 2003,
many semiconductor companies
have either established branch
offices or foundries in STSP. In
the mean time, many potential
researchers and engineers have
scattered over the soil of southern
Taiwan, either becoming faculty of
universities nearby, e.g., National
Cheng Kung University (NCKU),
National Sun Yat-Sen University
(NSYSU), and National Chung
Cheng University (CCU), or engineers in the branches of semiconductor companies.
Therefore, it seemed to be the
right moment to set up a solidstate circuit forum to enhance the
influence of IEEE as well as SSCS
in this area.
How the Tainan Chapter Became
Reality
In late 2006, when I discussed the
possibility of founding a new Chapter of SSCS with one of my colleagues, Prof. Tzyy-Sheng Horng, he
encouraged me to get such a great
idea going. Besides, he advised me
to inform graduates of our institute
to join SSCS such that SSCS would
become a significant forum in the
area of southern Taiwan.
Then I contacted Prof. ShenIuan Liu, who is the acting SSC
Chapter of IEEE Taipei Section,
and Prof. Chorng-Huang Wang,
who has long been involved with
SSCS, to ask for their advice
regarding the ups and downs of a
new Chapter in southern Taiwan.
Both of them gave me every warm
and positive response, and even
suggested that I attend 2006 ASSCC in Hangzhou, China, during
Nov. 13~15, 2006, to meet committee members of SSCS. However,
due to my tight schedule at that
moment, I did not make the trip.
Nevertheless, I also consulted several professors in different universities who were members of SSCS
and involved in different SSCSendorsed conferences to learn
what they thought about the
necessity of such new Chapter. To
my surprise, almost everyone was
looking forward to seeing such a
forum. These professors include:
Prof. Ming-Hwa Shew and Prof.
Ya-Hsin Hsueh of National Yunlin
University of Science & Technolo-
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gy, Prof. Po-Ming Lee of Southern
Taiwan University of Technology,
Prof. Chingwei Yeh and Prof.
Shuenn-Yuh Lee of National
Chung-Cheng University, Prof. BinDa Brian Liu and Prof. Kuen-Jong
Lee of National Cheng Kung University.
Besides searching for support
from university campuses, I also
turned my eyes to local semiconductor industrial links, particularly IC design houses. Dr. YihLong Tseng and Mr. Hon-Yuan
Leo of Himax Display, Inc.
(www.himaxdisplay.com)
expressed their interest in supporting SSCS activities, as did Mr. TianHau Chen of Himax Technologies,
Inc. (www.himax.com.tw). Himax
Display, Inc. and Himax Technologies, Inc., founded and owned by
Chi Mei Optoelectronics (CMO,
www.cmo.com.tw), are among the
top five TFT-LCD manufacturers in
the world. The former is an IC
design house focused on LCOS
and related products, while the latter is one of the major suppliers of
LCD driver IC world wide. Besides
these IC design houses, BeeDar
Technology Inc. and Etrend Electronics, Inc., both located in STSP,
are possible partners that we can
approach.
Defiining the Chapter’s Mission
Many research-oriented universities or colleges are located around
STSP:
•National Cheng Kung University
•National Sun Yat-Sen University
•National Chung-Cheng University
•National Yunlin University of Science & Technology
•National Kaohsiung University
•National Kaohsiung First University of Science & Technology
•Southern Taiwan University of
Technology
•Kun Shan University
Lots of faculty in the EE or CS
departments in these universities or
colleges have thrown great effort
68
IEEE SSCS NEWS
Geographic locations of STSP and
nearby universities in Southern Taiwan
into the advanced research topic of
IC circuit and system designs.
Moreover, STSP itself is a well
developed industrial community.
Notably, a total of over 6,000 engineers/managers with MS or Ph. D.
degrees are spread around almost
100 high-tech companies. Quite a
great portion of the elite RD task
force could be SSC-related or at
least semiconductor-related. The
following companies are considered to be highly correlated to
SSCS areas.
•TSMC
•Applied Materials Taiwan, Ltd.
•BeeDar Technology Inc.
•MPI Probe Inc. ST Branch
•Taiwan Shintex Technology Co.,
Ltd.
•Chip MOS Technologies Inc.
Tainan Plant
•LAM Research Co., Ltd.
•Etrend Electronics, Inc.
•Acute Technology Corp.
A forum steered by IEEE SSCS
would be considered a good platform for the companies inside
STSP and the universities to know
each other, especially because
more IC-design houses are expected to emerge due to the promotion
and encouragement of the government-driving National Si-Soft Project. I’d like to see SSCS play a sig-
nificant role in this area.
But first we need to enhance the
visibility of SSCS such that its potential contribution may be appreciated.
As the founder of this new Chapter,
I hope to proceed with several initiatives to introduce people to each
other in the area of SSCS:
1. Invite distinguished researchers/
lectures to southern Taiwan
2. Establish an email list of members
3. Set up a website for the Chapter
4. Co-sponsor
IEEE-sponsored
conferences/symposiums
5. Hold workshops for members
Hopefully, the number of SSCS
members can be increased significantly in the end of the term of the
first Chapter Chair. In the long
run, I certainly hope the Chapter
becomes a great organization in
southern Taiwan.
About the Author
Chua-Chin
Wang
(M’90, SM’07) was
born in Taiwan in
1962. He received the
B.S. degree in Electrical Engineering from
National Taiwan University in 1984, and the M.S. and
Ph.D. degrees in Electrical Engineering from State University of
New York in Stony Brook in 1988
and 1992, respectively. In 1992, he
joined the Department of Electrical
Engineering, National Sun Yat-Sen
University, Kaohsiung, Taiwan. He
has been a professor since 1998 in
the same department. His recent
research interests include low
power and high speed logic circuit
design, VLSI design, neural networks, and interfacing I/O circuits.
He served as member of the
technical committees of MST,
Nano-Giga, VLSI Systems & Applications of IEEE CAS Society since
2006. In 2007, he was invited to
serve as an Associate Editor of
VLSI Design. He is also the General Chair of 2007 VLSI/CAD Symp.
in Taiwan.
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CONFERENCES
Classic Books Remain Best Sellers at ISSCC 2007
Books on Music and Mathematics and Advanced Excel are Sleepers
Katherine Olstein, SSCS Administrator, k.olstein@ieee.org
CMOS: Circuit Design,
Layout, and Simulation, 2nd Edition by R.
Jacob Baker (Wiley-IEEE
Press, 2004) ISBN: 978-0471-70055-5, USD 99.95
www.wiley.com
Understanding DeltaSigma Data Converters
by Richard Schreier and
Gabor C. Temes, (WileyIEEE Press, 2004) ISBN:
978-0-471-46585-0, USD
99.95.
Four books popular at recent
ISSCC meetings were best sellers at
ISSCC 2007:
CMOS: Circuit Design, Layout,
and Simulation, 2nd Edition by
R. Jacob Baker was a conference
best seller for the third year in a
row. According to comments by
the publisher, “this comprehensive
presentation of CMOS integrated
circuit design navigates readers
through the process of implementing a chip from the physical
definition to the design and simulation of the finished product.”
(www.ieee.org/portal/pages/sscs/
04Oct/Books-SSCS.html)
Understanding Delta-Sigma Data
Converters by Richard Schreier
and Gabor C. Temes, also from
Wiley, has been a top ISSCC seller
since 2005. In a review in the SSCS
Newsletter of September 2005, Ian
Galton said, “It provides a ‘one-stop
shop’ for engineers who want a
comprehensive introduction to the
Spring 2007
Analog Design
Essentials, The Springer
International Series in
Engineering and Computer Science, Vol. 859
by Willy Sansen
(Springer, 2nd printing,
2006) ISBN: 978-0-38725746-4, USD 99.00
www.springer.com
field of delta-sigma data converters.
The authors are top researchers in
the field with extensive industrial
and academic experience in deltasigma data converter design. They
are also excellent teachers, with
vast experience lecturing the fine
points of delta-sigma data converter
design to both university students
and practicing engineers. As a
result, the book is well polished,
easy to understand, and provides a
solid and broad introduction to the
field.” www.ieee.org/portal/pages/
sscs/05Sept/Schreier_and_Temes.
html
Analog Design Essentials by
Willy Sansen, which was Springer’s
top seller at ISSCC 2006, “contains
all topics of importance to the analog designer which are essential to
obtain sufficient insights to do a
thorough job,” according to the
publisher’s website. “The book
starts with elementary stages in
building up operational amplifiers.
The synthesis of opamps is covered
The Design of CMOS
Radio-Frequency
Integrated Circuits,
Second Edition
by Thomas H. Lee
(Cambridge, 2003)
(ISBN-13: 9780521835398,
USD 80
www.cambridge.org
in great detail. Many examples are
included, operating at low supply
voltages. Chapters on noise, distortion, filters, ADC/DACs and oscillators follow,” all based on the
author’s extensive experience in
teaching. Slides are included on a
CD-ROM as PDF files.
The Design of CMOS Radio-Frequency Integrated Circuits 2nd
Edition, by Thomas H. Lee, was
one of the two top sellers for
Cambridge University Press at
ISSCC 2006 and sold comparably at
the conference in 2007.
Further commentary on the Lee
and Sansen books may be found in
the SSCS newsletter review of best
sellers at ISSCC 2006: www.ieee.org/
portal/pages/sscs/06Mar/Best_Sellers_at_ISSCC.html
Conference “Sleepers”
Danielle Christensen, Engineering
Editor at Oxford University Press,
had a hunch that Music and Mathematics: From Pythagoras to Frac-
IEEE SSCS NEWS
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tals, by John Fauvel, Raymond
Flood, and Robin Wilson, might be
of interest at ISSCC but did not
imagine it would turn out to be
Oxford’s best seller. www.oup.com
Music and Mathematics: From
Pythagoras to Fractals, by John
Fauvel, Raymond Flood, and
Robin Wilson (Oxford, 2006)
ISBN-13: 9780199298938, USD
32.50.
Advanced Excel for Scientific
Data Analysis by Robert de Levie
(Oxford, 2004) ISBN-13:
9780195152753, USD 59.50.
Equally surprising was Oxford’s
second best seller: Advanced
Excel for Scientific Data Analysis
by Robert de Levie. It is about
“how you hot-wire Excel to do
unusual things,” Ms. Christensen
said. De Levie, a chemist, is the
author of more than 160 papers in
analytical chemistry and electrochemistry and several books,
including an early Spreadsheet
Workbook for Quantitative Chemical Analysis (McGraw-Hill, 1992)
and a textbook on the Principles of
Quantitative Chemical Analysis
(McGraw-Hill 1997), according to
the Oxford website. He taught analytical chemistry and electrochemistry for 34 years at Georgetown
70
IEEE SSCS NEWS
University and is now an emeritus
professor associated with Bowdoin
College in Brunswick, Maine
The runaway best seller for Cambridge University Press was
Electromagnetics for HighSpeed Analog and Digital Communication Circuits, by Ali M.
Niknejad, University of California,
Berkeley, ISBN-13: 9780521853507,
USD 85.00, available March 2007.
This news came as a surprise to
the author. “Most people would
easily admit to disliking E&M or
have good horror stories about an
E&M professor in college who
drove them crazy,” he said in an
email interview, “but it's becoming so important in the design of
high frequency/high data rate circuits and the IC community is
becoming aware of it.”
According to Cambridge, the
book “begins with a review of the
basics (the origin of resistance,
capacitance, and inductance) and
progresses to more advanced topics such as passive device design
and layout, resonant circuits,
impedance matching, high-speed
switching circuits, and parasitic
coupling and isolation techniques.
Using examples and applications in
RF and microwave systems, the
author describes transmission lines,
transformers, and distributed circuits and reviews state-of-the-art
developments in Si based broadband analog, RF, microwave, and
mm-wave circuits.”
An article by Prof. Niknejad is
featured in this issue of the SSCS
newsletter.
Other top sellers at ISSCC 2007
were:
Cambridge University Press
Wireless Communications, by
Andrea, Goldsmith (2005) ISBN-13:
9780521837163, £40.00.
Elsevier (www.elsevier.com)
VLSI Test Principles and Architectures, by Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale,
CA, USA, Cheng-Wen Wu, National
Tsing Hua University, Hsinchu, Taiwan, Xiaoqing Wen, Kyushu Institute of Technology, Fukuoka, Japan
(2006) ISBN-13: 978-0-12-370597-6;
USD 59.95. A reviewer on the Elsevier website said, “This is the most
recent book covering all aspects of
digital systems testing. It is a “must
read” for anyone focused on learning modern test issues, test research,
and test practices.” The book sold
well because testing represents
“more than 50% of the development
cycle these days,” said Charles
Glaser, Elsevier’s ISSCC representative. Elsevier has more testing books
coming, he said.
Elsevier’s second and third top
conference sellers were:
Demystifying Switched Capacitor Circuits, by Mingliang Liu
(2006) ISBN-13: 978-0-7506-7907-7
USD 59.95.
Networks on Chips by Giovanni
De Micheli, Ecole Polytechnique
Federale de Lausanne, Switzerland,
edited by Luca Benini, University
of Bologna, Italy (2006) ISBN-13:
978-0-12-370521-1, USD 59.95.
McGraw-Hill (www.mhprofessional.com)
Charge Pump Circuit Design by
Feng Pan and Tapan Samaddar
(2006) ISBN: 007147045X /
9780071470452, USD 99.95 sold best.
This book is “The first-ever guide to
designing and implementing charge
pumps for today’s low-cost, highperformance mobile devices,” said
Nicole J. LeBlanc, McGraw-Hill’s
marketing manager.
Phase Locked Loops: Design,
Simulation and Applications5 by
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CONFERENCES
Roland E. Best (2003) ISBN
0071412018 USD 79.95) “remains the
yardstick by which all other circuit
references are measured,” Ms.
LeBlanc said. Roland E. Best is a
“world-renowned authority with
experience enough to know the
questions you would ask.” McGrawHill will publish the 6th edition of this
classic reference in September 2007.
Embedded Core Design with
FPGAs by Zainalabedin Navabi
(2006) ISBN 0071474811, USD
99.95.
Prentice Hall
(www.prenhall.com)
The Art of Analog Layout, by
Alan Hastings (2005, ISBN-13:
780131464100, USD 131.00).
Digital Integrated Circuits, by
Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic
(2003, ISBN-13: 9780130909961,
USD 135.00).
Solid State Electronic Devices,
by Ben Streetman, University of
Texas at Austin and Sanjay
Banerjee, University of Texas at
Austin (2006, ISBN-13:
9780131497269, USD $135.00).
Springer
Data Converters by Franco Maloberti (2007) ISBN: 978-0-387-324852A, 99.00).
RF System Design of Transceivers for Wireless Communications by Qizheng Gu (1st ed., 2005.
Corr. 2nd printing, 2006, ISBN: 9780-387-24161-6 USD 89.95).
Wiley-IEEE Press
Physics
of
Semiconductor
Devices, 3rd Edition by Simon M.
Sze, Kwok K. Ng (2006) ISBN: 9780-471-14323-9, US $125.00.
Digital and Analog Designers Spar at ISSCC Evening
Panel Session
Alice Wang, Senior Member of Technical Staff - Texas Instruments, aliwang@ti.com
“Digital RF: Fundamentally a New
Technology or Just Marketing
Hype?” was the title of Tuesday
night’s evening session at ISSCC
2007. This panel promised to highlight the classic battle of digital vs.
analog, and I always like a good
fight to end a long day of sessions.
With moderator Tom Lee giving
a rousing “Welcome Geeks” introduction to the packed room, I
knew the discussion would be
lively. As the crowd settled down,
it was clear the analog and RF
designers would put up a good
fight against the invasion of digital.
In their opening remarks, the
well-known panelists quickly differed on the first question posed
“What is Digital RF?”
Rudolf Koch from Infineon
pointed out that up to 20 radios on
a chip was imminent, and the
complexity of design may be alleviated by digital techniques. Professor Asad Abidi and Intel’s Krish-
Multiple radios on a chip is imminent from Infineon, said
ISSCC panelist Rudof Koch.
Spring 2007
namurthy Soumyanath (Souyma)
agreed that a true digital RF solution should mean Software
Defined Radios or Cognitive
Radios – that uses DSP techniques
to make a highly flexible universal
radio.
Dave Welland from Silicon Labs
was unimpressed with today’s digital radio that took the low frequency parts and turned them digital and would only be awestruck
if the LNA or VCO that are tradi-
According to Professor Asad Abidi and Intel’s Krishnamurthy
Soumyanath (Souyma), a true digital RF solution should
mean Software Defined Radios or Cognitive Radios.
IEEE SSCS NEWS
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tionally difficult to design went
digital.
Satoshi Tanaka from Hitachi
mulled over the difficulty of designing RF circuits in Deep Submicron
technologies with their digital
noise, low voltage levels and complexity. Very quickly the opening
statements degraded into “The
World versus Texas Instruments”
(who coined the term “Digital
Radio Processor (DRP)”). Bogdan
Staszewski from TI proposed that
the definition of Digital RF meant
the ability to scale RF from node-tonode like digital and stood behind
the fact that the “marketing hype”
can’t refute that DRP is already at
volume production in 90nm.
The floor was opened to the
audience whose questions ranged
from how to educate students both
in digital and analog to wondering
how many on-chip inductors are
really needed for those 20+ radios
(Abidi=3, Souyma=1). The conversation also turned to the business
side – how to fill fabs, how to
keep your high margins for analog
vs. low margins on digital, and
time-to-market for new RF standards. It was clear that everyone in
the audience had a pretty strong
opinion because proponents and
denigrators alike stepped to the
mike to wax on about “digital RF”
in their lives.
At the end of the night no one
wanted the fight to end as moderator Tom Lee closed out the session. With no real conclusion, the
answer is not “zero” or “one”
(excuse the pun) and the debate
will rage on about digital RF, reali-
ty or marketing hype?
The panelists’ topics were:
• Asad Abidi (UCLA) “SDR: Once
Objecf of Derision, Real Today
with Digital RF”
• Rudolf Koch (Infineon, Munich,
Germany) “Digital High Frequency or High Frequency Marketing?”
• Krishnamurthy Soumyanath (Intel,
Hillsboro, Oregon) “Digital Techniques will Imporve Multi Comm
Integrated Circuits”
• R. Bogdan Satszewski (TI, Dallas, TX) “Winning Recipe: Digital
Turns RF and RF Turns Digital”
• Satoshi Tanaka (Hitachi, Tokyo,
Japan) “Fusion of standard RF
Analog and Digital are Essential
for Future RF LSI”
• David Welland (Silicon Laboratories, Austin, TX) “Some Assembly Required”
VLSI Circuits Symposium Celebrates 20th
Anniversary in June
Sreedhar Natarajan, sn@emergingmemory.com
T
he International Symposium
on VLSI Circuits will be held
on June 14-16th, 2007 at the
Rihga Royal Hotel, Kyoto, Japan.
The Symposium consists of three
days of technical presentations and
informal evening rump sessions on
VLSI circuit design. Following the
tradition of the past several years,
the Circuit Symposium will follow
the Technology Symposium at the
same location.
This year will mark the 20th
anniversary of the first Circuit Symposium. The Symposium has
established itself as a major international forum for presenting and
exchanging important ideas and
new developments in VLSI circuit
design. The scope of the Symposium covers all aspects of VLSI circuits, including signal processing,
digital, processors, FPGAs, analog
& mixed signal RF circuits, memory circuits, and has been expanded
to include new concepts in VLSI
design, such as MEMS, novel mem-
72
IEEE SSCS NEWS
From left, Kazuo Yano, Circuits Symposium Program Chair, Stephen Kosonocky,
Circuits Symposium Co-Chair, Katsu Nakamura , Circuits Symposium Program
Co-Chair, and Sreedhar Natarajan, Publicity Chair, met at ISSCC 2007 to plan
the June Symposium on VLSI Circuits.
ory, quantum computing. The circuit innovations to be presented at
this Symposium will form the foundation for future developments
and advances in the semiconductor
industry. Contributions to the Symposium come from both industry
and academia around the world.
This year the technical program
committee reviewed 342 submissions to the conference and chose
103 papers for presentation and
publication at the Symposium.
Paper selections were based on
technical quality and impact to the
design community, with representation from industrial and academic institutions from around the
world. Considering the changing
technological demands, we hope
you will attend and participate in
discussions at the technical sessions, rump sessions and short
courses, featuring new and innova-
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tive discussions of leading-edge
concepts at this conference.
About the Venue
The Rihga Royal Hotel is located
west of Kyoto, the old capital of
Japan, which attracts many visitors
from all over the world. The JR
Kyoto station was totally renovated
and modernized in 1997, so now
you can enjoy the combination of a
modern station building along with
the traditional Kyoto cityscape. For
further information, please visit the
Web site of the Kyoto Convention
Bureau (which also provides a look
at the history and culture of Kyoto)
at web.kyoto-inet.or.jp/org/hellokcb/index.html.
•
•
Technical Highlights
Papers to be presented at the Symposium will cover latest and interesting circuit design concepts for
digital, memory, analog, wireless,
and wireline applications. The
highlights include:
• A number of multicore and configurable SoC implementations
including an HDTV real time
encoding SoC, a multi-purpose
configurable SoC with nine CPUs
and two Matrix processors, an
LDPC decoder design, and a heterogeneous multicore, dynamically-reconfigurable with two
CPUs and two Dynamic Reconfigurable Processors. (Session 2)
• High frequency design takes several forms in the High Performance Processing session. This
session has a wide variety of
papers from a 65nm 5.1Ghz
router chip, a FIR filter with onchip 1Ghz resonant clock in fully
ASIC flow, and synthesizable
designs to reach 4Ghz. (session 5)
• Applications such as software
defined radios, ultra-wideband
radio and hard-disk drives
require high sampling rate
ADCs. Multiple papers discuss
time interleaving and a flash
design to realize gigahertz sampling rate ADCs targeted
towards digital-TV and satellite
receivers, as well as UWB radios
Spring 2007
•
•
•
•
followed by a high speed DAC
for backplane communication.
Most designs are at state-of-theart 90nm technologies that pose
the additional challenge of
designing at lower supply voltage. (Session 7)
The state of the art microprocessors and SOCs (System On a
Chip) require the K-bit order of
electrical-fuse-memory-array on
the die as well as the high-density of SRAM cells fabricated by
deep submicron CMOS technologies. To overcome these
challenges, interesting circuit
techniques will be reported in
the 2007 Symposium. (Session 8)
IBM will demonstrate a >10X
density compact eFUSE programmable array configured as a
4Kb one-time programmable
ROM. The 1T1R cell size is only
6.2μm2 using 65nm SOI CMOS.
On the SRAM side, a novel failure model of multi-bit-error
caused by a neutron induced
single event upset will be reported and relaxed ECC guidelines
will be given by Infineon Technologies. (Session 8)
“MM-Wave Building Blocks”
focusing on millimeter wave
CMOS RFIC designs for highspeed communication and radar
applications. (Session 17)
The Dynamic and Non-Volatile
Memory session will host the
most advanced state of the art
developments in architecture
and circuit techniques in DDR3
DRAM’s, MLC NAND Flash,
Phase Change Memory, and
Emerging Memory Technology
Devices such as the CBRAM.
(Session 18)
Various innovative clock generation schemes like PLLs, DLL and
time-to-digital converters are
covered in multiple sessions.
The SRAM session discusses various embedded SRAM cache
arrays to support low-voltage
and high-speed operation, at
and beyond 65nm technology.
Industry is shifting focus to 8T
SRAM designs instead of con-
ventional 6T SRAMs to achieve
low voltage functionality. The
SRAM session discusses various
dual port 8T SRAMs and 65nm
SOI SRAMs. (Session 24)
Invited Speakers
Invited papers presented by academic and industry leaders are
always the pinnacle of the Symposium, focusing on both technical
and business implications of technological changes.
This year’s symposium includes
four invited talks by distinguished
speakers. Their titles, listed in
alphabetical order by speaker
name, are:
• “Future of microprocessors
enabling game consoles,” by
Jeff Brown (IBM)
• “Future vision of mobile phone
technology as the driver of this
industry,” by Koji Chiba (NTT
Docomo)
• “Fundamental Limits of Power
Consumption in Analog Circuits,” by Prof. Hae-Seung Lee
(MIT)
• “Recent rapid progress in organic, printable, foldable electronics” by Prof. Takao Someya (University of Tokyo).
Tadahiro Kuroda, Symposium Chair
(left), with plenary speaker HaeSeung (Harry) Lee.
Rump Sessions
Evening rump sessions are organized around controversial topics
and experts are invited to present
their divergent views. All aspects
of the controversy are explored,
and a spirited discussion ensues;
active audience participation is
encouraged! This year the rump
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session topics for the Circuits Symposium are:
(1) CMOS scaling: Where will
economics set the “end of
the line”?
Continued scaling is largely
being driven by the fact that
scaling is still reducing the cost
of a transistor, a trend that is
quickly changing as tooling
and fabrication challenges
multiply. Where will economics set the “end of the line”?
What players or markets will
determine this “end of the line”
scaling node?
(2) Analog scaling and SoC integration
In this special evening session
four speakers with very different backgrounds will discuss
the impact of technology scaling on analog and RF design.
How can we still design efficient analog circuits in nanometer CMOS and what are the
design challenges in this scaling? What technology should
we choose for RF: BiMOS or
CMOS and SiP or SoC?
Special Feature: Joint Rump Session (Technology and Circuits)
A special feature of the Symposium
is the one-day overlap in the
schedules for the International
Symposium on VLSI Technology
and the Symposium on VLSI Circuits. This is an excellent opportunity to meet with members of the
opposite discipline to share experiences, issues, and ideas for future
improvements. In addition, there is
also a joint rump session organized
by members of both the Circuits
and Technology committees. This
year’s topic is “Is compact modeling measuring up to the challenge
of the DFM era?”
VLSI Circuits Short Course
Vivek De of Intel and Masayuki
Mizuno of NEC have organized an
excellent one-day Short Course,
“Design for Variability in Logic,
Memory and Microprocessors” on
Wednesday, 13 June, 2007. The
Short Course includes talks by
experts in the field, covering
design techniques for managing
variability.
This is a condensed one-day
course intended to give attendees
an excellent overview of the topic
as well as to provide the latest
developments in the area. This is
a rare opportunity to hear timely
presentations describing work in a
technical area given by recognized leading practitioners and
researchers who teach others to
do what they do best.
VLSI Symposium Workshop
Hiroki Ishikuro and Foster Dai have
organized an excellent workshop on
“Advanced Topics on Multi-Standard
Wireless Transceiver RFIC Designs.“
This workshop will be held on 15
June, 2007. This tutorial includes talks
by experts in the field starting with a
discussion on multi-com radios for
multi-standard coexistence continuing
to focus on multi-band RF front-end
and multi-band frequency synthesis
RFIC designs. The second half of the
workshop presents advanced topics
including software defined radio, digital-video-broadcast receivers, and
MIMO wireless transceiver SoC’s.
Further Information
For questions about hotel reservations contact:
Rihga Royal Hotel Kyoto
Horikawa-Shiokoji, Shimogyo-ku,
Kyoto 600-8237, Japan
Tel: +81-75-341-1121
Fax: +81-75-341-3073
For registration and other information, visit the VLSI Symposia home
page at: www.vlsisymposium.org
or see more contact information in
the SSCS Events Calendar.
Corrections
I
n the article entitled “The Second A-SSCC Considers
Challenges for the e-Life” in the Winter ’07 issue, the
caption under the picture of the A-SSCC student
design contest winners mistakenly read as if their left to
right position indicated their rank. The A-SSCC Student
Design contest is not ranked. All three were winners with
no ranking.
SSCS Members at ISSCC Receive Replacement DVD
Archive Disks
The SSC Digital Archive pair of DVDs distributed to SSCS
members at the ISSCC was mislabeled: The disk misla-
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IEEE SSCS NEWS
beled “Update 2006” actually contains all the files from
1955 to 2000. And the disk mislabeled “Foundations”
contains all the most recent files from 2001 through 2006.
Replacement disks were mailed to postal addresses
provided at the time of ISSCC registration. The new
disks are date-stamped with a “March 2007 Issue” to differentiate them from the erroneous disks and can be
stored in the original jewel case.
If you are an SSCS member who attended the ISSCC
and have not received your replacement disks, please
contact sscs@ieee.org and provide your member number and postal address.
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Persico and Streit to Speak at RFIC Symposium in
Honolulu, 3-5 June 2007
David, Ngo, RFIC 2007 Publicity Chair
M
ark your calendar and
make reservations for the
2007 IEEE RFIC Symposium (www.RFIC2007.org ) to be
held in Honolulu, Hawaii from
June 3rd through June 5th. RFIC is
sponsored by the IEEE Solid-State
Circuits, Microwave Theory and
Techniques (MTT), and Electronic
Devices Societies.
Once again, this year’s RFIC
Symposium continues its tradition
as the premier conference showcasing the latest advancements and
innovations in RF integrated circuits, wireless sub-systems, broadband communications, and circuit
technology for emerging wireless
applications. The symposium continues to provide a forum for some
of the most innovative advancements from both industry and academia.
Plenary Session to Focus on Wireless and Future RF Applications
A Plenary Session will be held on
Sunday evening, with keynote
addresses given by two renowned
industry leaders. The first speaker,
Charles Persico, Senior Vice President of Engineering at Qualcomm
Inc. will present a talk entitled
“Wireless Convergence - Your
Spring 2007
Phone is Not Just a Phone Anymore.” The second speaker,
Dwight C. Streit, Ph.D., Vice President, Electronics Technology,
Northrop Grumman Space Technology, will discuss “Technology
Directions for Future RF Applications.” Three student paper
awards will also be presented in
the Plenary Session. The highly
anticipated RFIC Reception will
follow immediately after the Plenary Session, providing a relaxing
time for all to mingle with old
friends and catch up on the latest
news.
Program to Offer a Vast Array of
RFIC Technology
The vitality of the RFIC community appears stronger than ever, as
an all-time record number of man-
uscripts were submitted to this
year’s conference. The Technical
Program Committee worked diligently to provide a superior venue
for this vast array of RFIC technology. The symposium will feature
15 workshops and tutorials on
Sunday, June 3rd. In addition, 30
oral sessions, an Interactive Forum,
and two panel sessions will be
given on Monday and Tuesday,
covering nearly all facets of RFIC
technology.
When you think of the word
Hawaii, what first comes to mind?
Sunshine, beautiful beaches,
snorkeling, and a great place to
visit are immediate thoughts
many of us would have. In addition to all of this, add one more
thought: three days of some of
the most remarkable RFIC technology to be found anywhere in
the world.
On behalf of the RFIC Technical
Program Committee, we look forward to seeing you at the 2007
RFIC Symposium. Mahalo.
Luciano Boglione,
RFIC General Chair
Tina Quach & Jenshan Lin,
RFIC Technical Program
Chairs
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CEDA Currents
News from the IEEE Council on Electronic Design Automation
CEDA Distinguished Speaker
Videos Available
IEEE CEDA announces online
videos of talks by distinguished
speakers, available at www.ieeeceda.org/lectures.html.
Recent
additions include a talk by Frances
A. Houle of the IBM Almaden
Research Center on professional
ethics, one by Janusz Rajski on
embedded deterministic test, and
Zhenhai Zhu’s “A Fast Stochastic
Integral Equation Solver for Modeling the Rough Surface Effects.”
IEEE Fellows Elected in 2006 for
CEDA-Related Activities
These individuals have been elected as IEEE Fellows for contributions in the following CEDA-related areas.
• Luca Benini, University of
Bologna, Bologna, Italy: Design
technologies for low-power
design of integrated circuits and
systems
• Bhargab B. Bhattacharya, Indian
Statistical Institute, Calcutta: Testing and design of digital ICs
• Abhijit Chatterjee, Georgia Institute of Technology, Atlanta: Testing of analog and mixed-signal
circuits
• Anirudh Devgan, Magma Design
Automation, Austin: Electrical
analysis, and simulation of ICs
• Kenneth S. Kundert, Designer’s
Guide Consulting, Los Altos:
Simulation and modeling of analog RF and mixed-signal circuits
• Sandip Kundu, University of
Massachusetts, Amherst: Design
of IC test methods
• Gaetano Palumbo, University of
Catania, Catania, Italy: Analysis
and design of high-performance
analog and digital circuits
76
IEEE SSCS NEWS
• Ruchir Puri, IBM Thomas J. Watson Research Center, Yorktown
Heights: Automated logical and
physical design of electronic circuits
• Jose Schutt-Aine, University of
Illinois, Urbana: Modeling and
simulation of distributed circuits
with applications to signal
integrity
This is not a complete list of the
2007 IEEE Fellows. We apologize in
advance for any omissions. Please
see www.ieee.org/web/aboutus/fellows/new-fellows.html for the complete list.
IEEE TAB Approves Council
Cosponsorship of the IEEE Phil
Kaufman Award
The IEEE Technical Activities Board
(TAB) approved CEDA sponsorship
of the Phil Kaufman Award for Distinguished Contributions to Electronic Design Automation jointly
with the EDA Consortium. This
award honors an individual who
has significantly impacted the field
of electronic design through contributions in electronic design
automation (EDA).
CEDA is also cosponsoring a
Donald O. Pederson Award for
the best paper in IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems
and the William J. McCalla Award
for the best paper at ICCAD, and
provides nominations and input
for the IEEE Piore Award. Together, these awards represent excellent mechanisms to recognize
contributions from our community. Please send your suggestions
and nominations to CEDA administrator Barbara Wehner at
b.wehner@ieee.org.
Upcoming Events
Design, Automation and Test in
Europe Conference (DATE)
16-20 April 2007
Nice, France
www.date-conference.com
16th International Workshop
on Logic & Synthesis (IWLS)
30 May - 1 June 2007
San Diego, Calif.
www.iwls.org
Paper submissions deadline: 3
March 2007
5th ACM-IEEE International
Conference on Formal Methods
and Models for Codesign (MEMOCODE)
30 May - 1 June 2007
Nice, France
memocode.irisa.fr
7th International Forum on
Application-Specific
MultiProcessor SoC (MPSoC)
25-29 June 2007
tima.imag.fr/mpsoc
Hyogo, Japan
15th VLSI-SOC
15-17 October 2007
Atlanta, GA, USA
www.vlsisoc2007.gatech.edu
For more information regarding
sponsorship of conferences and
meetings, contact Richard Smith,
dsmith@topher.net.
CEDA Currents is a publication of
the IEEE Council on Electronic Design
Automation. Please send contributions to Kartikeya Mayaram
(karti@eecs.oregonstate.edu) or Preeti
Ranjan Panda (panda@cse.iitd.
ac.in).
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IEEE SSCS will Focus on Strategic Planning in 2007
AdCom Highlights
At its biannual meeting on 11 February, 2007 in San Francisco, the Sold-State Circuits Society AdCom voted
to launch a process to set goals and a strategic directions for the Society and to participate in a newly organized Council on Engineering Management.
SSCS AdCom members who met in San Francisco on 11 Feb. 2007 were: Top row, from left: Jan Sevenhans, Domine Leeanarts,
Paul Hurst, Bram Nauta, Kevin Kornegay. Third row, from left: David Johns, Mehmet Soyuer, Rakesh Kumar, C.K. Wang, Un-Ku
Moon, Larry Starr, Sreedhar Natarajan, Tadahiro Kuroda, Anne O’Neill, K. Nagaraj. Second row, from left, Bruce Hecht, Harry
Lee, Bill Bidermann, C.K. Ken Yang, Takayasu Sakurai, Anantha Chandrakasan, John Corocoran, Terri Fiez, Akira Matsuzawa.
Front row, from left: Katherine Olstein, Wanda Gass, Ali Hajimiri, Tom Lee, Dick Jaeger, Steve Lewis, Lew Terman, Willy Sansen.
Ad Hoc Committee Formed for Goal Setting
With the Society 10 years old in 2007, Society President Dick Jaeger charged the AdCom to articulate
Society goals. Some Society activities have steadily
grown in the last decade, while others have shown
wide swings.
The Journal page count, the numbers of Chapters
and the number of technically co-sponsored meetings
have all shown steady growth. The Journal page count
has increased from 2,000 to 3,100 pages, while Chapters have grown from none to 59 and technically cosponsored meetings have grown from 5 to 11.
In contrast to the steady growth of these activities,
Society financial reserves, which reflect general financial markets dipped from their previous 1999 high of
$3.25 million to $1.1 million in 2002, but have
returned to an even higher level of $4 million.
Membership, on the other hand, peaked in 2001 at
14,500 members, but has declined to 11,000 in 2006,
the approximate size of the Society when it was
formed in 1997. This drop in membership is believed
to be a measure of the success of IEEEXplore in supplying technical articles through employer subscriptions rather than individual memberships. Engineers
interested in the field of Solid-State Circuits continue
to read the Journal of Solid-State Circuits in record
Spring 2007
numbers, which can be verified by download counts
of pdf files in Xplore. But readers no longer have to
join SSCS to read the Journal online if their employer subscribes, saving out-of-pocket money while
benefiting from the support of industry and academic subscriptions.
These trends deserve closer examination. At
Jaeger’s suggestion, the AdCom agreed to launch
an AdHoc Committee to focus on goals and strategic directions for the Society. Appointed chair of
the new committee, Rakesh Kumar (also SSCS
Treasurer) said that two areas of AdCom concern
that the committee may address are maintaining
the quality of the Society’s sponsored conferences
and publications and devising “out of the box”
ways to increase membership. The AdHoc committee will be comprised of a representative from
each of the four standing AdCom committees
(Meetings, Publications, Membership, Education)
plus two or three at-large members. The group will
prepare an initial report with recommendations for
the AdCom in August.
What’s new at the IEEE Board?
IEEE 2007 President-Elect Lew Terman gave a short
report on the main focus items and new directions
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which he sees at the IEEE Board of Directors level for
2007. He noted that the IEEE Board meetings would
be held during the week of February 12th, and there
would be more information available after the meetings. The main items from IEEE Board meetings are
reported to IEEE members through the Institute. His
report follows:
Past-President Mike Lightner is continuing his focus
in two areas he initiated in 2007. The first is IEEE
membership. He started investigation of an alternative
membership model with different levels of benefits
and cost. Surveys have been made of current members (all grades), former members, and non-members.
Given a choice, there is no single benefit everyone
wants, and over 100 benefits that at least some members want. The current focus is on evaluating the
alternative models and their financial impact.
Past-President Lightner is also heading the effort to
establish a formal presence in China. While the IET
(formerly the IEE in the UK) was able to register itself
as a not-for-profit organization, the China government
is now holding up such registrations indefinitely. A
possible alternative is to register as a for-profit organization until the not-for-profit status becomes available. This does not appear to have any downside, but
is being looked at closely.
2007 President Leah Jamieson is focusing on three
areas: membership, strategic planning, and more efficient board meetings and board series. Membership
includes growth of the overall Institute membership,
the increasing percentage of non-US members, retention of student members after graduation, and Society
membership. Membership was the subject of a facilitated strategic planning meeting attended by around
40 volunteer leaders from across the Institute during
the Board Series week, focusing on the value of members, their role in IEEE, and long term goals.
Two half-day sessions have been set aside at the
Board Series for strategic planning, one on membership, noted above, and the other on long term planning for the Institute. The latter was preceded by two
facilitated sessions, and the sessions are expected to
continue at the two remaining 2007 Board meetings.
The goal is to develop a clear view of where IEEE
should be in 10-15 years, how it should get there, and
what are the more focused shorter term actions to get
there. It is expected that the plan will be reviewed
yearly. President Jamieson’s focus on strategic planning is very welcome, as it has not been receiving sufficient attention.
Efficient IEEE Board Meetings are very important,
since they are the three times a year the IEEE Board
gets together for face-to-face meetings and interaction. Under the new approach, the more important
items are moved to the beginning of the meeting to
ensure that they are addressed early. Current sched-
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IEEE SSCS NEWS
uling has the Board and ExCom meeting on Wednesday and Sunday, requiring Board members to stay the
intervening days, a major inconvenience. The pros
and cons of scheduling the Board meetings for Saturday and Sunday are being investigated.
Other items:
• A new New Initiatives process that allows submission and rapid approval/funding of new initiatives
around the year, and adds a new category of Seed
Grants at a much lower level of funding to allow
quick exploration of high risk pilot programs.
• A proposal to restructure the Infrastructure Oversight Committee with an increased membership,
three year terms, and the requirement for member
financial expertise. The committee will be charged
with delving deeply into the IEEE Indirect Infrastructure Charge (overhead), the rise of which has
been a concern to IEEE operating units.
• A new method of funding the Indirect Infrastructure
Charge, based on taking a fraction of the IEEE
packaged products net (primarily from Xplore/IEL).
This is expected to be revenue neutral for 2008.
• The new Business Management System (BMS) is on
track for roll-out for the 2008 renewal cycle. This is
a complete revision of the business software used
for membership related activities, sales, and Institute information.
• A new method of funding for the Foundation,
Awards Board, and History Center, which involves
budgeting up to 1.5% of the average reserves over
the previous three years. This is revenue neutral for
2008. Including the 3% for New Initiatives, this
gives IEEE a “spending rule” of 4.5% of the Institute
reserves.
• Expert Now is off to an excellent start and will be
available to members this year. The Education Activities Board is doing a strong world-wide effort on
accreditation. EAB also has a strong focus on attracting pre-college students to science, engineering, and
IT, and is working with universities to develop curricula leading to degrees in the Services area.
• Financially, 2007 was the fourth good year in a row
for the IEEE, with the addition of about US$30M to
the reserves bringing them to just over US$200M.
Reserves have more than doubled since the low
point of US$91M at the end of 2002. The need for
a long range plan on the growth and/or wise use of
reserves is apparent.
SSCS Joins the new Engineering Management
Council
Rakesh Kumar reported on the IEEE Board’s approval
of the change of the IEEE Engineering Management
Society to the Engineering Management Council. The
major difference between IEEE Societies and Councils is
that Societies have members, while technical Councils
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SSCS NEWS
do not have members, but are governed by representatives from the IEEE societies which are members of the
Council; thus a Council is made up of the member societies. IEEE technical Councils generally deal with disciplines which are broadly spread across a number of
Societies. In this case, the EMS governance felt that
engineering management is a skill that transcends specific technical disciplines, and Council status would put
them in a more favorable position to impact the full
spectrum of IEEE societies and members.
In recent surveys, IEEE members have put management skill high on their list of important career
goals, along with computer skills, communication,
and circuits and systems skills, as Robert A. Lutz, former President and Chairman of Chrysler Corporation,
pointed out in “Engineers……. Write it up.”
The Engineering Management Council will improve
the opportunity to help members expand beyond the
technical area through training and awareness of leadership, management, and communication issues. SSCS
joins 10 other IEEE Societies in forming the new Council.
The other Societies are: Aerospace and Electronic Systems (AES), Circuits and Systems (CAS), Communications
Society (ComS), Computer Society (CS), Electron Devices
(EDS), Industrial Electronics (IES), Lasers and ElectroOptics (LEOS), Reliability (Rel), Signal Processing (SPS),
and the Systems, Man, and Cybernetics Society (SMC).
The Journal and Conferences
The Journal and Conferences continue to be the Society’s core vehicles to disseminate the latest in IC circuits, and they are the primary focus of SSCS AdCom.
Bernhard Boser, the Publications Committee Chair,
reported on the excellent time to publication and management of Nagaraj, the editor-in-chief of the JSSC,
one of the fastest turnarounds in IEEE. AdCom voted
that the JSSC plan for 3,100 published pages for 2008.
Bram Nauta of University of Twente, Netherlands will
be the next JSSC Editor beginning next summer.
Because SSCS sponsored conferences have an
important goal to provide new and unique results, a
manuscript should not be submitted to more than one
Society President Dick Jaeger (at left) attended the VLSI Design
Symposium in Bangalore, India in January 2007 with Sreedhar
Natarajan (center), liaison between ISSCC and the conference,
and Navakant Bhat (at right), the founder of the Bangalore
chapter. They are standing in front of the ISSCC 50th Anniversary Musuem display at VLSI, which also traveled to the ASSCC in November 2006 meeting in Hangzhou, China.
at a time. Bill Bidermann will draft a pre-publication
policy for SSCS AdCom consideration, that will
require authors to state they are not engaging in multiple submissions. When approved by the AdCom at
its meeting next September, the policy will be applicable to all the Society’s conferences.
The Meetings Committee, Chaired by Anantha
Chandrkasan, reviewed metrics for 7 of SSCS 11 technically co-sponsored conferences and endorsed three
upcoming.
• BCTM 2007, the Bipolar/BiCMOS Circuits and
Technology Meeting which in 2008 will be collocated with the Compound Semiconductor IC Symposium (CSICS) in 2008
• DATE 2008, the Design Automation and Test in
Europe
• Hot Chips 2007 – a Symposium on high-performance chips sponsored by the IEEE Computer Society and its Technical Committee on Microprocessors and Microcomputers.
For more news of SSCS conferences check out the
online database:
www.ieee.org/portal/pages/sscs/conf_list/conf_200
7.html
Call for Nominees for SSCS Administrative
Committee Election
Petition Deadline is 1 August
E
ach year SSCS elects five members to the governance of the Society on the Administrative Committee (AdCom). The Bylaws of the Society guarantee a choice for members in the election by requiring
that the Nominations Committee prepare a slate of a
minimum of 8 candidates for the 5 positions. SSCS members interested in running or nominating others must
their recommendations along with their reasons for sug-
Spring 2007
gesting a candidate to the Chair of the Nominations
Committee, Stephen H. Lewis, (lewis@ece.ucdavis.edu),
by the end of February of the year of the election. Student
members are not eligible to run or vote. The Nominations
Committee begins its work in spring and will announce
the slate of candidates in the summer SSCS News.
The election is in the fall. The five nominees receiving the highest number of votes of the Society mem-
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bership will be elected.
There is also a petition process for interested parties
who are not endorsed by the Nominations Committee.
Bylaws for petition candidates were revised in 2005
and supersede the previous Society rules.
AdCom Member Duties and Responsibilities
Nominees by Petition
After the announcement in the summer issue of the SSCS
News, of the slate of candidates from the Nominations
Committee, there is an opportunity to add petition candidates to the ballot. The statement of intent to begin the
petition process must arrive at the Society Executive office
(a.oneill@ieee.org) by August 1. It must be submitted
with the knowledge and agreement of the nominee. The
petition candidate’s eligibility will be verified. The petition
process itself can be completely managed online under
the administration of the IEEE Corporate Office. Any society voting member who wishes to sign such petition may
do so electronically. A link to the petition site will be provided on the SSCS website, sscs.org. Once a petitioner is
posted on the site, he or she will remain up to receive
endorsement signatures for 30 days.
The number of signatures required is defined by IEEE
Bylaw I-308.16, as 2% of SSCS voting members at the time
the petition process begins. This is expected to be approximately 140 signatures. Such petitions must be submitted
with the knowledge and agreement of the nominee.
SSCS Bylaws are currently being revised to harmonize with these new IEEE petition procedures. IEEE
Elected AdCom members are expected to attend the
two administrative meetings each year. Much of the
Committee’s work is carried on by email, telephone,
and fax throughout the year. The AdCom oversees the
operations of chapters, publications and conferences
including the Journal of Solid-State Circuits, the International Solid-State Circuits Conference, the Custom
Integrated Circuits Conference, the VLSI Circuits Symposium, and the Asia Solid-State Circuits Conference. In
addition, the Society cosponsors or technically cosponsors a number of other conferences and meetings.
The AdCom has responsibility for overseeing these
and for other potential future technical activities within the Society's field of interest.
Terms of Office
• The term of office is three years beginning 1 January 2008.
• AdCom members may be reelected to a second
consecutive term.
Members who miss two consecutive AdCom meetings shall be dropped from membership in the absence
of extenuating circumstances.
IEEE Partners with Knowlegde Master, Inc. to Offer
Microelectronics Courses in Mandarin Chinese
P
ISCATAWAY, NJ, 18 December 2006 - The IEEE
has partnered with Knowledge Master, Inc. to
offer IEEE members courses specific to microelectronics, semiconductors, and integrated circuit design in
Mandarin Chinese. This partnership fulfills two important objectives of the IEEE: to serve the community of
practitioners in the area of microelectronics – one of the
most important, highly expanding, and technically exciting fields of electrical engineering – as well as to serve
a segment of IEEE’s practitioner population that resides
in China.
Founded in 2004, Knowledge Master Microelectronics Institute, Inc. is a provider of online career development courses for Chinese or Chinese American
working professionals through its website at KnowledgeOnDemand.com.
Primarily focusing on the information services and
internet technologies industry, Knowledge Master,
Inc., a California-based e-learning company, has
developed a unique, on-demand content delivery system built around Macromedia Breeze and Flash technologies. The system lets students hear the professor’s
voice as it walks them through interactive slides, as if
they were sitting in the same classroom. It also lets
students control their own pace of learning with a full
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IEEE SSCS NEWS
set of controls to pause, rewind, repeat, skip and
search through their lectures.
Knowledge Master’s curriculum features 26 courses
totaling more than 25,000 animated slides in English
with 350+ hours of voice-over narration in Mandarin
Chinese. The courses are developed by Dr. WenChing Chang, an internationally-renowned professor
of microelectronics, specializing in RFIC, CMOS, analog IC, optoelectronics and wireless communications.
Dr. Chang has taught more than 30,000 college students and working professionals over the past 20
years in Taiwan.
“I am highly honored to be affiliated with IEEE, and
am excited about the opportunity to offer our full library
of online courses to Chinese-speaking IEEE members to
assist them in their professional career development,”
stated Dr. Wen-Ching Chang, CEO. “We hope our rich
content, combined with our easy to use interface will
give IEEE members the freedom and power to learn at
their own pace, on their own schedule.”
“As a working professional in the IC design industry for 15 years and then having learned with Dr.
Chang for six months, I started to realize what the
core concepts and analysis skills of microelectronics
were all about,” said Mr. Hong-Yuan Yang, a senior
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SSCS NEWS
analog IC design engineer from Holtek Corporation in
Taiwan, who gave this testimony to the public during
the 2006 Taiwan Microelectronics Conference.
The IEEE’s Educational Partner Program, exclusively for IEEE members, offers on-line degree programs,
certifications and courses at up to a 10 percent discount. The partners are a carefully selected number
of universities and corporations reviewed and
approved by highly qualified IEEE volunteers to
ensure members receive the most effective learning
resources. The goal of the IEEE education program is
to ensure the growth of skill and knowledge among
the technical profession and to foster individual commitment to continuing education among the engineering and scientific community, the general public,
and the more than 365,000 IEEE members in approximately 150 countries.
To access courses, have free preview offered by
Knowledge Master Microelectronics Institute, or to
review other partners, visit www.ieee.org/partners.
Call for Nominations: SSCS Predoctoral Fellowships
2007 – 2008
Due Date is 1 May, 2007
N
ominations for the Society’s
2 pages is appropriate), plus a list
Predoctoral Fellowships in
of any publications authored or
solid-state circuits are due on
co-authored. A copy of each pub1 May, 2007 for the academic year
lication is desirable. Work that
2007-2008. The one-year awards will
must be done to complete the
provide $15,000 for tuition, up to
graduate program of study should
$8000 in addition for fees, and a grant
be explained -- why it is imporof $2,000 to the department in which
tant, and what is novel about its
the recipient is registered. A maxiapproach -- as well as the impormum of two awards will be made.
tance of SSCS predoctoral fellowLast year’s predoctoral fellows
ship support toward completion
were Chinmaya Mishra of Texas
of the doctoral degree.
A&M University and Peter H. R. President Richard C. Jaeger presented
Letters of Recommendation Popplewell of Carleton University, SSCS Predoctoral Fellowship certificates At least two letters of recommento Mr. Popplewell (left) and Mr. Mishra dation are required; one should be
Ottawa Canada.
Fellowship awards are available during the plenary session Awards Pro- from the principal advisor. These
world-wide. Applicants must have gram at ISSCC 2007 in San Francisco.
letters should address academic
completed at least one year of graduate study, be in a record, accomplishments and promise, graduate study
Ph.D. program in the area of solid-state circuits, and research program, and need.
be a member of IEEE. The award will be made on the
Deadline: 1 May 2007
basis of academic record and promise, dissertation
Please email your application materials to:
research program, and need.
sscsfellowship@ieee.org.
Applications should be in electronic format and
Electronic file submission is preferred, but if paper
must include the following items:
files are all you can provide, either fax them to +1
A Short (one-page) Biography - including IEEE 732-981-3401 or mail to:
membership number.
Academic Records - including a copy of all releIEEE-SSCS Executive Office
vant undergraduate and graduate transcripts.
Predoctoral Fellowship
Graduate Study Plans - including a summary of
445 Hoes Lane
what has been completed and what is planned (about
Piscataway, NJ 08854
Spring 2007
IEEE SSCS NEWS
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Presubmission Professional Editing Services for IEEE
Authors
Dawn Melley, Director, Editorial Services, IEEE Periodicals
I
n conjunction with a TAB Periodicals subcommittee,
chaired by Jacek Zurada, and in response to the interest you expressed at the April 2006 Panel of Editors
meeting in Montreal, IEEE Publishing Operations has partnered with one of our established vendors, SPi Publisher
Services, to offer presubmission professional editing services to IEEE authors, beginning immediately.
SPi provides scientific, technical and medical publishers with a high quality, end-to-end outsourcing solution. Their multi-country delivery platform harnesses
the talent of more than 3,500 content and BPO specialists. Located in the US, Europe and the Philippines,
these specialists copyedit and typeset more than 1 million pages per year for over 600 journals. SPi has provided content tagging and editing services to IEEE Publishing Operations since 2002.
An author who would like assistance with English
grammar and usage prior to submitting their manuscript
to an IEEE publication for review or during the review
process can now go directly to www.prof-
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IEEE SSCS NEWS
editing.com/ieee/ to submit a manuscript for copy editing. The SPi copy editors will edit for grammar, usage,
organization, and clarity, querying potentially substantive revisions as necessary. An author can use the service, at their own expense, as often as desired. Cost estimates are available immediately on line. Edited manuscripts will generally be returned to the author within
two weeks of submission.
Please help us to publicize this service by adding the
above information to your Information for Authors document as well as to your manuscript submission site, if
applicable. We will publish the information in the Tools
for Authors section of the IEEE website.
If you would like additional information about this
new service, please feel free to contact me directly.
Dawn Melley
Director, Editorial Services, IEEE Periodicals
445 Hoes Lane, Piscataway, NJ 08855
+1 732 562 3902
d.melley@ieee.org
Spring 2007
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Proven
POWERFUL
IEEE Member
Digital Library
The information you need to succeed can
be at your fingertips when you subscribe
to the IEEE Member Digital Library.
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Over a million full-text documents
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Access to the top-cited publications you
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Power up. Learn more at:
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SSCS EVENTS CALENDAR
Also posted on www.sscs.org/meetings
SSCS SPONSORED MEETINGS
2007 Symposium on VLSI Circuits
www.vlsisymposium.org
14–16 June 2007
Kyoto, Japan
Contact: Phyllis Mahoney,
vlsi@vlsisymposium.org
or Business Center for Academic Societies,
Japan,
vlsisymp@bcasj.or.jp
2007 Custom Integrated Circuits
Conference
http://www.ieee-cicc.org/
16–19 September 2007
San Jose, CA, USA
Paper deadline: 9 April 2007
Contact: Ms. Melissa Widerkehr
cicc@bis.com
2007 A-SSCC Asia Solid-State Circuits
Conference
www.a-sscc.org/
12–14 November 2007
Jeju Island, Korea
Paper deadline: 11 June 2007
Contact: : kyung@ee.kaist.ac.kr
2007 ISSCC International Solid-State
Circuits Conference
www.isscc.org
3– 7 February 2008
San Francisco, CA, USA
Paper deadline: 17 September 2007
Contact: Courtesy Associates,
ISSCC@courtesyassoc.com
SSCS PROVIDES TECHNICAL
CO-SPONSORSHIP
2007 Design, Automation and Test in
Europe
www.date-conference.com/conference/next.htm
16–20 April, 2007
Acropolis, Nice, France
Contact: sue.menzies@ec.u-net.com
2007 International Symposium on VLSI
Technology, Systems and Applications
(VLSI-TSA)
vlsidat.itri.org.tw
25 Apr - 27 Apr 2007
Hsinchu, Taiwan
Contact: Ms. Stacey C.P. Hsieh
stacey@itri.org.tw
2007 International Symposium on VLSI
Design, Automation and Test (VLSI-DAT)
vlsidat.itri.org.tw
25 Apr - 27 Apr 2007
Hsinchu, Taiwan
Contact: Elodie J.F. Ho
elodieho@itri.org.tw
2007 Radio Frequency Integrated
Circuits Symposium
www.rfic2007.org
3–8 June 2007
Honolulu, Hawaii
Contact: Dr. Luciano Boglione
l.boglione@ieee.org
2007 IEEE Integrated Circuit Ultra-Wide
Band
ICUWB
www.icuwb2007.org
30 Sep - 02 Oct 2007
Singapore
Paper Deadline: 18 March 2007
Contact: Michael Y.W. Chia,
chiamichael@i2r.a-star.edu.sg
2007 IEEE Bipolar/BiCMOS Circuits and
Technology Meeting - BCTM
www.ieee-bctm.org
30 Sep - 02 Oct 2007
Boston Marriott Long Wharf, Boston, MA
Contact: Ms. Janice Jopke
ccs@mn.rr.com
2007 IEEE Compound Semiconductor
Integrated Circuit Symposium (CSICS)
(Formerly GaAs IC Symposium)
2007 Design Automation Conference
www.dac.com
4–8 June 2007
San Diego, CA, USA
Contact: Kevin Lepine, Conference Manager
kevin@mpassociates.com
www.csics.org
14 Oct – 17 Oct 2007
Portland, OR
Paper Deadline: 7 May 2007
Contact: William Peatman
wpeatman@anadigics.com
Hot Chips
www.hotchips.org
11 Sep - 13 Sep 2007
Palo Alto, CA, USA
Paper Deadline: 25 March 2007
Contact: John Sell, info2007@hotchips.org
2007 IEEE/ACM International Conference
on Computer-Aided Design (ICCAD)
www.iccad.com/future.html
04 Nov - 08 Nov 2007
DoubleTree Hotel, San Jose, CA
Paper Deadline: 11 April 2007
Contact: Ms. Kathy Embler
kathy@mpassociates.com
SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State Circuits
Society of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th
Floor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member of
the Solid-State Circuits Society. This newsletter is printed in the U.S.A. Application to mail Periodicals
postage rates is pending at New York, NY and at additional mailing offices.
Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane,
Piscataway, NJ 08854. ©2007 IEEE. Permission to copy without fee all or part of any material without a
copyright notice is granted provided that the copies are not made or distributed for direct commercial
advantage and the title of publication and its date appear on each copy. To copy material with a copyright notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Manager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.
445 Hoes Lane
Piscataway, NJ 08854
ESSCIRC/ESSDERC 2007 - 37th European Solid
State Circuits/Device Research Conferences
www.essscirc.org
11 Sep - 13 Sep 2007
Munich, Germany
Contact: Mr. Philip Teichmann
teichmann@tum.de
To maintain all your IEEE and SSCS
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To make sure you receive an email alert, keep
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