Cadence® Parasitic Simulation User Guide
Product Version 4.4.6
April 2002
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Cadence Parasitic Simulation User Guide
Contents
Preface ............................................................................................................................ 6
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typographic and Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1
Diva Flow: Simulating Analog Circuits with Parasitics. . . . . . . . . 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Adding Component Description Format (CDF) Simulation Information . . . . . . . . . . . 10
Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Extracting Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Creating ConcICe Views from Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Comparing Schematic and Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Building an analog_extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Creating and Using a Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Backannotating Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
Diva Flow: Simulating Mixed-Signal Circuits with Parasitics
30
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Estimating Delays (Pre-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting Up for Pre-Layout Delay Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating a Design with Pre-Layout Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculating Delays (Post-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preparing for Post-Layout Mixed-Signal Parasitic Simulation . . . . . . . . . . . . . . . . . . .
Creating mixed_extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
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32
40
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48
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Modifying the Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting the Mixed-Signal Simulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating a Design (Post-Layout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
59
61
62
3
Diva Flow: Working Through an Extended Design Example 67
Simulating with Schematic Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Configuring and Partitioning the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Modifying the Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Choosing an Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Generating a Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Plotting Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Alternate Waveform Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Saving the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Simulating with Analog Parasitics and Estimated Digital Delays . . . . . . . . . . . . . . . . . . . 84
Extracting Analog Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Setting Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Estimating Digital Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Simulating with Analog and Digital Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Cell Library Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Creating a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Building a Mixed Extracted View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Whole Design Approach to Mixed-Signal Parasitic Simulation . . . . . . . . . . . . . . . . . 123
Comparing Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4
Assura Flow: Simulating Analog Circuits with Parasitics
. . . 128
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Preparing Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Preparing Technology Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
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Creating Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating Extracted Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparing Views using LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Building an av_extracted View using RCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(Optional) Building an av_analog_extracted View using MSPS . . . . . . . . . . . . . . . .
Creating and Using a Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Probing Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backannotating Parasitic Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
131
131
135
138
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144
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149
A
LVS Form Field Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Preface
This manual describes how you can use Cadence® tools to investigate the effect of parasitics
on your circuits. The guidance here is designed for users who are already familiar with circuit
design, simulation, and layout.
The information is divided into four chapters. Chapter’s 1-3 are based on the Diva physical
verification flow and Chapter 4 on the Assura™ flow.
Chapter 1, “Diva Flow: Simulating Analog Circuits with Parasitics” describes the flow and
tools for analog circuits. If your design contains only analog circuits, and you use the Diva
physical verification tool to extract parasitics, use the information in Chapter 1.
Chapter 2, “Diva Flow: Simulating Mixed-Signal Circuits with Parasitics,” describes the flow
used for digital or mixed-signal designs. Taking digital elements into account leads to a flow
that includes using the Affirma™ timing analyzer. If your design is digital or mixed-signal, you
can skip Chapter 1 and go directly to Chapter 2.
Chapter 3, “Diva Flow: Working Through an Extended Design Example” is a tutorial that
guides you through a series of examples illustrating the information in Chapter’s 1 and 2.
Chapter 4, “Assura Flow: Simulating Analog Circuits with Parasitics” describes the flow and
tools for analog circuits. If your design contains only analog circuits, and you use the Assura
physical verification tool to extract parasitics, use the information in Chapter 4.
This preface discusses the following:
■
Related Documents on page 6
■
Typographic and Syntax Conventions on page 7
Related Documents
Running a simulation with parasitics requires knowledge of several Cadence tools, which are
described in the following documents.
■
Affirma Analog Circuit Design Environment User Guide
■
Component Description Format User Guide
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Preface
■
ConcICe Help
■
Assura Diva Verification Reference
■
Cadence Hierarchy Editor User Guide
■
Affirma Pearl Timing Analyzer User Guide
■
SDF Annotator User Guide
■
Technology File and Display Resource File User Guide
■
Assura Physical Verification User Guide
■
Assura Physical Verification Developer Guide
Typographic and Syntax Conventions
Special typographical conventions emphasize or distinguish certain kinds of text in this
document.
Code examples are displayed in Courier font.
; This is an example of Courier font.
Within the text, variables and filenames are in Courier italic. This is an example of
the Courier italic font.
Within the text, keywords are set in Courier font, like this: keyword.
If a statement is too long to fit on one line, the remainder of the statement is indented on the
next line. For example
corSetMeasExpression("bandwidth" "bandwidth(v('/out' ?result 'ac) 3
'low')")
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1
Diva Flow: Simulating Analog Circuits
with Parasitics
This chapter describes how you can use Cadence® tools to investigate the effect of parasitics
on analog circuits. By accounting for the effect of parasitics, you can improve the accuracy of
your circuit simulations. If your design includes digital or mixed-signal circuits, skip this
chapter and go to Chapter 2, “Diva Flow: Simulating Mixed-Signal Circuits with Parasitics.”
Click a topic below for more information.
■
“Overview” on page 8
■
“Preparing Cell Libraries” on page 10
■
“Creating Designs” on page 13
■
“Creating Extracted Views” on page 14
■
“Creating and Using a Configuration” on page 21
■
“Simulating the Design” on page 26
■
“Probing Parasitic Values” on page 27
Overview
Simulating an analog circuit with parasitics requires these steps.
1. Preparing cell libraries
2. Creating an analog_extracted view of your design
In this step, the tool calculates parasitics from information in the layout view of your
circuit.
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The following flow diagram illustrates the substeps in creating an analog_extracted view
using the Assura™ Diva® physical verification tool. The substeps for the Assura RC
network reducer are shown with dotted lines because they are optional.
Diva Physical Verification
Rules File
layout View
Extractor
extracted View
Assura RC network reducer
concICe View
LVS
map files
Build_Analog
analog_extracted
View
3. Creating a configuration for your design
4. Simulating the design with parasitics included
After a successful simulation, you can select terminals and device pins on the schematic and
use plot commands to display the results in a waveform window. The resulting waveforms can
be used with all Analog Artist design system calculation and analysis tools.
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Preparing Cell Libraries
Before you can follow the flow outlined in this chapter, you need to provide the following views
and component description format (CDF) information for analog primitives and parasitic cells.
Analog primitives must have
Parasitic cells (such as presistors and
pcapacitors) must have
symbol cellview
symbol cellview
layout cellview or extraction rules that the
extractor will recognize
auLvs cellview for analog primitives
Model matching the simulator you use
CDF simulation information for auLvs
auLvs cellview that provides parameter
values used by LVS
CDF component parameters for resistance
(r) and capacitance (c)
The analogLib library contains examples of analog primitives and parasitic cells that you
can copy to create your cell library.
Preparing Technology Files
To prepare a library for parasitic extraction,
1. Describe the technology layers.
For details about the technology layers, refer to the Technology File and Display
Resource File User Guide.
2. Add or modify the verification rules used by the Diva processes DRC, Extract, and LVS.
Refer to the Assura Diva Verification Reference for details about creating verification
and extraction rules.
Adding Component Description Format (CDF) Simulation Information
Refer to the Component Description Format User Guide for more details about the steps
in this section.
To netlist primitives correctly, you must verify the auLvs CDF parameters for each primitive.
1. Start the Cadence software by typing icfb & at the command prompt.
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2. In the command interpreter window (CIW), choose Tools – CDF – Edit.
The Edit Component CDF form appears.
3. In the upper portion of the form, choose Cell for CDF Selection and Base for CDF
Type.
You must edit the base-level CDF for changes to be effective.
4. Fill in the Library Name and Cell Name fields, or click the Browse button to select the
cell.
The Edit Component CDF form expands to display additional information.
5. In the Simulator Information area of the expanded Edit Component CDF form, click on
Edit.
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The Edit Simulation Information form appears, displaying existing CDF information about
auLvs netlisting.
6. Select auLvs in the Choose Simulator drop-down list box.
7. Ensure that the netlistProcedure field specifies ansLvsCompPrim. This is the
internal auLvs procedure for netlisting primitives.
8. In the instParameters field, specify the parameters you want in the netlist.
A component can have several parameters, such as temperature coefficients, that do not
apply to LVS netlist comparison. Your LVS comparison rules tell LVS how to handle such
parameters.
If model is included in the instParameters field, auLvs uses the value of the model
property in the instance instead of the value of componentName in the netlist.
9. In the componentName field, type the component name you want included in the
netlist.
This optional field allows you to use a common name in the netlist for different cells. For
example, 3-terminal cellviews (with programmable bulk nodes) and 4-terminal cellviews
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(with a bulk node as a pin) that have distinct names like nmos3 and nmos4 can be
netlisted with the same component name like nmos.
The component names pcapacitor, presistor, pinductor, and pdiode are used
for parasitic devices. All these devices are removed from the netlist before layout versus
schematic (LVS) runs but are used in simulation and backannotation. For presistors and
pinductors, the nets are shorted together.
10. In the termOrder field, type the names of the device terminals as they appear in the
symbol cellview.
This is the order in which the terminals are netlisted.
11. If termOrder uses programmable nodes, type the names of the terminals in
deviceTerminals.
The input is the same as for termOrder, but programmable nodes are replaced by
names in this field.
12. For existing designs that use older databases, use propMapping to change the name
of an instance parameter.
This allows instParameter names that use lowercase letters to be mapped to LVS rules
that are defined in uppercase letters.
Note: Do not use this feature for new designs.
13. In the Permute Rule field, specify the LVS permute rule used to define equivalent pins.
14. Click OK on the Edit Simulation Information form and Apply on the Edit Component CDF
form to accept your changes.
Note: The CDF parseAsNumber property distinguishes strings from numbers in numeric
parameters. String parameters without the parseAsNumber property set to true are
netlisted as strings beginning and ending with “\”. This feature is not compatible with releases
before 4.4.2.
Creating Designs
If you intend to extract parasitic components from the layout view and run a simulation with
parasitics, use the following guidelines to avoid problems as you plan your design.
■
Devices with the componentName parameter set to pcapacitor, presistor, pinductor,
and pdiode are automatically removed from the netlist. Do not use these names for your
components.
■
Nets are shorted together for LVS on presistors and pinductors.
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■
Do not use the LVS permuteDevice parameter to match groups of components in a
series because that makes it impossible to determine which device is which for waveform
probing.
Creating Extracted Views
You use the Diva physical verification tool to extract parasitics from the layout view of a block.
Then you use LVS to compare the extracted view to the schematic view to identify areas that
are not consistent between the views. After a successful LVS run, you create an
analog_extracted view of the design.
Extracting Parasitics
To extract parasitics from the layout view of a cell or block,
1. Be sure that the environment variable CDS_Netlisting_Mode is set to Analog.
2. Choose Verify – Extract from the layout cellview of the cell.
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The Extractor form appears.
3. Choose flat for Extract Method.
You need to use flat extraction because parasitic capacitance values can vary between
different instances of the same cell. Each cell, therefore, must be extracted.
4. (Optional) Choose Join Nets With Same Name.
This ensures that nets with the same name are joined automatically.
5. To select the types of parasitics you want extracted, click Set Switches.
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The Set Switches form appears. The parasitics displayed vary, depending on the
extraction rules file defined for your design. In some cases, you do not need to make any
selection.
To select more than one item, click on your first selection, then hold down the Control
key and make the rest of your selections.
6. When you have specified the parasitics you want, click OK.
The Extractor form reappears with the parasitics you selected in the Switch Names
field.
7. Click OK or Apply to create the extracted views.
A message in the command interpreter window (CIW) tells you when the extraction
process is complete.
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Creating ConcICe Views from Extracted Views
The Assura RC network reducer reduces networks with a large amount of parasitic resistance
and capacitance data into smaller, electrically equivalent networks that you can more easily
use with analysis tools. If you decide to use concICe views, the flow described in this chapter
can accommodate them. However, you should be aware of the following.
■
In a concICe view, all cross-coupling capacitors between analog nets are grounded.
■
When you use a concICe view in the flow, you can probe interconnects in the layout view
only at the terminals.
For detailed information on creating concICe views from extracted views, see the ConclCe
Help.
Comparing Schematic and Extracted Views
To compare the schematic view with the extracted view created earlier, follow these steps. (To
compare the schematic view with a concICe view, follow the same steps but substitute the
concICe view for the extracted view.)
1. From a window displaying the extracted view, choose Verify – LVS.
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The LVS form appears. For a detailed description of the fields and buttons, see
Appendix A, “LVS Form Field Descriptions.”
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2. Depending on which views are open, use one of the following procedures to identify the
schematic and extracted views that you want to compare.
If both the schematic and extracted
views are open
If only the extracted view is open
1. Click the Sel by Cursor button
below the schematic detail, then
click the cursor in the open
schematic view.
1. Click the Sel by Cursor button
below the extracted detail, then click
the cursor in the open extracted
view.
2. Do the same for the extracted view.
2. Click the Browse button below the
schematic detail and select the
schematic view.
3. Enter the names of the rules file and rules library for the Diva LVS rules.
4. Click the Run button near the bottom of the form to begin the comparison.
Click here.
5. When the comparison finishes, click Info.
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The Display Run Information form appears.
Click here
6. Click Log File.
Scroll through the log file to the netlist comparison section near the end of the file. This
section identifies any mismatches between the two files. Each error is described in the
sections following the comparison results.
Not all mismatches are fatal. Look over the comparison results to determine if you need
to correct one of the files and redo the extraction and comparison or if you can proceed
with the views as they are.
7. Choose File – Close Window in the log file window.
8. Click Cancel in the Display Run Information form.
9. Correct any problems in the schematic or extracted views.
10. If necessary, rerun the comparison.
Building an analog_extracted View
When the comparison between schematic and extracted views is acceptable, you need to
select the parasitics to use for simulation. You also need to build the analog_extracted view.
1. In the LVS form, click on Build Analog.
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The Build Analog Extracted View form appears.
2. Select one of the following choices to specify the analog parasitics that you want to use
for simulation.
Select
If you want to
Include All
Simulate with all the parasitics that have been extracted.
Set From Schematic
Select parasitics to include in the simulation by placing
special symbols (spresistor, spcapacitor, spinductor,
and spcapacitor2) on nets in the schematic view. The
spcapacitor2 device is used to include parasitics in the
simulation that appear between two specified nets. If
you add or remove symbols from the schematic, click
Check and Save to save the modified view.
The parasitics you select by placing these symbols
(which are provided in sbaLib) are the only ones
included in the simulation.
If you choose Set From Schematic and click OK
without identifying any nets on the schematic, the
Extracted Parasitics Selective Annotation form asks you
to confirm your choice.
None
Simulate with none of the parasitics.
3. Click OK to accept your settings and build the analog_extracted view.
Creating and Using a Configuration
This section explains how to set up a configuration so that the simulator runs with the
analog_extracted view created in the previous step. The steps given here for using the
Hierarchy Editor to create a configuration are abbreviated. For complete information, see the
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Cadence Hierarchy Editor User Guide. If your design already has a configuration, skip to
Step 13.
To create a configuration for your design,
1. From the CIW, choose File – New – Cellview.
The Create New File form appears.
2. Choose the library for the new file.
3. Type the name of the cell for which you want to create the configuration.
The top-level cell for your design is usually the appropriate cell to use.
4. If you do not want to use config as the view name, type the name you want into the
View Name field.
5. Choose Hierarchy-Editor from the Tool drop-down list box.
6. Ensure that the Library path file field correctly specifies the cds.lib file that contains
the paths to your libraries.
7. Click OK.
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The New Configuration form appears.
8. Click on the Use Template button located at the bottom of the form.
The Use Template form appears.
9. Select a template that is compatible with the simulator you are running from the Name
drop-down list box.
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10. Click OK in the Use Template form.
The New Configuration form redisplays with default data for the Top Cell and Global
Bindings sections. This allows you to modify a typical view list and stop list, rather than
creating them from scratch.
Templates exist for each of the simulators. (To create templates that provide defaults for
these fields, see the Cadence Hierarchy Editor User Guide.)
11. In the Top Cell section, enter the library, cell name, and schematic cellview from which
to build the configuration.
Be sure to specify schematic for the view type because the configuration is built from
the original schematic of your design.
12. Click OK.
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The Hierarchy Editor window displays your data.
The Hierarchy Editor window configures the design by using a default View List and
Stop List in the Global Bindings section. You need to modify these lists for your design.
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13. Use one of the following methods to specify the analog_extracted view for the cells or
blocks for which you want parasitics simulated.
To specify views for individual blocks To specify views for multiple blocks
1. In the Instance Binding section of ➤
the Hierarchy Editor window,
position the cursor in the View To
Use column of the appropriate
block.
Note: If the Instance Binding
section is not visible in the window,
choose View – Instance Table to
display this section.
In the Global Bindings section of
the Hierarchy Editor window, add
analog_extracted as the first
view in the View List text field.
This ensures that the
analog_extracted view is the
selected view for every cell that has
an analog_extracted view.
2. Press the right mouse key to display
a list of commands.
3. Choose Select View to display the
list of views for this block.
4. Choose analog_extracted as the
view for this block.
14. Choose View – Update to reconfigure the design to reflect your changes.
The Update Sync-up form appears.
15. Click OK.
16. Choose File – Save to save the configuration with your changes.
17. Choose File – Exit to close the Hierarchy Editor.
Simulating the Design
To run the simulation,
1. In the CIW, choose Tools – Analog Environment – Simulation.
The Analog Artist Simulation window appears.
2. Choose Setup – Design.
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The Choosing Design form appears.
3. Choose the library and cell name of your design.
4. Choose config from the View Name drop-down list box.
5. Click OK.
This view supplies configuration as well as schematic information.
6. In the Analog Artist Simulation window, choose your simulator, model path, environment
variables, analyses, and simulator options.
7. Choose Simulation – Run.
When complete, the schematic appears so that you can select outputs and probe the
design.
8. Choose Outputs – Set from Schematic.
9. Click on terminals in the schematic or in the layout views of the blocks where parasitics
were extracted, to select outputs.
Note: The only places where connections on different views are guaranteed to match are on
component terminals.
Probing Parasitic Values
By probing the schematic or extracted view, you can examine the instances of parasitic
components. To probe parasitic values, follow these steps.
1. In the LVS form, click the Parasitic Probe button.
The Parasitic Probing form appears.
2. In the Max list size field, specify how many parasitic instances to display.
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3. Sort parasitics by resistance or capacitance by selecting R or C.
4. Click the appropriate button to specify which parasitics should be collected.
❑
Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
❑
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
❑
Click Net to Net and then click on two nets in the schematic or extracted view to
collect parasitic capacitances between two different nets.
A list of the collected parasitic instances appears. Select an instance from this list to
highlight the component symbol associated with this parasitic on the extracted view.
Backannotating Parasitic Values
1. Click the Backannotate button on the LVS form to backannotate the resistances and
capacitances to the schematic.
The Parasitic Backannotation form appears.
2. Select the font size and label offsets that you want and click the Add Parasitics button.
Resistance and capacitance labels appear on the schematic view. To see them, you
might need to zoom in on a portion of the schematic. Note that the new information
displayed on the schematic is for viewing only. Using the Add Parasitics button does not
include the parasitics in the schematic.
3. Click the Remove Parasitics button to remove these labels.
4. Choose Print All to write all of the parasitics to a file.
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The Print All Parasitics form appears.
5. Click the appropriate Sort Parasitics by button.
Select R for a list sorted by resistance. Select C for a list sorted by capacitance.
6. Specify the filename for the printed listing.
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2
Diva Flow: Simulating Mixed-Signal
Circuits with Parasitics
The information in this chapter describes how you can use Cadence® tools to investigate the
effect of parasitics on mixed-signal circuits. By accounting for the effect of parasitics, you can
improve the accuracy of your circuit simulations. If your design includes only analog circuits,
go to Chapter 1, “Diva Flow: Simulating Analog Circuits with Parasitics” instead.
Click a topic below for more information.
■
“Overview” on page 31
■
“Estimating Delays (Pre-Layout)” on page 31
■
■
❑
“Setting Up for Pre-Layout Delay Estimation” on page 32
❑
“Simulating a Design with Pre-Layout Estimation” on page 40
“Calculating Delays (Post-Layout)” on page 40
❑
“Preparing for Post-Layout Mixed-Signal Parasitic Simulation” on page 43
❑
“Creating mixed_extracted Views” on page 48
❑
“Modifying the Configuration” on page 58
❑
“Setting the Mixed-Signal Simulation Options” on page 59
❑
“Simulating a Design (Post-Layout)” on page 61
“Probing Parasitic Values” on page 62
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Overview
The flows in this chapter describe two ways to calculate delays for mixed-signal circuits.
■
You can estimate delays before layout by using timing library format (TLF) and fan-in and
fan-out information.
■
You can use layout information to determine delays with increased accuracy.
The pre-layout flow is discussed in “Estimating Delays (Pre-Layout).” For information on using
layout information to calculate delays, see “Calculating Delays (Post-Layout)” on page 40.
Before following any of the flows in this chapter, be sure that the environment variable
CDS_Netlisting_Mode is set to Analog. To ensure that all the tools for the flow are
available, start your session with the command icfb.
Estimating Delays (Pre-Layout)
Even without layout information, you can obtain useful delay estimates of digital partitions by
following the pre-layout mixed-signal parasitic simulation (MSPS) flow illustrated in Figure 2-1
on page 32. The figure illustrates how Affirma™ timing analyzer (the Cadence static timing
analyzer) operates on the digital netlist to produce a standard delay format (SDF) file. The
MSPS flow then annotates the SDF file to the top-level cell instance.
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Figure 2-1 Pre-Layout Simulation Flow
Top Level
Configuration View
pearl.cmd
Mixed-Signal Netlister
gcfConstraints.gcf
Digital Netlist
Analog Netlist
compiled TLF
Affirma™ timing analyzer
SDF
SPECTRE®
IPC
VERILOG®.VMX
Setting Up for Pre-Layout Delay Estimation
To specify that delays are to be estimated, set up the Mixed Signal Options form as described
in the following steps.
1. Choose Simulation – Options – Mixed Signal in the Analog Artist Simulation window.
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The Mixed Signal Options form appears.
2. If necessary, set the DC Interval and Max DC Iterations fields.
For information on these fields, see the Affirma Mixed-Signal Circuit Design
Environment User Guide.
3. Turn on the Estimate (Pre-Layout) button.
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The form expands as shown below:
4. Edit the delay calculator files as necessary.
For guidance, see “Preparing the pearl.cmd and gcfConstraints.gcf Files” on page 34.
5. Ensure that you have a correctly set up the SDF annotator file (sdf.cfg).
For more information, see “Editing the SDF Annotator File” on page 39.
Preparing the pearl.cmd and gcfConstraints.gcf Files
The Affirma timing analyzer requires two control files: pearl.cmd and
gcfConstraints.gcf. The pearl.cmd file is the command initialization file for the Affirma
timing analyzer. The gcfConstraints.gcf file specifies the boundary and operating
conditions for the analysis and lists the compiled timing library format (CTLF) file to be used.
You can do either of the following:
■
Provide these files in one of the locations listed in “Locations Searched for the pearl.cmd
and gcfConstraints.gcf Files” on page 35
If you provide the files, clicking on the Command and Constraints buttons opens the
files for editing.
■
Create these files from templates by clicking on the Command and Constraints buttons
If the files do not exist, clicking the buttons copies templates to your run directory and
opens the copies for editing.
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Locations Searched for the pearl.cmd and gcfConstraints.gcf Files
The Affirma timing analyzer searches for the pearl.cmd and gcfConstraints.gcf files
in the following locations, which are searched in the order given.
1. The run directory
For example, if the simulation directory is $HOME/simulation, the run directory is
$HOME/simulation/topLevelCellName/simulatorName/viewName/
netlist/digital
2. Your working directory (where you start icfb or icms)
3. Your home directory ($HOME)
4. Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)
Editing the pearl.cmd and gcfConstraints.gcf Files
You can change the contents of the gcfConstraints.gcf and pearl.cmd files as
necessary.
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1. To change the gcfConstraints.gcf file, click the Constraints button in the Mixed
Signal Options form. Your default text editor opens, displaying the contents of the file. For
example, the file might contain information like this.
(GCF
(HEADER
(VERSION "1.2")
Change this to the name of your top(DESIGN "ccadc")
level design.
(TIME_SCALE 1.0E-09)
)
(GLOBALS
(GLOBALS_SUBSET ENVIRONMENT
(OPERATING_CONDITIONS "" 1.00 3.13 100.00)
(EXTENSION "CTLF_FILES" ("./timing.ctlf"))
(VOLTAGE_THRESHOLD 10.0 90.0)
)
)
Specify the path to the compiled CTLF
(CELL()
file here.
(SUBSET TIMING
(ENVIRONMENT
(INPUT_SLEW 1.60 1.60)
)
)
)
)
Important
Change the design name to the name of your top-level design. Ensure that the path
to the compiled timing library format (CTLF) files is specified with one of the
following.
❑
An absolute path
❑
A relative path defined with respect to the run directory
For more information about the run directory, see “Locations Searched for the pearl.cmd
and gcfConstraints.gcf Files” on page 35.
Do not use a tilde (~) to specify the path.
When you finish editing the file, save it.
2. To change the contents of the pearl.cmd file, click the Command button in the Mixed
Signal Options form.
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The Command Options form appears.
The Command Options form allows you to change the options that are listed in the
following table.
Option
Default
Meaning
Power Node
VDD
The name of the power node. You must specify this
value for cells with tie-high connections.
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Option
Default
Meaning
Ground Node
VSS
The name of the ground node. You must specify this
value for cells with tie-low connections.
Library
Corner
all
One of all, min, typ, or max indicating the type of
delays the Affirma timing analyzer uses for calculating
total delay. The Library Corner choice also applies to
PVT values that are defined as triplets.
SDF files report delays as triplets; for example,
(1.999:2.685:3.244). If you specify all, the output is in
the min:typ:max triplet format, otherwise all three
values in the triplet are the same. For example, if you
specify max, the output for this example is
(3.244:3.244:3.244).
Slew Mode
all
One of all, min, typ, or max indicating the type of rise
and fall times (slew rates) that the Affirma timing
analyzer uses.
Wireload
Library
Blank
A timing library format (TLF) library name defined with
the TLF Library statement. The netlister searches for a
wireload model only in this library.
If you do not specify a library, the netlister searches all
the TLF libraries until it finds a wireload model with the
specified name or group.
Wireload
Group and
Value
Blank
A group of wireload models specified with a
Wireload_By_xxx statement in the TLF library,
where xxx is Area, Cell_Count, Gate_Count, or
Transistor_Count. The value specifies the block
area, cell count, gate count, or transistor count. For
more information, see the Affirma Pearl Timing
Analyzer User Guide
Wireload
Name
Blank
The name of a wireload model specified with a
Wireload or Wireload_By_xxx statement in the
TLF library.
Wireload
Topology
balanced
One of none, cap, best, worst, balanced, or star.
For use only with RC estimation, this option describes
the topology of the estimated nets.
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Option
Default
Meaning
SDF Timing
Scale
ns
Either ns (nanoseconds) or ps (picoseconds). The unit
of time the Affirma timing analyzer uses when
reporting delay values.
SDF
Precision
4 for ns
units; 0 for
ps units
The number of digits the Affirma timing analyzer prints
after the decimal point.
Report
Boundary
Nets
Not
selected
A button telling the Affirma timing analyzer to calculate
the interconnect delays for nets connecting to primary
I/O pins (ports) at the boundary of the design block. If
you select this button, the Affirma timing analyzer
reports boundary net delays in the SDF file.
SDF Edge
Specifier
Not
selected
A button telling the Affirma timing analyzer to write SDF
IOPATH statements with edge specifiers on the input
signal when both inverting and non-inverting paths
exist between two pins.
Editing the SDF Annotator File
The simulator uses the sdf.cfg file to control the SDF annotation. An existing sdf.cfg file
that you want the simulator to use must be located in one of the following locations, which are
searched in the following order. These are the same locations searched for the pearl.cmd
and gcfConstraints.gcf files.
1. The run directory
For example, if the simulation directory is $HOME/simulation, the run directory is
$HOME/simulation/topLevelCellName/simulatorName/viewName/
netlist/digital
2. Your working directory (where you start icfb or icms)
3. Your home directory ($HOME)
4. Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)
To edit the sdf.cfg file, or to copy a template so that you can create a new sdf.cfg file,
1. Click Config on the Mixed Signal Options form.
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The SDF Annotator Config File form appears.
2. Change the values as necessary. If you need guidance, see the SDF Annotator User
Guide.
Simulating a Design with Pre-Layout Estimation
After you set up the mixed-signal simulation options, you are ready to simulate. Follow the
standard mixed-signal simulation process.
Calculating Delays (Post-Layout)
Simulating a mixed-signal design with parasitics calculated from layout information involves
the following major steps:
1. Preparing cell libraries
2. Creating a mixed_extracted view of your design
3. Creating or modifying a configuration for the design so that mixed_extracted views are
used for the mixed-signal simulation
4. Using one of the mixed-signal simulators to simulate the configured schematic with
parasitics included
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Figure 2-2 shows the flow for steps 2 and 3 in graphical format. The Assura™ RC network
reducer steps are shown with dotted lines because they are optional.
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Figure 2-2 Post-Layout Simulation Flow
Diva Physical Verification
Rules File
layout View
Extractor
extracted View
Assura™ RC network reducer
.simrc File
config View
concice View
LVS
config View
map files
Build_Mixed
mixed_extracted
View
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Top Level
config View
SPF
MS Netlister
pearl.cmd
gcfConstraints.gcf
Digital Netlist
Analog Netlist
compiled TLF
Affirma™ timing analyzer
SDF
External SDF
SPECTRE®
IPC
VERILOG®.VMX
Digital parasitics are calculated by the Affirma timing analyzer or can be imported from an
external calculator. The SDF file created by the Affirma timing analyzer is annotated to the
netlist at simulation time.
Preparing for Post-Layout Mixed-Signal Parasitic Simulation
Before you can run a post-layout mixed-signal parasitic simulation, you must ensure that the
necessary preliminary steps are complete. The following sections describe the tasks.
■
“Preparing Libraries for Post-Layout Mixed-Signal Parasitic Simulation” on page 44
■
“Preparing Layout Views for Analog and Digital Cells” on page 46
■
“Updating View and Stop Lists for LVS” on page 47
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■
“Preparing to Create the top.spf File” on page 48
Preparing Libraries for Post-Layout Mixed-Signal Parasitic Simulation
Ensure that the cells and primitives that you plan to use in a post-layout parasitic simulation
have the following required views and information.
Analog cells must have
Analog primitives must have
schematic view
simulation stopping view
symbol view
auLvs view (the default stopping view for
auLvs)
layout view (with ivCellType =
"graphic" for analog layouts with pins)
CDF simulation information
Digital cells must have
Digital primitives must have
symbol view
msps view
logic view (verilog, for example)
CDF simulation information for LVS
schematic view
if you are using the Affirma timing analyzer,
an entry in a compiled timing library format
(CTLF) file
layout view (with ivCellType = “graphic” for
hierarchical digital blocks)
The following sections describe how to prepare some of this information.
Creating an msps View for a Digital Primitive
Each digital primitive must have an msps stopping view, which is required for layout versus
schematic (LVS).
To create msps views,
1. In the CIW, choose Tools – Mixed Signal Environment – Prepare Library for MSPS.
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The Create msps views & auLvs CDF simInfo form appears.
2. Select the primitives for which you want to create msps views. As described below, you
can either select the primitives manually or select primitives that have certain specified
views.
Selecting Primitives Manually
To select primitives manually,
1. Choose cells from the Not in the Selected List list box, and click the right-arrow button
to add them to the In the Selected List list box.
If you want to, you can highlight and move multiple entries.
2. To create an msps view for each cell in the In the Selected List list box, click OK or
Apply and then click Yes in the create msps views confirmation form.
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Selecting Primitives with Specified Views
To select primitives that have specified views,
1. Click Select Cells.
The Select Cell Views form appears.
2. Change the View Choice List field as necessary.
The views specified in the View Must List field and the View Choice List field become
the selection criteria for digital primitives. To be selected, a cell must have all the views
specified in the View Must List field and at least one of the views specified in the View
Choice List field.
For example, assume that View Must List contains layout and symbol and that View
Choice List contains behavioral and auLvs. Then any cell that has a layout view, a
symbol view, and either a behavioral view or an auLvs view meets the search criteria.
3. Click OK or Apply.
The search results appear in the In the Selected List list box on the Create msps views
& auLvs CDF simInfo form.
4. In the Create msps views & auLvs CDF simInfo form, click OK or Apply to create an
msps view for each cell in In the Selected List.
5. Confirm your actions by clicking Yes in the create msps views confirmation dialog box.
6. If any of the selected cells have existing auLvs CDF siminfo, the create auLvs Siminfo
confirmation dialog box asks you to confirm the overwrite.
Preparing Layout Views for Analog and Digital Cells
In macro mode, the extractor treats any cell with pins as a macro cell and stops expanding it.
If a block is an analog block or a hierarchical digital block and requires further expansion, you
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need to add the property ivCellType = "graphic" to the layout master of the block.
With this property set, the extractor expands the cell even though pins exist.
You can set the ivCellType property at the instance level or for multiple cells in the
macroCellFile. Refer to the Assura Diva Verification Reference for details on either
of these methods.
For example, the following procedure sets the ivCellType property at the instance level for
a cell. With this method, every instance of this cell in the design has the same setting.
1. Open in edit mode the layout view of the instance you want expanded to the transistor
level.
2. From the Layout window, choose Design – Properties.
The Edit Cellview Properties form appears.
3. Click Add.
The Add Property form appears.
4. Type ivCelltype in the Name field.
5. Set the Type drop-down list box to String.
6. Type graphic in the Value field.
7. Click OK to add the new property and its value.
Updating View and Stop Lists for LVS
The .simrc file contains the view lists and stop lists for Assura Diva® LVS. For mixed-signal
parasitic simulation, you must update these lists with the msps view before you run LVS.
To update the lists,
1. Open the .simrc file using any editor.
2. Add or update the following variable definitions in the .simrc file so that the msps view
appears at the beginning of each list. For example, after you update the file, the
definitions might look like this:
lvsSchematicViewList =
'( "msps" "auLvs"
"schematic" "symbol")
lvsSchematicStopList =
'( "msps" "auLvs")
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lvsLayoutViewList =
'( "msps" "auLvs"
"extracted")
lvsLayoutStopList =
'( "msps" "auLvs")
For standard settings for these variables, refer to the Assura Diva Verification
Reference.
3. Save the .simrc file.
Preparing to Create the top.spf File
The Affirma timing analyzer uses a standard parasitic format (SPF) file called top.spf,
which contains the parasitic information for your design. In preparation for creating this file,
you must ensure that the property names for resistance and capacitance are set to r and c.
➤
In the CDF Simulation Information section of the presistor or pcapacitor component,
specify the resistance and capacitance parameter names as r and c.
Creating mixed_extracted Views
For mixed-signal blocks, the extraction process consists of
1. Verifying consistent pin direction in schematic and layout views
2. Extracting parasitics and creating extracted views
3. (Optional) Creating concice views
4. Comparing the schematic and extracted (or concice) views
5. Creating mixed_extracted views and (optional) using the Affirma timing analyzer to
generate delay calculation files
The mixed_extracted views and the optional SDF files become input to the simulation of the
top-level design.
You can run the extraction process on selected blocks within the design or on the entire
design.
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Verifying Consistent Pin Direction
To verify that pin directions on the schematic and layout views are consistent,
1. From a window displaying the layout or extracted view, choose Verify – MSPS Check
Pins.
The MSPS Check Pins form appears.
2. Click OK.
The CIW displays a list of any discrepancies. Fix them before you extract the parasitics.
Extracting Parasitics and Creating Extracted Views
To extract parasitics and create extracted views,
1. From a window displaying a layout view of the cell, choose Verify – Extract.
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The Extractor form appears.
2. Choose macro cell for Extract Method.
This allows the digital cells to be extracted at the macro level.
Be sure that any analog blocks have the ivCellType property set to graphic. This
ensures that the analog blocks are flattened. For more information, see “Preparing
Layout Views for Analog and Digital Cells” on page 46.
3. (Optional) Choose Join Nets With Same Name.
This ensures that nets with the same name are joined automatically.
4. Click Set Switches to select the type of parasitics you want extracted.
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The Set Switches form appears. The parasitics displayed vary, depending on the
extraction rules file defined for your design. In some cases, you do not need to make any
selection.
To select more than one item, click on your first selection, then hold down the Control
key and click on the rest of your selections.
5. Click OK.
The Extractor form reappears with the parasitics you selected in the Switch Names
field.
6. Click OK or Apply to create the extracted views.
A message in the CIW tells you when the extraction process is complete.
Creating Concice Views from Extracted Views
The Assura RC network reducer reduces networks with a large amount of parasitic resistance
and capacitance data into smaller, electrically equivalent networks that you can more easily
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use with analysis tools. If you decide to use concice views, the flow described in this chapter
can accommodate them. However, you should be aware of the following.
■
In a concice view, all cross-coupling capacitors between analog nets are grounded.
■
When you use a concice view in the flow, you can probe interconnects in the layout view
only at the terminals.
For detailed information on creating concice views from extracted views, see the ConcICe
Help.
Comparing Schematic and Extracted Views
To compare the schematic view with the extracted view created earlier, follow these steps. (To
compare the schematic view with a concice view, follow the same steps but substitute the
concice view for the extracted view.)
1. From a window displaying the extracted view, choose Verify – LVS.
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The LVS form appears. For a detailed description of the fields and buttons, see
Appendix A, “LVS Form Field Descriptions.”
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2. Depending on which views are open, use one of the following procedures to identify the
schematic and extracted views that you want to compare.
If both the schematic and extracted
views are open
If only the extracted view is open
1. Click the Sel by Cursor button
below the schematic detail, then
click the cursor in the open
schematic view.
1. Click the Sel by Cursor button
below the extracted detail, then click
the cursor in the open extracted
view.
2. Do the same for the extracted view.
2. Click the Browse button below the
schematic detail and select the
schematic view.
3. Fill in the names of the rules file and rules library for the Diva LVS rules.
4. Click the Run button near the bottom of the form to begin the comparison.
Click here.
5. When the comparison finishes, click Info.
The Display Run Information dialog box appears.
6. Click Log File.
Scroll through the log file to the netlist comparison section near the end of the file. This
section identifies any mismatches between the two files. Each error is described in the
sections following the comparison results.
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Not all mismatches are fatal. Look over the comparison results to determine if you need
to correct one of the files and redo the extraction and comparison, or if you can proceed
with the views as they are.
7. Choose File – Close Window in the log file window.
8. Click Cancel in the Display Run Information dialog box.
9. Correct any problems in the schematic or extracted views.
10. If necessary, rerun the comparison and compare the results.
Building a Mixed_Extracted View
When the comparison between schematic and extracted views is acceptable, you need to
select the parasitics to use for simulation. You also need to build the mixed_extracted view.
1. In the LVS form, click Build Mixed.
The Build Mixed Extracted View form appears.
2. Verify that the Library, Cell, and View fields correctly specify the configuration view that
you want to use.
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If your design does not have a configuration view associated with it, refer to the Cadence
Hierarchy Editor User Guide and create a configuration.
Note: The msps view, used as the digital stopping view for LVS, is also used as the
internal stopping view for SPF generation when the build mixed process runs. Be sure
the configuration stopping view stops at digital cells that have an msps view.
3. Select one of the following options to specify the analog parasitics that you want to use
for simulation.
Select
If you want to
Include All
Simulate with all the parasitics that have been extracted
Set From Schematic
Select parasitics to include in the simulation by placing
special symbols (spresistors and spcapacitors) on nets
in the schematic view.
The parasitics you select are the only ones included in
the simulation.
The special symbols are available in the sbaLib library.
If you choose Set From Schematic and click OK
without identifying any nets on the schematic, the
Analog Parasitics Selective Annotation form asks you to
confirm your choice.
None
Simulate with none of the parasitics
4. Ensure that the pearl.cmd and gcfConstraints.gcf files are ready and available
in one of the following locations, which are searched in the order given.
❑
The run directory
library_path/cell/view/mixed_extracted/layout_msb
❑
Your working directory (where you start icfb or icms)
❑
Your home directory
❑
Your installation path ($CDS_INST_DIR/tools/dfII/etc/tools/mmsimenv)
For guidance on using the Command and Constraints buttons to view or change these
files, see “Preparing the pearl.cmd and gcfConstraints.gcf Files” on page 34. When the
files are ready, turn on the Calculate button in the Digital Delays section.
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If you click OK without editing the pearl.cmd and gcfConstraints.gcf files or
without ensuring that the files are available in the searched directories, the Delay
Calculator Option Files dialog box appears.
5. Click Yes if you want to use the default templates for the option files.
6. To build the mixed_extracted view, click OK in the Build Mixed Extracted View form.
The build mixed process removes all digital parasitics and places them in the SPF file. The
Affirma timing analyzer uses the SPF file to calculate the delays and generate an SDF file.
The mixed_extracted view contains analog parasitics and analog and digital instances for
netlisting and simulation.
The build mixed process creates or places the following files in the layout_msb directory.
Filename
Description
msbCheckFile
Timestamp file specifying the SPF creation time
msbEnableFlag
Zero-length file that indicates the Affirma timing analyzer
is on, and enables sdfAnnotate
pearl.cmd
Command initialization file for the Affirma timing
analyzer
gcfConstraints.gcf
File that defines constraints, operating conditions, and
compiled timing library format (CTLF) files used by the
Affirma timing analyzer
top.spf
Detailed SPF file with digital parasitics
top.tmp.sdf
SDF file generated by the Affirma timing analyzer delay
calculation
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Filename
Description
annotate.com
File that contains a $sdf_annotate command with the
location of the top.sdf file
runPearl.log
Error and log file
Modifying the Configuration
To use parasitic simulation, you must specify mixed_extracted as the View To Use for each
cell in your top-level design for which you want the extracted parasitics simulated. To specify
mixed_extracted as the View To Use, you modify the configuration for your top-level design.
If your design does not have a configuration, refer to the Cadence Hierarchy Editor User
Guide.
To modify a configuration,
1. Open the Hierarchy Editor and specify the configuration for your top-level design.
2. Use one of the following methods to specify the mixed_extracted view for the cells or
blocks for which you want parasitics simulated.
To specify views for individual blocks To specify views for multiple blocks
1. In the Instance Binding section of
the Hierarchy Editor window,
position the cursor in the View To
Use column of the appropriate
block.
2. Press the right mouse key to display
a list of commands.
1. Add mixed_extracted as the
first view in the Global Bindings
View List text field. This ensures
that the mixed_extracted view is the
selected view for every cell that has
a mixed_extracted view.
3. Choose Select View to display the
list of views for this block.
4. Select mixed_extracted as the
view for this block to update the
View Found and View To Use
fields.
3. Choose View – Update to reconfigure the design to reflect your changes.
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4. To save the configuration with your changes, choose File – Save.
5. To close the Hierarchy Editor, choose File – Exit.
Partitioning is done automatically by comparing the Global Bindings Stop List field and the
Analog and Digital Stop View Sets.
Setting the Mixed-Signal Simulation Options
To set up the Mixed Signal Options form for post-layout delay calculations,
1. Choose Simulation – Options – Mixed Signal in the Analog Artist Simulation window.
The Mixed Signal Options form appears.
2. If necessary, set the DC Interval and Max DC Iterations.
For information on these fields, see Affirma Mixed-Signal Circuit Design
Environment User Guide.
3. Click the Use Existing (Layout) radio button.
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The form expands to allow you to use SDF files created during the build mixed process
and to import SDF files.
4. To use the SDF files created during the build mixed process, turn on the SDF From
Mixed Extracted View button.
5. To import SDF files created by a different tool, turn on the Import SDF Files button and
fill in the associated fields.
❑
In the File field, type the path to and filename of the SDF file that you want to import.
The name you enter must be a legal Verilog® language name.
❑
In the Scope field, type the hierarchical scope of the instance for which the delay
file is to be annotated during simulation. For example, you might type something like
I1/I3 to indicate an instance one level down in the hierarchy.
6. If you want to import more SDF files, click the Import More button and fill in the Import
SDF Files form as described in “Importing Additional SDF Files” on page 61.
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Importing Additional SDF Files
The Mixed Signal Options form provides space for you to enter the name of one SDF file to
be imported. If you want to import more than one SDF file, click the Import More button to
open the Import SDF Files form.
To use the form,
1. Type a number from 2 to 10 in the Number of Additional Files To Import field.
The form expands to accommodate the information that you want to enter.
2. For each additional file, type the name of the SDF file to be imported.
3. For each additional file, type the hierarchical scope of the instance for which the delay
file is to be annotated during simulation.
Simulating a Design (Post-Layout)
After you set up the configuration for the parasitic cells, you are ready to simulate the
configured schematic using one of the mixed-signal simulators. Follow the standard mixedsignal simulation process.
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Probing Parasitic Values
Although it is not required, you might want to probe the instances of parasitic components.
To probe parasitic values in the schematic or extracted views,
1. In the LVS form, click the Parasitic Probe button.
The Parasitic Probing form appears.
2. In the Max list size field, specify how many parasitic instances to display.
3. Sort parasitics by resistance or capacitance by selecting R or C.
4. Click the appropriate button to specify the parasitics to be collected.
❑
Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
❑
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
❑
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collect parasitic capacitances between two different nets.
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A list of the collected parasitic instances appears.
Select an instance from this list to highlight the component symbol associated with this
parasitic on the extracted view.
5. To backannotate the resistances and capacitances to the schematic view, click the
Backannotate button on the LVS form.
The Parasitic Backannotation form appears.
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6. Select the font size and label placement that you want and click the Add Parasitics
button.
Resistance and capacitance labels appear on the schematic view. To see them, you
might need to zoom in on a portion of the schematic. The new information displayed on
the schematic is for viewing only. Using the Add Parasitics button does not include the
parasitics in the schematic.
7. To remove these labels, click the Remove Parasitics button.
8. To write all of the lumped parasitics to a file, click Print All.
The Print All Parasitics form appears:
9. Click the appropriate Sort parasitics by button.
Select R for a list sorted by resistance. Select C for a list sorted by capacitance.
10. Specify the filename for the printed listing.
Even though you are simulating from the mixed_extracted view of the design, you can probe
signals from the schematic view. This is called out-of-context probing. You can also probe the
mixed_extracted view directly for analog and mixed nets.
Important
When you probe different types of signals (analog, digital, or mixed), keep in mind
which nets really exist in the mixed_extracted view. Probing a net or a terminal at a
level of the schematic that does not have a simulation waveform causes a probing
error.
Because analog components are flat in the mixed_extracted view, you cannot probe nets
connected to terminals of hierarchical analog blocks. You must descend to the transistor
level of the schematic to probe these nets. It is only at the transistor level that the program
can map terminals from the schematic to the mixed_extracted view.
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To probe a signal, click on the wire at a point close to the terminal. The probe automatically
jumps to the closest terminal on that net. An X appears on the selected terminal as shown in
the following figure.
You can select several terminals on the same net. Each selected terminal is marked with a
different color X. The associated waveform displays in the same color as the X on the
schematic.
You can select and probe only real geometries from a mixed_extracted view. For example, if
the metal layer is broken up into resistors, the geometries do not have connectivity. In this
case, you need to probe the metal layer at contacts and vias.
If you are unable to select a geometry on the mixed_extracted view, the layer might be invalid.
Set valid layers from the Edit menu of the LSW form.
If you probe a net that cannot be mapped to a terminal in the mixed_extracted view, warnings
similar to the following appear:
*WARNING* Could not obtain the external name
*WARNING* Unable to map net 'VBG'
*Warning* no valid full path name for net "VBG", selection not taken
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You can probe mixed-nets connected to terminals of hierarchical analog blocks near the
digital terminal, but not near analog terminals, as shown in the following figure.
Probe here.
Analog Block
Do not probe here.
Actual nets being probed
Analog Block
D2A
A2D
In the netlist
In the netlist
The D2A and A2D elements are attached to the digital components in the netlist. The output
of the D2A element or the input of the A2D element, therefore, is a valid analog net in the
extracted view.
Because digital parasitics are removed from the mixed_extracted view, digital nets can be
probed anywhere and do not have to be associated with terminals. An X is placed in the
middle of the net indicating its selection.
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3
Diva Flow: Working Through an Extended
Design Example
The three sections of this design example provide an overview of the front-to-back mixedsignal simulation flow for Analog Artist® Design Environment 4.4.3. The circuit used
throughout this design example is a counter-controlled A/D converter (ccadc). The circuit
simulator used is spectreVerilog. For more information on mixed-signal simulation, refer to the
Affirma Mixed-Signal Circuit Design Environment User Guide.
The three sections of this example are
■
“Simulating with Schematic Data” on page 68
■
“Simulating with Analog Parasitics and Estimated Digital Delays” on page 84
■
“Simulating with Analog and Digital Parasitics” on page 111
Before you can follow the steps in these sections, you need to prepare the libraries and start
the tools that are used.
1. Copy the mixed-signal design example files to your home directory by typing the
following at the command prompt:
cp -r your_inst_dir/tools/dfII/samples/artist/mixSig/msps
2. Change directories (cd) to msps.
3. Extract the sample mixed-signal library files for use in this design example. Type the
following at the command prompt:
tar xvf mixSigLib.t
4. To start the Cadence® software and enter the mixed-signal simulation environment, type
the following at the command prompt:
icfb &
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The command interpreter window (CIW) appears.
Note: If the icfb command does not work, contact your Cadence system administrator for
assistance.
Simulating with Schematic Data
In this section, you run a simulation using mixed-signal hierarchical netlisting (MHNL) and
schematic data only (no layout data). The tasks to perform are summarized here, and the
steps to complete them follow.
■
Configuring and partitioning the design
■
Simulating the design
■
Plotting and saving results
Configuring and Partitioning the Design
A configuration file defines the cell and instance view selections for netlisting and simulation.
The mixed-signal partitioner uses the configuration file and configured schematic to provide
expansion information for your design.
Creating a Configuration File
In the following steps, you use the hierarchy editor to create a configuration file—or config
view—for the tutorial schematic.
1. From the CIW, choose Tools – Library Manager.
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The Library Manager window appears.
2. Select the mixSigLib library and the tutorial cell. (Scroll down the list of cells to select
the tutorial cell.)
3. Choose File – New – Cell View.
The Create New File form appears.
4. In the Tool drop-down list box, choose Hierarchy - Editor. Notice that the View Name
field automatically changes to config.
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5. Click OK.
The Hierarchy Editor window opens, and a New Configuration form appears.
6. In the New Configuration form, click Use Template.
The Use Template form appears.
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7. In the Use Template form, choose spectreVerilog in the Name drop-down list box.
The template provides lists of views that are most often used for that simulator.
8. Click OK.
The New Configuration form redisplays with default data in the Top Cell and Global
Bindings sections.
9. In the Top Cell section, View field, replace myView with schematic.
The configuration file is built from the original schematic.
10. Click OK.
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The Top Cell, Global Bindings, and Cell Bindings sections in the Hierarchy Editor
window are updated with your selections. Notice that the Hierarchy Editor window now
displays all of the cells in the design and the default cell bindings.
11. To save this new configuration, choose File – Save in the Hierarchy Editor window.
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Modifying the Configuration
You can override the default cell bindings and specify other views for partitioning or
simulation. In the following steps, you change some cell bindings and update the
configuration view from the Hierarchy Editor.
1. In the Hierarchy Editor window, move the cursor into the View To Use field for the
4-bit DAC cell.
2. Press the right mouse button and choose Select View to display the available views for
this cell.
3. Choose schematic and release the right mouse button. The View Found and View To
Use fields are updated with your selection.
4. Repeating this process, change the View To Use for the Comparator cell to ahdl and
for the counter cell to schematic.
You have to scroll down in the Cell Bindings section to the counter cell.
5. To propagate the changes through the hierarchy, update the configuration by using either
of the following methods:
❑
From the menu bar in the Hierarchy Editor window, choose View – Update.
❑
Click on the update icon in the tool bar.
Note: Whenever a white exclamation mark with a red background appears over the update
icon, an update is needed.
update icon
Because you are updating the configuration, you need to save the changes to disk to syncup the Hierarchy Editor (HED) with icfb (because they are separate processes). The Update
Sync-up form appears. Click OK.
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Opening the Configured Schematic
Next, you open the schematic view specified in the configuration file.
1. In the Top Cell section of the Hierarchy Editor window, click Open.
The configured schematic for the tutorial cell opens.
2. Notice that the title bar of the schematic window identifies the schematic as being
opened from a configuration (config) view.
Note: You run subsequent netlisting processes and simulations from this configured
schematic view to access the design expansion information.
For more information about design partitioning and creating a configuration file, refer to
Affirma Mixed-Signal Circuit Design Environment User Guide.
Simulating the Design
1. From the configured schematic window, choose Tools – Analog Environment.
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The Analog Artist Simulation window appears.
2. Make sure the status bar displays Simulator: spectreVerilog and that ~/simulation
is the project directory. (To check the project directory, choose Setup – Simulator/
Directory/Host).
Note: If a different simulator or project directory is displayed, choose Setup – Simulator/
Directory/Host and use the Choosing Simulator/Directory/Host form to make changes as
needed.
3. Choose Setup – Model Libraries.
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The Model Library Setup window appears.
You need to specify every model file that is used in the simulation. In this case, all the
device models that you need are in a file called models.scs.
4. Click Browse.
The Unix Browser form appears.
5. Find models.scs and click on it.
6. Click Apply.
7. In the Model Library Setup form, click Add.
The path to the msps model file appears at the top of the Model Library File list box.
Because you are using mixed signal, you also need to add the interface elements to the
model file list.
8. Add CML_a2d.scs and CML_d2a.scs to the list displayed in the Model Library Setup
form.
9. Choose Cancel in the Unix Browser form.
10. Click OK in the Model Library Setup form.
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Choosing an Analysis
1. From the simulation window, choose Analyses – Choose.
The Choosing Analyses form appears.
2. Set Analysis to tran (transient).
3. Type 125n in the Stop Time field.
4. Ensure that the Enabled button is selected.
5. Click OK.
The analysis information appears in the Analyses section of the simulation window.
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Generating a Netlist
Analog Artist automatically creates a netlist when you run a mixed-signal simulation, so this
procedure is optional.
1. From the simulation window, choose Simulation – Netlist – Create.
The mixed-signal netlister creates separate analog (Spectre®) and digital (Verilog®)
netlists.
2. Examine the netlists.
Notice that hierarchical netlisting preserves the design hierarchy.
Both analog and digital netlists contain interface elements. These interface elements are
placed at every analog-to-digital and digital-to-analog connection. Interface elements
allow the Spectre and Verilog simulators to exchange information during simulation. For
more information on interface elements, refer to “Mixed-Signal Interface” of the Affirma
Analog Circuit Design Environment User Guide.
Spectre interface elements definitions
Verilog interface elements definitions
// Begin Interface Element Header and Verimix Synchronization task
initial begin
$vmx_initialize( ‘_VMX_SIMULATOR_NAME_ , dc_mode_flag);
$vmx_define_export( test.top.I0.net45, "I0/99999"); // /I0/net45
$vmx_define_export( test.top.I0.net155, "I0/99998"); // /I0/net155
$vmx_define_export( test.top.I0.net154, "I0/99997"); // /I0/net154
$vmx_define_export( test.top.I0.net153, "I0/99996"); // /I0/net153
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3. Choose File – Close Window to dismiss the netlist windows.
Starting the Simulation
1. From the simulation window, choose Simulation – Run.
Alternatively, because you have already created a netlist, you can click on the Run
Simulation button (yellow traffic light).
2. View the progress of the simulation in the spectre.out and verilog.log windows. At the end
of a successful simulation, the following appears in the CIW:
reading simulation data...
...successful.
Plotting Results
1. From the simulation window, choose Outputs – To Be Plotted –
Select On Schematic.
2. On the configured schematic, click on the output of the AND gate (andOut), the output
of the comparator (compOut), and the output of the DAC (dacOut).
Select these
outputs.
The outputs to be plotted appear in the Outputs section of the Analog Artist Simulation
window.
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3. From the simulation window, choose Results – Plot Outputs – Transient.
A Waveform window displays the results.
dacOut
compOut
The counter counts up. The digital output of the counter converts to an analog voltage
via the DAC. Once the DAC voltage exceeds the input reference voltage (as defined by
the Input design variable), the comparator output swings low and shuts off the clock.
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Alternate Waveform Views
The analog waveforms are currently displayed in analogComposite view. You can also display
the analog waveforms in strip mode. (Digital waveforms are always displayed in strip mode.)
1. To view the analog waveforms in strip mode, type the following in the CIW:
envSetVal("asimenv.plotting" "stripModeType" ‘cyclic "analogStrip")
2. Press Return.
3. In the Waveform window, choose Window – Reset.
4. From the simulation window, choose Results – Plot Outputs – Transient.
The analog simulation results appear as strips in the Waveform window.
5. To return to viewing composite waveforms, type the following in the CIW:
envSetVal("asimenv.plotting" "stripModeType" ‘cyclic "analogComposite")
6. Press Return.
7. In the Waveform window, choose Window – Reset.
8. Replot the results from the simulation window.
For more information on plotting, refer to “Plotting Results” on page 79.
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Saving the Simulation Results
The mixed-signal front-end simulation is complete. Before you go on to the next section, save
these simulation results so you can compare them to the results of the back-end simulation
that you will run in “Simulating with Analog and Digital Parasitics” on page 111.
1. From the simulation window, choose Results – Save.
The Save Results form appears.
2. In the Save As field, type config-frontEnd.
3. Click OK.
Saving the Simulation Environment
You can also save this simulation environment setup to a state file, for use in “Simulating
with Analog Parasitics and Estimated Digital Delays” on page 84.
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1. From the simulation window, choose Session – Save State.
The Saving State form appears with state1 in the Save As field.
2. Click OK.
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Ending This Session
1. To end this session, choose Session – Quit from the simulation window.
2. Close the schematic window; do not save changes.
3. Exit the hierarchy editor.
Simulating with Analog Parasitics and Estimated Digital
Delays
Delay calculation is essential for predicting and verifying the performance of IC and boardlevel designs. The scope of delay calculation extends from the front-end logic design to the
back-end layout tools.
In this section, you run a mixed-signal simulation with extracted analog parasitics and
estimated (prelayout) digital parasitics. The tasks to perform are summarized here, and the
steps to complete them follow.
■
Extracting analog parasitics
■
Setting partitions
■
Estimating digital delays
■
Simulating the design
In this design example, you also view the analog backannotated parasitics.
Extracting Analog Parasitics
You can extract parasitics from cells in the design below the first level of hierarchy. You can
run the extraction process on blocks within the design or on the entire design.
The analog parasitic extraction process consists of extracting parasitics, running LVS (layout
versus schematic comparison for terminal mapping), and creating an analog extracted view.
You repeat this process for each block in your design where you want parasitics extracted.
In this design example, you build an analog extracted view for the 4-bit DAC cell.
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Extracting Parasitics
1. If a Library Manager window is not already open, start the library manager from the CIW
by choosing Tools – Library Manager.
2. In the Library Manager window, select mixSigLib as the library, 4_bit_DAC as the cell,
and schematic as the view.
3. Choose File – Open.
A schematic window opens, displaying the 4-bit DAC schematic. This is an analog-only
design.
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4. From the Library Manager window, open the layout view of the 4-bit DAC. (Select layout
as the View and choose File – Open).
5. In the layout window, choose Verify – Extract.
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The Extractor form appears.
6. Choose Join Nets With Same Name.
This ensures that nets with the same names are automatically joined.
7. Click on Set Switches to select the parasitics to be extracted.
The Set Switches form appears, showing the parasitics defined for your design.
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8. Select parameters, Rparasitics, and Rpoly.
9. Click OK.
The Switch Names field updates with the parasitics you selected.
10. Ensure that the Extractor form is filled in as shown.
11. Click OK to start the extraction process.
You can follow the extraction process in the CIW. When the extraction completes
successfully, the following message appears in the CIW:
***Summary of rule violation for cell "4_bit_DAC layout" ***
Total errors found: 0
12. Close the 4-bit DAC layout window. Do not save changes.
Comparing Views
In this procedure, you run LVS, which compares the schematic view with the extracted view
you just created. Any mismatches are identified at the end of the run.
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1. In the Library Manager window, select the extracted view of the
4-bit DAC cell.
2. Choose File – Open.
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A new window opens with the extracted view.
3. In the extracted view window, choose Verify – LVS.
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The LVS form appears.
4. Ensure that the fields are filled in as shown above.
If the Create Netlist section of the form is not filled in as shown, you must identify the
schematic and extracted views that you want to compare.
❑
Click Sel by Cursor on the schematic side and click again in the 4-bit DAC
schematic window. The Library, Cell, and View fields are updated automatically.
❑
Click Sel by Cursor on the extracted side, then click in the 4-bit DAC extracted view
window. The Library, Cell, and View fields are updated automatically.
5. Click the Run button at the bottom of the LVS form to begin the comparison.
6. Click the Info button to view the log file while LVS is running.
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The Display Run Information form appears.
7. Click Log File.
A log file window opens and the LVS run information appears.
Running simulation in directory: "/user1/msps/LVS".
Begin netlist:
Aug 4 22:35:15 1997
view name list = ("msps" "auLvs" "extracted")
stop name list = ("msps" "auLvs")
library name = "mixSigLib"
cell name = "4_bit_DAC"
view name = "extracted"
globals lib = "basic"
Upon successful completion of the LVS run, the log file displays information about the
netlist comparison.
The net-lists match.
un-matched
rewired
size errors
pruned
active
total
layout schematic
instances
0
0
0
0
0
0
0
0
80
80
80
80
nets
un-matched
merged
pruned
active
total
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0
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62
0
0
0
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un-matched
total
End comparison:
terminals
0
0
14
14
Aug 4 22:35:43 1997
Comparison program completed successfully.
Backannotating Parasitics
During extraction, Assura™ Diva® calculated the parasitics associated with the 4-bit DAC and
stored this information in the extracted view. In this procedure, you use the backannotation
and parasitic probing features of LVS to display the parasitic information on the schematic.
1. Bring the schematic view to the front. Zoom in on the upper left corner of the schematic.
2. On the LVS form, click Backannotate.
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The Parasitic Backannotation form appears.
3. Click Add Parasitics.
The parasitic information associated with each net displays on the schematic. This
information is for illustrative purposes only. The resistors and capacitors are not actually
added to the schematic.
Backannotated
parasitics
4. Click Remove Parasitics.
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5. Click Cancel to close the Parasitic Backannotation form.
Parasitic Probing
1. In the LVS window, click Parasitic Probe.
The Parasitic Probing form appears.
Clicking Whole Net dumps all parasitics on the net, up to the Max list size designated
on the form. Clicking Point to Point dumps the parasitics between two terminals you
select on the schematic. Clicking Net to Net shows the parasitics between two different
nets.
2. Click Whole Net.
3. On the schematic, select the output of the 4-bit DAC.
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A form appears, displaying the parasitics for the net you selected.
4. Select one of the presistors on this form.
In the top right corner of the extracted view, the corresponding presistor highlights. If you
select another presistor on the form, the highlight on the extracted view changes
accordingly.
5. Click Cancel to close the form.
6. In the Parasitic Probing form, click Cancel to close the form.
7. Close the schematic, layout, and extracted view windows. Do not save
the data.
Leave the LVS form open.
Building an Analog Extracted View
To include the analog parasitics for simulation, you must first create an analog extracted view.
This view contains the analog parasitic information. For more information, refer to Chapter 1,
“Diva Flow: Simulating Analog Circuits with Parasitics.”
1. On the LVS form, click Build Analog.
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The Build Analog_Extracted View form appears.
2. For Extracted Parasitics, ensure that Include All is selected.
This option selects all extracted analog parasitics for simulation.
3. Click OK to build the analog extracted view.
The analog extracted view is built when the CIW displays
Building analog_extracted view for 4_bit_DAC
Done
You can now simulate the 4-bit DAC with parasitics.
4. Choose Commands – Close Window to close the LVS window.
Setting Partitions
In this section, you prepare to run the simulation with the analog extracted view you just
created.
Setting Up the Simulator
1. In the Library Manager window, choose mixSigLib as the library, tutorial as the cell, and
config_FE as the view. (Scroll down the list of cells to select the tutorial cell.)
2. Choose File – Open.
Either the Open Configuration or the Top CellView form appears.
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3. Click yes to open both the Configuration and the Top Cell View.
4. Click OK.
The configured schematic for the tutorial cell opens, and the Hierarchy Editor window
appears.
5. In the configured schematic window, choose Tools – Analog Environment.
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The Analog Artist Simulation window appears.
6. Make sure the status bar displays Simulator: spectreVerilog and that ~/simulation
is the Project directory. (To check the Project directory, choose Setup – Simulator/
Directory/Host.)
Modifying the Configuration
In the following steps, you display the View to Use and Inherited View List properties on
the configured schematic and change those properties prior to circuit simulation.
Viewing the Design Partition
1. Click on the ccadc block in the schematic window.
2. Choose Design – Hierarchy – Descend Edit to descend into the ccadc schematic.
A Descend form appears.
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3. In the Descend form, set View Name to schematic.
4. Click OK.
The schematic view of the ccadc displays.
5. From the schematic window, choose Mixed-Signal – Display Partition – Interactive.
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The Partition Display form appears.
6. Click on Show View List.
7. Click Apply.
On the schematic, View To Use shows view = view_name, and Inherited View List
shows View List = view_name_list.
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For example, on the 4-bit DAC, View to Use is schematic, and Inherited View List is
$default.
8. On the comparator and counter cells, verify that View to Use is schematic.
9. In the Partition Display form, click Cancel.
Changing the View to Use
Before running the simulation, you must change the View To Use field to the analog
extracted view you created earlier. You can change View To Use from the hierarchy editor
(HED) or from the Hierarchy-Editor menu in the configured schematic window. In this
example, you use the Hierarchy-Editor menu.
1. In the configured schematic window, choose Hierarchy-Editor – Set Instance
Binding.
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The Set Instance Binding form appears.
2. On the configured schematic, select the 4-bit DAC.
3. On the Set Instance Binding form, set the View Binding drop-down list box to
analog_extracted.
4. Click OK.
The instance on the schematic updates.
5. To propagate this change through the hierarchy editor, save the changes to disk.
6. Return to the hierarchy editor and click View - Update.
7. Click OK in the Update Sync-up form.
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In the hierarchy editor, notice that the View To Use field for the 4-bit DAC is
analog_extracted.
8. From the configured schematic window, choose Design – Hierarchy –
Return To Top.
Estimating Digital Delays
In this section, you prepare to simulate the design with prelayout digital delay estimates. You
load the state file from the previous simulation, then set up the Affirma timing analyzer to
generate prelayout digital delay estimates for simulation. The Affirma timing analyzer also
generates post-layout digital delays for mixed-signal parasitic simulation. Refer to the Affirma
Pearl Timing Analyzer User Guide for more information about using the Affirma timing
analyzer.
Loading the Simulation State
1. In the Analog Artist Simulation window, choose Session – Load State.
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The Loading State form appears.
2. In the State Name list box, select state1.
3. Click OK.
The simulation window updates, and the waveform window opens, displaying the results
of the previous simulation session.
Setting Up Pre-layout Estimation and the Affirma Timing Analyzer
1. From the simulation window, choose Simulation – Options – Mixed Signal.
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The Mixed Signal Options form appears.
2. For Digital Delays, choose Estimate ( Pre-Layout ).
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The form expands to show additional buttons.
The Affirma timing analyzer requires two initialization files to run: pearl.cmd and
gcfConstraints.gcf. The Affirma timing analyzer searches for these files in the
locations described by “Locations Searched for the pearl.cmd and gcfConstraints.gcf
Files” on page 35. If the files are not in these locations, the Affirma timing analyzer uses
a default, which can be found at $CDS_INST_DIR/tools/dfII/etc/tools/
mmsimenv. For this example, use the defaults.
3. Click Command to open the Command Options form.
The information in this form is used in the pearl.cmd file.
4. Click OK to close the form.
5. In the Mixed Signal Options form, click Constraints.
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An edit window opens with the gcfConstraints.gcf file.
6. Change the DESIGN entry to "tutorial".
7. Change the "CTLF_FILES" path to the path to your TLF file. For this example the path
is
home_dir/msps/mixSigLib/timing.ctlf
Do not use a tilde (~) to specify the path.
8. Save your changes and close the edit window.
9. In the Mixed Signal Options form, click Config.
The SDF Annotator Config File form appears. You need the sdf.cfg file controlled by
this form to send the correct annotate commands to the spectreVerilog netlist. For this
example, use the defaults.
10. Click OK.
11. On the Mixed Signal Options form, click OK.
Simulating the Design
1. In the Analog Artist Simulation window, choose Simulation – Netlist and Run.
The saved state included the waveforms to be plotted. Upon successful completion of
the simulation, the waveforms of andOut, compOut, and dacOut plot automatically.
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You can now compare the previous simulation results to the current results with analog
parasitics and estimated digital delays.
2. In the Simulation window, choose Results – Printing/Plotting Options.
3. The Setting Plotting Options form appears.
4. Choose Overlay Plots.
5. Click OK.
6. In the Simulation window, choose Results – Select.
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The Select Results form appears.
7. Select config-frontEnd.
This is the name of the results file you saved from the front-end simulation in “Simulating
with Schematic Data” on page 68.
8. Click OK.
9. Click the Plot Outputs button in the lower right corner of the Analog Artist Simulation
window.
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The waveform window overlays the results of the front-end simulation. Note that in the
simulation with analog delays, the DAC voltage exceeds the input reference voltage
sooner, and the circuit shuts off one cycle earlier.
10. To end this session, close all windows except the CIW. Do not save any changes.
Simulating with Analog and Digital Parasitics
In this procedure, you simulate a mixed-signal design with both analog and digital parasitics.
To fully experience mixed-signal parasitic simulation (MSPS), you run two simulations. In the
first simulation, you use AHDL, analog extracted, and mixed extracted views. In the second
simulation, you use one mixed extracted view for the entire ccadc design. You will see how
the second approach affects probing on the schematic.
The tasks to perform are summarized here, and the steps to complete them follow. In this
design example, some of the tasks are already done for you.
■
Preparing cell libraries
■
Partitioning the design (block-level)
■
Creating extracted views (block-level)
■
Modifying the configuration file (top-level)
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■
Simulating the design (top-level)
■
Waveform probing
For a complete MSPS flow description, refer to “Calculating Delays (Post-Layout)” on
page 40.
Cell Library Requirements
Cell libraries must contain appropriate views of analog and digital cells. In addition to the
basic setup for mixed-signal simulation, the following views are required for MSPS:
For analog cells in the library:
■
Layout view
Note: For analog layouts with pins, ivCellType must be graphic.
■
auLVS view (the default stopping view for auLVS) and CDF simulation information for
analog primitives
For digital cells in the library:
■
Layout view
Note: For hierarchical digital blocks, ivCellType must be graphic.
■
msps view (stopping view for auLVS and Build Mixed) and CDF simulation information
for digital primitives
Note: For information on creating an msps view, refer to “Creating an msps View for a
Digital Primitive” on page 44.
■
If using the Affirma timing analyzer, a compiled TLF (.ctlf) file provides a timing
definition for each digital primitive
For parasitic components:
■
In CDF simulation information, componentName must be presistor or pcapacitor
■
Properties are extracted as r and c
Creating a Mixed Extracted View
To simulate a digital block or a mixed analog and digital block with parasitics, you must create
a mixed extracted view.
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In this procedure, you build a mixed extracted view for the counter cell.
Extracting Parasitics
1. From the CIW, open the layout and schematic of mixSigLib/counter.
2. From the layout window, choose Verify – MSPS Check Pins.
The MSPS Check Pins form appears.
3. Click OK.
This runs a pin direction check between the layout and schematic views of the counter
cell, which verifies that pin directions are consistent on the schematic and layout views.
Discrepancies in pin direction might generate an incorrect netlist.
The following appears in the CIW.
Comparing Pins between Library:mixSigLib,Cell:counter,View:schematic
and Library:mixSigLib,Cell:counter,View:layout
The following pins Do Not match between the schematic and layout:
("vcc!" "gnd!")
The following pins direction Do Not match between the schematic and
layout:
Sch_Pin_Name Direction
Lay_Pin_Name
Direction
MSPS: done...
The pin direction check finds that the supply pins in the layout do not exist in the
schematic. This does not matter for digital blocks because, in the final mixed extracted
view, the symbol of the counter takes the place of the macro cells. Therefore, the final
netlisting view does not contain the supply pins.
4. From the layout view window, choose Verify – Extract.
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5. Set up the Extractor form as shown. Set all switches except capOnly.
Note: You must set Extract Method to macro cell to stop extraction of digital cells
below the top level of hierarchy.
6. Click OK to create the extracted view.
As the extracted view is created, you can view progress in the CIW.
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Comparing Views
1. Open the extracted view of the counter cell.
2. From the extracted view window, choose Verify – LVS.
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Make sure the form is set up correctly for the counter cell.
3. Click Run to start LVS.
4. Check the output to make sure the netlists match.
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Building a Mixed Extracted View
The build mixed process removes all digital parasitics and places them in an SPF file. The
Affirma timing analyzer uses the SPF file to calculate digital delays and generate an SDF file,
which provides the digital delay information used during mixed-signal parasitic simulation.
1. On the LVS form, click Build Mixed.
The Build Mixed Extracted View form appears.
Note: View must be set to config. The config view tells the software which cells are
analog and which cells are digital.
2. Click Command.
The Command Options form appears. If the mixed extracted view did not previously exist,
the form uses a pearl.cmd file found in the locations detailed in “Locations Searched
for the pearl.cmd and gcfConstraints.gcf Files” on page 35. If there is no pearl.cmd file
in one in those locations, the form gets a default file from $CDS_INST_DIR/tools/
dfII/etc/tools/mmsimenv.
3. Click OK.
4. Click Constraints in the Build Mixed Extracted View form.
The gcfConstraints.gcf file opens in an edit window. Update the DESIGN entry to
"counter" and the CTLF_FILES entry to the path to timing.ctlf.
5. Save your changes and close the edit window.
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6. In the Build Mixed Extracted View form, click OK.
The Affirma timing analyzer starts running in the background and the output appears in
the Affirma timing analyzer log file.
7. Open the mixed extracted view of the counter cell.
8. Zoom into the origin until you see symbols of all blocks in the counter stacked one on top
of the other.
Notice that all macro cells in this view are replaced with modified schematic names to
preserve the original schematic hierarchy in the digital netlist.
9. Close all windows except the CIW.
Simulating the Design
In this design example, you use two different approaches to mixed-signal parasitic simulation.
The first is the block approach, in which you simulate the design using extracted parasitics
only from selected blocks. The second is the whole design approach, in which you simulate
the design using a mixed extracted view for the entire design.
Block Approach to Mixed-Signal Parasitic Simulation
An MSPS simulation using extracted parasitics on selected blocks generally runs faster than
an MSPS simulation using a mixed extracted view of the entire design, but the results are not
as accurate. Using the block approach, you can add layout data when it becomes available.
1. From the CIW, open both schematic and configuration windows for mixSigLib/
tutorial/config_msps.
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2. View the design partitioning in the hierarchy editor. View To Use should be set as
follows:
4_bit_DAC to analog_extracted
Comparator to ahdl
ccadc to schematic
counter to mixed_extracted
3. From the configured schematic window, choose Tools – Analog Environment to open
an Analog Artist Simulation window.
4. In the Analog Artist Simulation window, choose Session – Load State.
The Loading State form appears.
5. In the State Name list box, select state1.
6. Click OK.
7. From the simulation window, choose Simulation – Options – Mixed Signal.
8. In the Digital Delays pane, choose Use Existing (Layout).
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The form expands to include additional controls.
9. Make sure that SDF From Mixed Extracted View is selected.
10. Click Config to set parameters in the sdf.cfg file.
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The SDF Annotator Config File form appears.
Note: For more information on parameters in the sdf.cfg file, refer to the SDF
Annotator User Guide.
11. Set the MTM (delay) value to TYPICAL.
12. Click OK.
Note: You can annotate only one delay value to the simulation. This value is determined
by the MTM setting.
13. On the Mixed Signal Options form, click OK.
14. Run the simulation by choosing Simulation – Netlist and Run in the Analog Artist
Simulation window.
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When the simulation completes, andOut, compOut, and dacOut plot automatically.
15. Close all windows except the CIW. Do not save changes.
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Whole Design Approach to Mixed-Signal Parasitic Simulation
In the following simulation, you use a mixed extracted view for the entire ccadc design. You
will see that this approach affects your ability to probe the schematic because extraction
flattens the design.
A mixed extracted view of the entire ccadc design has been created for this simulation.
1. From the CIW, open both schematic and configuration windows for mixSigLib/
tutorial/config_msps2.
Notice that the design partitioning is different from the config_msps view. The ccadc
is set to mixed_extracted (instead of schematic), and the counter is set to schematic
(instead of mixed_extracted). These changes are required because nested mixed
extracted views are not allowed.
2. From the schematic window, choose Tools – Analog Environment to open a simulation
window.
3. In the simulation window, choose Session – Load State.
The Loading State form appears.
4. In the State Name list box, select state1.
5. Click OK.
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6. Choose Simulation – Options – Mixed Signal and set up the Mixed Signal Options
form as shown.
7. Click Config.
On the standard delay format (SDF) form, ensure that MTM is set to TYPICAL.
8. Click OK in the SDF Annotator Config File form.
9. Click OK in the Mixed Signal Options form.
10. In the Analog Artist Simulation window, choose Simulation – Netlist and Run to run
the simulation.
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Notice that this simulation, which uses parasitics extracted from the entire design, takes
longer than the previous simulation, which used parasitics extracted only from selected
blocks.
When the simulation ends, andOut, compOut, and dacOut plot automatically.
Probing the Schematic
1. In the schematic window, choose Design – Hierarchy – Descend Edit. Select the
ccadc block and descend into the schematic view of ccadc.
2. Try to probe the net between the 4-bit DAC and the Comparator.
Notice that you cannot probe there. Although you are looking at the schematic view, you
ran the simulation from the mixed extracted view. The net you are trying to probe does
not exist on the mixed extracted view.
To probe this net, you must descend into the schematic view of the Comparator. Because
these cells are flat, the nets exist in both schematic view and mixed extracted view. Probe
on a terminal closest to the net between these two cells.
Comparing Simulation Results
In this procedure, you compare the results of the most recent parasitic simulation to the
results of the front-end simulation you performed in “Simulating with Schematic Data” on
page 68.
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1. From the Analog Artist Simulation window, choose Results – Printing/Plotting
Options.
The Setting Plotting Options form appears.
2. Choose the Overlay Plots option and click OK.
3. In the simulation window, choose Results – Select.
The Select Results form appears.
4. Click on config-frontEnd.
The config-frontEnd file contains the results of the front-end simulation with analog
delays.
5. Click OK.
6. Click on the Plot Outputs button in the lower right corner of the simulation window.
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A Waveform window displays the results.
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4
Assura Flow: Simulating Analog Circuits
with Parasitics
This chapter describes how you can use Cadence® Assura™ tools to investigate the effect of
parasitics on analog circuits. By accounting for the effect of parasitics, you can improve the
accuracy of your circuit simulations.
Click a topic below for more information.
■
“Overview” on page 128
■
“Preparing Cell Libraries” on page 130
■
“Creating Designs” on page 131
■
“Creating Extracted Views” on page 131
■
“Creating and Using a Configuration” on page 139
■
“Simulating the Design” on page 144
■
“Probing Parasitic Values” on page 145
Overview
Simulating an analog circuit with parasitics requires these steps,
1. Preparing cell libraries.
2. Creating an av_analog_extracted view of your design.
In this step, the tool calculates parasitics from information in the layout view of your
circuit.
3. Creating a configuration for your design.
4. Simulating the design with parasitics included.
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After a successful simulation, you can select terminals and device pins on the schematic and
use plot commands to display the results in a waveform window. The resulting waveforms can
be used with all Analog Artist® design system calculation and analysis tools.
The following flow diagram illustrates the substeps in creating an av_analog_extracted view
using the Assura physical verification tool.
schematic View
Assura Physical Verification
Rules File
layout View
LVS
RCX
av_extracted View
MSPS
Build Analog
av_analog_extracted View
Note: Diva physical verification rules files can be used with the Assura physical verification
tool to create an extracted view.
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Preparing Cell Libraries
Before you can follow the flow outlined in this chapter, you need to provide the following views
and component description format (CDF) information for analog primitives and parasitic cells.
Analog primitives must have
Parasitic cells (such as presistors and
pcapacitors) must have
symbol cellview
symbol cellview
layout cellview or extraction rules that the
extractor will recognize
auLvs cellview
Model matching the simulator you use
CDF simulation information for the auLvs
view
auLvs cellview that provides parameter
values used by layout versus schematic
(LVS)
CDF component parameters for resistance
(r) and capacitance (c)
The analogLib library contains examples of analog primitives and parasitic cells that you
can copy to create your cell library.
Preparing Technology Files
To prepare a library for parasitic extraction,
1. Describe the technology layers.
For details about the technology layers, refer to the Technology File and Display
Resource File User Guide.
2. Add or modify the verification rules used by the Assura processes.
The Assura processes include designed device extraction, LVS, and parasitic resistor
and capacitor extraction (RCX). Refer to the Assura Physical Verification Developer
Guide for details about creating verification and extraction rules.
Note: Use capacitance generation (capgen) to create the parasitic coefficients and files
required for parasitic simulation.
3. Prepare the Assura technology directory.
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This directory must contain all the designed device extraction rules, verification rules,
and the files required for parasitic extraction. Refer to the Assura Physical Verification
Developer Guide for details about preparing the Assura technology directory.
Creating Designs
If you intend to extract parasitic components from the layout view and run a simulation with
parasitics, use the following guidelines to avoid problems as you plan your design.
■
Devices with the componentName parameter set to pcapacitor, presistor, pinductor,
and pdiode are reserved for use by Cadence. Do not use these names for your
components.
■
Do not use the LVS permuteDevice parameter to match groups of components in a
series because that makes it impossible to determine which device to use for waveform
probing.
Creating Extracted Views
You first use the Assura physical verification tool to compare the layout view to the schematic
view. Assura creates an internally formatted database from the layout view. This database
contains only the designed devices. Assura RCX reads the database to extract the parasitics
and to create the extracted view. This extracted view contains designed devices and parasitic
devices.
Note: When you create an extracted view, the layout and schematic views need to match to
correctly associate the parasitics with the entire schematic network.
Comparing Views using LVS
To extract parasitics from the layout view of a cell or block,
1. Be sure that the environment variable CDS_Netlisting_Mode is set to Analog.
2. Start the Cadence software by typing the following at the command prompt:
icfb &
3. Choose Assura – Run LVS from the main menu bar of the Virtuoso® Layout Editor
window.
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The Assura Run LVS form appears. The first entry in the Technology definition file
assura_tech.lib is selected as the default in the Technology field.
assura_tech.lib
4. If you want to use a different technology definition file for your process, click on the
Select button to choose a technology definition file.
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Choosing a technology definition file automatically fills in the names of the rules files and
other files needed for LVS.
5. Click the Set Switches button.
The Set Switches form appears.
6. Select switches as needed and click OK.
❑
If you are using a Diva rule file containing the Extract? switch, select Extract?
from the list of switches.
❑
If the Diva rule file contains switches to specify parasitic extraction commands, do
not select these switches.
7. Click OK in the Assura Run LVS form to start the LVS run.
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A Progress Form appears during the LVS run. This form provides run status information
and contains Stop Run and Watch Log File options. The Progress Form automatically
closes after the run is complete.
A new dialog box appears indicating the LVS run is complete.
8. Click Yes to view the results of the LVS run.
Assura creates several run files with the cell name prefix, or run name prefix if you
specified a value for the run name. These files include the Assura generated database
and report files. The LVS errors for the top cell appear in a window generated by Assura.
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If there are no errors for the top cell, or errors in the run, you get a dialog box instead of
the LVS Error Report window.
Building an av_extracted View using RCX
Once the comparison between schematic and layout views is completed, you need to run
RCX to extract the parasitics and build the av_extracted view.
1. Choose Assura – Run RCX.
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The Assura Parasitic Extraction form appears.
xxx18u
analogChip
av_extracted
Note: If the Run RCX menu item is inactive, either the LVS runs have not been
completed or the LVS runs have been completed in a previous design framework II
session, or in batch mode, but have not been opened.
❑
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The Assura Open Run form appears.
analogChip
analogChip
❑
Select a run name from the list box located below the Run text field.
Once a run is selected, the run name appears in the Run text field.
❑
Choose OK to close the Open Assura Run form.
The LVS Error Report window appears if there are LVS errors in the top cell. If there
are no LVS errors, a dialog box appears informing you that there are no errors at this
level.
The Run RCX menu item becomes active.
❑
Choose Assura – Run RCX.
2. In the Assura Parasitic Extraction form, use the Extract Capacitance and Resistance
check boxes to choose the parasitics you want to extract.
3. Select an extracted view for output using the Output buttons.
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4. In the View text field, type the name of the view.
The default name is av_extracted, but you can create a view with any other name.
5. Select OK to start the parasitic extraction.
A Progress Form appears during the RCX run. This form provides run status information
and contains Stop Run and Watch Log file options. The Progress Form automatically
closes after the run is complete.
A new dialog box appears indicating the RCX run is complete.
6. Click Yes to view the results of the RCX run.
(Optional) Building an av_analog_extracted View using MSPS
Note: The user does not need to perform this step to simulate the Assura extracted view.
Building an av_analog_extracted view is only necessary if the user wants to filter parasitic
devices out of the extracted view.
The next step is to build an av_analog_extracted view using the mixed signal parasitic
simulation (MSPS). This new extracted view is derived from the av_extracted view.
1. Choose Assura – MSPS.
The Mixed Signal Parasitic Simulation form appears.
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2. In the Schematic Cellview group box, if the current view is not schematic, choose
schematic in the View drop-down list box.
3. In the Extracted Cellview group box, choose the av_extracted view created in “Building
an av_extracted View using RCX” on page 135.
4. Click the Build Analog button.
The Build Analog Extracted View form appears.
5. Choose which extracted parasitics are needed for the extraction.
6. Enter the extracted view name in the Analog Extracted View Name text field.
Note: The default analog extracted view name is av_analog_extracted.
7. Click OK.
The MSPS form closes and an av_analog_extracted view is created.
Creating and Using a Configuration
This section explains how to set up a configuration so that the simulator runs with the
av_analog_extracted view created in the previous step. The steps given here for using the
Hierarchy Editor to create a configuration are abbreviated. For complete information, see the
Cadence Hierarchy Editor User Guide. If your design already has a configuration, skip to
Step 13.
To create a configuration for your design,
1. From the CIW, choose File – New – Cellview.
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The Create New File form appears.
2. Choose the library for the new file.
3. Type the name of the cell for which you want to create the configuration.
The top-level cell for your design is usually the appropriate cell to use.
4. If you do not want to use config as the view name, type the name you want into the
View Name field.
5. Choose Hierarchy-Editor from the Tool drop-down list box.
6. Ensure that the Library path file field correctly specifies the cds.lib file that contains
the paths to your libraries.
7. Click OK.
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The New Configuration form appears.
8. Click on the Use Template button located at the bottom of the form.
The Use Template form appears.
9. Select a template that is compatible with the simulator you are running from the Name
drop-down list box.
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10. Click OK in the Use Template form.
The New Configuration form redisplays with default data for the Top Cell and Global
Bindings sections. This allows you to modify a typical view list and stop list, rather than
creating them from scratch.
Templates exist for each of the simulators. (To create templates that provide defaults for
these fields, see the Cadence Hierarchy Editor User Guide.)
11. In the Top Cell section, enter the library, cell name, and schematic cellview from which
to build the configuration.
Be sure to specify schematic for the view type because the configuration is built from
the original schematic of your design.
12. Click OK.
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The Hierarchy Editor window displays your data.
The Hierarchy Editor window configures the design by using a default View List and
Stop List in the Global Bindings section. You need to modify these lists for your design.
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13. Use one of the following methods to specify the av_analog_extracted view for the cells
or blocks for which you want parasitics simulated.
To specify views for individual blocks To specify views for multiple blocks
1. In the Instance Binding section of ➤
the Hierarchy Editor window,
position the cursor in the View To
Use column of the appropriate
block.
Note: If the Instance Binding
section is not visible in the window,
select View – Instance Table to
display this section.
In the Global Bindings section of
the Hierarchy Editor window, add
av_analog_extracted as the
first view in the View List text field.
This ensures that the
av_analog_extracted view is the
selected view for every cell that has
an av_analog_extracted view.
2. Press the right mouse key to display
a list of commands.
3. Choose Select View to display the
list of views for this block.
4. Choose av_analog_extracted as
the view for this block.
14. Choose View – Update to reconfigure the design to reflect your changes.
The Update Sync-up form appears.
15. Click OK.
16. Choose File – Save to save the configuration with your changes.
17. Choose File – Exit to close the hierarchy editor.
Simulating the Design
To run the simulation,
1. In the CIW, choose Tools – Analog Environment – Simulation.
The Analog Artist Simulation window appears.
2. Choose Setup – Design.
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The Choosing Design form appears.
3. Choose the library and cell name of your design.
4. Select the config view for your design.
5. Click OK.
This view supplies configuration as well as schematic information.
6. In the Analog Artist Simulation window, choose your simulator, model path, environment
variables, analyses, and simulator options.
7. Choose Simulation – Run.
When complete, the schematic appears so that you can select outputs and probe the
design.
8. Choose Outputs – Set from Schematic.
9. To select outputs, click on terminals in the schematic or in the layout views of the blocks
where parasitics were extracted.
Note: The only places where connections on different views are guaranteed to match are on
component terminals.
Probing Parasitic Values
By probing the schematic or av_extracted view, you can examine the instances of parasitic
components. The name, value, and net connectivity can be displayed for each parasitic
instance. To probe parasitic values, follow these steps.
1. Choose Assura – MSPS.
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The Mixed Signal Parasitic Simulation form appears.
2. In the MSPS form, click the Parasitic Probe button.
The Parasitic Probing form appears.
3. In the Max list size field, specify how many parasitic instances to display.
4. Sort parasitics by resistance or capacitance by selecting the R or C button.
5. Click the appropriate button to specify which parasitics should be collected.
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❑
Click Whole Net and then click on a net in the schematic or extracted view to display
an ordered list of all the parasitics on the net. The largest resistances or
capacitances appear at the top of the list.
Tip: If a parasitic instance is selected in the Parasitic List form, and the extracted view
is open, then the extracted view is zoomed to the component symbol associated with the
parasitic instance, and the cursor is moved to rest on the symbol.
Note: The zoom feature works for the Whole Net, Point to Point, and Net to Net
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options.
❑
Click Point to Point and then click on two pins or instance pins in the schematic or
extracted view to collect all the parasitics between two points.
If the points are on the same net, both resistances and capacitances are collected.
If the points are on different nets, only capacitances are collected.
❑
Click Net to Net and then click on two nets in the schematic or extracted view to
collect parasitic capacitances between two different nets.
A list of the collected parasitic instances appears. Select an instance from this list to
highlight the component symbol associated with this parasitic on the extracted view.
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Backannotating Parasitic Values
1. To backannotate the resistances and capacitances to the schematic, choose Assura –
MSPS.
The Mixed Signal Parasitic Simulation form appears.
2. Click the Backannotate button on the MSPS form.
The Parasitic Backannotation form appears.
3. Select the font size and label offsets that you want and click the Add Parasitics button.
Resistance and capacitance labels appear on the schematic view. To see them, you
might need to zoom in on a portion of the schematic. Note that the new information
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displayed on the schematic is for viewing only. Using the Add Parasitics button does not
include the parasitics in the schematic.
Note: The schematic window must be open for edit access to backannotate.
4. Click the Remove Parasitics button to remove these labels.
5. Choose Print All to write all of the parasitics to a file.
The Print All Parasitics form appears:
6. Click the appropriate Sort Parasitics by button.
Select R for a list sorted by resistance or C for a list sorted by capacitance.
7. Specify the filename for the printed listing.
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LVS Form Field Descriptions
The LVS program compares two versions of a circuit. For mixed-signal usage, you use LVS
to compare an extracted layout cellview with the schematic. For further details, refer to the
Assura Diva Verification Reference.
Run Directory defines the full or relative path to the run directory. If the directory you type
in does not exist, LVS creates the directory.
Browse displays a browser window that lets you select the run directory you want for this run.
Create Netlist creates netlists for the schematic and extracted cellviews. The first time you
run LVS, you must generate netlists for both cellviews. Any time you change cellviews, you
must generate a new netlist for that cellview.
schematic creates a netlist for the schematic cellview and enables or disables the
schematic cellview column.
The schematic option defines a working schematic cellview. If you have a schematic
cellview open, or if you use the defaults from the run directory, the Library, Cell, and
View fields are filled in automatically.
❑
Library is the library name for the schematic cellview.
❑
Cell is the cell name for the schematic cellview.
❑
View is the cellview name for the schematic cellview.
❑
Browse displays a browser window that lets you select the library, cell name, and
cellview name you want. Assura™ Diva® physical verification automatically enters
the cellview information in the form.
❑
Sel by Cursor fills in the rest of the fields with information from the schematic
cellview window you select with the mouse.
extracted creates a netlist for the extracted cellview and enables or disables the
extracted cellview column.
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LVS Form Field Descriptions
The extracted option defines a working extracted cellview. If you have an extracted
cellview open, or if you use the defaults from the run directory, the Library, Cell, and
View fields are filled in automatically.
❑
Library is the library name for the extracted cellview.
❑
Cell is the cell name for the extracted cellview.
❑
View is the cellview name for the extracted cellview.
❑
Browse displays a browser window that lets you select the library, cell name, and
cellview name you want. When you select a cellview using the Library Browser, Diva
physical verification automatically enters the cellview information in the form.
❑
Sel by Cursor fills in the rest of the fields with information from the extracted
cellview window you select with the mouse.
Rules File specifies either the UNIX location of a rules file or, if you specified a rules library,
the name of the rules file within the library.
Browse displays a browser window that lets you select the Rules Library and Rules File you
want.
Rules Library specifies the library from which the rules are referenced. If this option is not
selected, Diva physical verification gets the rules from a UNIX location.
LVS Options generates a cross-reference text file, fix devices, and bypass errors.
Rewiring changes the extracted and schematic network to bypass errors and continue
processing. Diva physical verification flags each change.
Device Fixing uses fix properties on device instances to limit device permutability.
Create Cross Reference generates a text file containing a list of nets and devices
found in both the layout and the schematic. The first number of a pair refers to the layout,
and the second number refers to the schematic. Net numbers begin with an N and device
numbers begin with an I.
Terminals uses terminals at the top level of the circuit as correspondence points.
Correspondence File uses file information for correspondence points.
Create creates a file containing the correspondence points for the LVS run.
Priority specifies the job priority of the LVS run. The highest priority is 0, and the lowest is 20.
Run specifies whether to run the verification checks on the local machine or a remote
machine. This field appears only if you have a remote Diva physical verification license.
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LVS Form Field Descriptions
local specifies your local machine.
remote specifies the workstation or server that contains the Diva physical verification
software and where the job is run. See the Assura Diva Verification Reference for
details on running Diva physical verification remotely.
Run starts the LVS program.
Output displays the Display Run Information form in which you can define the run information
that you want displayed in this run.
Error Display displays the LVS Error Display form.
Monitor displays the Analysis Job Monitor form, which displays information about the current
status of verification jobs, including the start time, host, status, and priority. You can also
suspend, remove, or change the priority of jobs in process.
Info displays the Show Run Information form, which displays the log file, output file, netlist
file, and error report.
When you use the Analog Artist® design system, four buttons appear at the bottom of the LVS
form. These buttons are used for backannotating parasitics, for probing parasitics, and for
building analog or mixed-signal views. When you use the command LayoutPlus to start
the Cadence® design framework II product, you do not see these buttons.
Backannotate displays the Parasitic Backannotation form. Backannotation allows you to
display the parasitic resistance and capacitance values from the layout on the schematic.
Note: Parasitic simulation produces useful working estimates of the combined resistances or
capacitances on each net, but they are not precise enough for simulation use, especially
when complex resistor networks are involved.
Parasitic Probe displays the Parasitic Probing form from which you can display the
parasitics for a specific net, between selected points, or between selected nets.
Build Analog displays the Build analog_extracted View form. This form specifies the
parasitics to be simulated for an analog block and builds an analog_extracted cellview.
Build Mixed displays the Build Mixed Extracted View form. This form specifies the analog
parasitics and digital delays for a mixed-signal design and builds a mixed_extracted cellview.
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