Cadence QRC Extraction
Better, faster design convergence with in-design and signoff
parasitic extraction
Cadence® QRC Extraction is the industry’s fastest, most accurate 3D full-chip parasitic extractor,
delivering in-design and signoff extraction. It supports both transistor-level and cell-level
extractions during design implementation and signoff, and it integrates seamlessly with both
Cadence Virtuoso® custom design and Cadence Encounter® digital implementation platforms.
This tight integration ensures ease of use, enables rapid analysis to accelerate design closure,
and provides better and faster convergence by using the same engine during implementation
and signoff.
Cadence QRC Extraction
As advanced process geometries
continue to shrink, parasitic extraction
becomes a necessity throughout
the design implementation flow
and the validation phase. Cadence
QRC Extraction is an integrated
extraction solution for design implementation and validation at 90nm
and below. It includes full-spectrum,
production-proven technologies for
all nanometer-scale design styles
including RF, analog, cell, mixedsignal, custom-digital, and thin-film
transistor liquid-crystal display
(TFT-LCD). It offers advanced capabilities such as multi-mode/multi-corner
(MMMC) extraction, RLCK extraction,
advanced process modeling, signoff
ECO, substrate analysis, statistical
extraction, distributed processing,
netlist reduction, DFM effects support,
and substrate parasitics extraction,
and it includes an integrated, foundryqualified field solver (QRC-FS).
QRC Extraction models physical
effects found in advanced process
technologies to ensure that extracted
parasitics match those on silicon. By
delivering higher quality parasitics, it
helps designers reduce overall design
cycle times and significantly enhance
the quality of silicon in complex
designs.
Integrated with the Virtuoso custom
design platform and the Encounter
digital implementation platform, QRC
Extraction is the most complete and
efficient path to accurate parasitic
extraction for all mainstream and
advanced node designs.
Benefits
Better, faster, and predictable
convergence
• Performs efficient analysis
of parasitic effects on circuit
performance with pre- and
post-layout simulation analysis
• Extracted View enables easy and
efficient simulation with Virtuoso
ADE
• Reduces ECO loops by using same
extraction engines in implementation and signoff to provide
predictable timing closure
Productivity and time to market
• Delivers best-in-class performance
for both single- and multi-process
corner extraction including multiple
temperatures
• Delivers the best performance
on both full-chip and hierarchical
designs without compromising
accuracy
• Unparalleled reduction technology
improves productivity without
impacting simulation time or timing
closure
Seamless integration with custom
design, digital implementation,
and signoff tools
• Shortens design cycles using
an in-design methodology with
Virtuoso and Encounter design and
analysis environments
• Features production-proven
in-design incremental extraction in
Encounter Digital Implementation
System
Cadence QRC Extraction
Design Convergence
Silicon Virtual Prototype
Power-Grid Synthesis
Early Prototyping
Default Extraction
Placement
perform parasitic extraction,
backannotation, crossprobing, re-simulation,
and analysis within a single
design environment for
increased productivity.
Used in-design with the Encounter
environment, QRC Extraction allows
designers to reduce design turnaround
time dramatically by performing incremental extraction, and to reach timing
closure faster by using signoff-accurate
extraction data for timing and noise
optimization.
Integrated QRC Extraction
QRC Extraction provides
silicon-accurate resistance (R) and capacitance
Clock-Tree Synthesis
(C) interconnect parasitic
extraction for all process
Post-CTS Optimization
technologies for transistorlevel designs including
Routing
RF, analog, mixed-signal,
Post-Route
custom, and memory. It
Post-Route
Optimization
provides highly accurate
Timing/SI Optimization
+ SI Optimization
parasitics of both dense and
Incremental
Signoff Extraction
sparse layouts for circuit
Extraction/ECO
simulation and analysis.
Timing, SI, Power
QRC Extraction integrates
Signoff
Signoff
Extraction
with Cadence layout-vs.schematic verification
Figure 1: Enabling in-design in the Encounter digital
technologies (Assura® LVS,
implementation platform
Physical Verification System);
with Mentor Graphics
• Speeds convergence on design closure
Calibre; and with Cadence simulation
via tight links with other Cadence
technologies (Virtuoso Spectre Circuit
signoff analysis technologies (Virtuoso
Simulator, Virtuoso Spectre RF Simulation
UltraSim Full-Chip Simulator, Virtuoso
Option, Virtuoso UltraSim Full-Chip
Spectre® Circuit Simulator, Encounter
Simulator).
Power System, Physical Verification
System, Encounter Timing System, and
Integration with the Encounter
Virtuoso Power System)
Power Routing
Support for all advanced node
functionality required at 28/20nm
• Supports all foundries
At advanced nodes with multi-million
instances designs, it is imperative
that parasitic load, read, and analysis
turnaround time is not a bottleneck. QRC
Extraction provides a binary interface and
format, RCDB, with Encounter Timing
RF
Analog
Mixed
Signal
Custom
Digital
Model-Based CMP and Litho
Hierarchical Extraction
Cell
Field Solver
L and K Extraction
Manufacturing Effects
QRC Extraction’s advanced cellbased 3D technology extracts
full-chip designs quickly and
has the capacity and accuracy
for signoff extraction on the
largest nanometer designs.
Accurate coupling capacitance extraction is a must for
crosstalk and power analysis of
sub-90nm designs. Integrated
with the Encounter design
environment, QRC Extraction
provides seamless solutions
for timing, IR, EM, and signal
integrity analyses, and for
power verification. It can
output distributed or lumped,
and coupled or decoupled
RC data.
Substrate
www.cadence.com
QRC–Encounter Timing System
binary interface
Reduction
An integral part of the silicon analysis
function inside the Virtuoso custom
design environment, QRC Extraction
supplies the critical parasitic information
for optimizing chip performance and
yield. Built on a foundation of patented
algorithms and proprietary extraction
technologies, QRC Extraction brings the
physics of interconnect parasitics into
the Virtuoso environment for designing,
characterizing, and optimizing chip
layouts. Seamless integration with
Virtuoso technology enables designers to
With the exploding number of process
corners at advanced nodes, design
convergence is becoming a bottleneck
in the design flow process. For example,
signal integrity issues can occur at hightemperature conditions and thus requires
efficient multi-corner extraction performance including temperature corners.
QRC Extraction provides the best and
most efficient solution to extract multiple
corners simultaneously while significantly
reducing overall runtime without compromising accuracy
Digital Implementation
Platform
Distributed Processing
Integration with the Virtuoso
Custom Design Platform
Multi-corner/temperature extraction
Multi-Corner / Statistical
• Enables double-patterning technology
(DPT) –aware extraction, litho bias,
multi-value SPEFs, etc.
Features
R and C Extraction
Figure 2: Key functionalities of Cadence QRC Extraction
2
Cadence QRC Extraction
Advanced CMP modeling support
QRC Extraction interfaces with innovative
Cadence chemical-mechanical polishing
(CMP) technology for modeling full-chip
thickness variation and accurately
predicting systematic variations in interconnect layer thickness. QRC Extraction
uses the resulting thickness information
to generate more precise estimates of
parasitic capacitance and resistance, and
thus more accurate timing analysis and
simulation results. By precisely predicting
CMP effects with this new capability,
designers targeting sub-65nm processes
can achieve more accurate timing analysis
and simulation, while manufacturing
teams can optimize yield.
w/o substrate
n-well
VDD
p-substrate
Vss
n-well
p-substrate
Figure 3: RF interconnect loss
System and the Encounter digital implementation platform. RCDB is a randomaccess format that reduces memory
footprint. It offers up to 120x better
performance while reading in the SPEF file
into Encounter Timing System, and 1.7x
overall runtime performance improvement
for extraction and SPEF read times
without compromising accuracy.
Wafer-Level
Variation
Wafer
Surface
Advanced substrate modeling
capability
RF designers need a tool that not only
extracts parasitic inductance accurately,
but also evaluates the impact of substrate
parasitics on their designs. Substrate
noise coupling is a growing concern due
to higher frequencies, higher integration,
smaller feature sizes, and lower supply
voltages. Including the p-substrate and
n-well as part of the substrate model
has an effect on the extraction result
and leads to RF interconnect loss. QRC
Extraction includes substrate Rs and Cs
for accurate simulation and analysis of
RF IC circuits, and allows designers to
perform what-if analysis for substrate
noise distribution.
Metal layers compound
the topographical impact
Wire
Global
Via
Intermediate
Local
Within-Chip
Variation
Chip
Surface
Oxide Loss
Dishing
Isolated
Isolated
Thin-Lines Wide-Lines
Erosion
Total Copper Loss
Dense
Array
Thin-Lines
Dense
Array
Wide-Lines
Figure 4: CMP interconnect variation
Distributed processing
QRC Extraction offers a distributed
processing capability to extract multimillion gate chips efficiently. It partitions the extraction task into multiple
independent tasks that can be executed
in parallel using multiple CPUs and/or
machines. Distributed processing can
significantly reduce extraction runtimes,
especially during the final signoff stages.
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Lightly doped substrate,
no guard ring
Lightly doped substrate with
guard ring connected to
ideal power supply
Heavily doped substrate, no
guard ring
Figure 5: What-if analysis with noise contour map (Cadence QRC Extraction GXL)
3
Cadence QRC Extraction
Cadence Services And Support
What you design is not what you get!
• Cadence application engineers can
answer your technical questions by
telephone, email, or Internet—they can
also provide technical assistance and
custom training
As drawn
As fabricated
Timing difference with and
without litho effect
Figure 6: Litho-aware extraction
Lithography-aware extraction
support
Foundry support
QRC Extraction interfaces with Cadence
silicon-correlated electrical designfor-manufacturing (DFM) analysis
technologies. Cadence Litho Electrical
Analyzer allows designers to optimize
and control the impact of lithography,
mask, etch, RET, and OPC effects on
chip parameters. Its contour-based
analysis technology provides an accurate,
model-based solution for designers to
minimize the impact of manufacturing
variations on design performance. It also
uses fab-certified technology to predict
contours across the process window
and to predict device and interconnect
electrical behavior.
• Cadence QRC Extraction process
files are:
–– Certified and supported by leading
merchant foundries
–– Flow tested and qualified with
foundry process design kits (PDKs)
–– Complemented by development
services (available from Cadence)
• Cadence certified instructors teach
more than 70 courses and bring
their real-world experience into the
classroom
• More than 25 Internet Learning
Series (iLS) online courses allow you
the flexibility of training at your own
computer via the Internet
• Cadence Online Support gives you 24x7
online access to a knowledgebase of
the latest solutions, technical documentation, and software downloads and
more
Format support
• Design input: GDSII, LEF/DEF, DFII, OA
• LVS data from Assura Physical
Verification, Physical Verification System
(PVS), and Calibre
• Design output: Extracted View, DSPF,
xDSPF, SPICE, SPEF, xSPEF, SSPEF
• Direct binary interface to Encounter
Timing System—RCDB
Specifications
Packaging
• Cadence QRC Extraction is available
in L and XL configurations for basic
extraction
• On top of the base licenses, Cadence
QRC Extraction has GXL options for
advanced analysis, nodes, and display
technologies
Platforms
• Sun Solaris (32-bit, 64-bit)
• Linux (32-bit, 64-bit)
• IBM AIX (32-bit, 64-bit)
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
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trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.
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