Design Aids – Global Resources in PSoC® Designer™ AN2221 Author: Mohana Koteeswaran Associated Project: No Associated Part Family: CY8C27xxx ® Software Version: PSoC Designer™ 5.0 or Newer Associated Application Notes: AN2027, AN2216, AN2219, AN2224 Application Note Abstract ® This application note describes the Global Resource settings in PSoC Designer™. These settings enable users to configure system level registers through an easy to use graphical user interface. This is one of the many unique features of PSoC Designer. It enables rapid system level configuration without manually writing system configuration registers. Figure 1. Global Resources Introduction This application note discusses each resource and its corresponding settings, and the registers affected by these resources. Good practices are recommended where applicable. ® Figure 1 shows the Global Resources window of PSoC TM Designer 5.0. Figure 2 on page 2 shows a flowchart ® overview of the PSoC clock sources. In addition, Table 2 in the Appendix (see page 6), lists the Global Resource Parameters, and their corresponding registers. Power Setting [Vcc/SysClk freq] This parameter enables the user to choose the Vdd at which the system runs and also the System clock frequency. Changing Vdd parameter changes the trim values for the oscillator and the Power-on-Reset (POR) levels. For more information on the PSoC Power-onReset, refer to Chapter 32 in the Technical Reference Manual, “POR and LVD.” When the source for Sysclk selected in “Sysclk_Source” parameter is Internal (IMO), the IMO frequency selected here in this parameter is used as the source for SysClk. The IMO frequency can either be 24 MHz or 6 MHz (Slow IMO (SLIMO)). Note: When the SysClk is set to 6 MHZ, the fastest CPU clock is now 6 MHz. Also note that the IMO is less accurate when running in SLIMO mode. But this saves more power on the part. CPU_Clock The CPU clock parameter sets the M8C processor speed. The system clock (SysClk) is divided to generate the CPU clock. The maximum CPU clock speed is 24 MHz. A 5V Vdd is necessary when the PSoC is running at 24 MHz. If running under 4.75V, the maximum CPU frequency is 12 MHz. Refer to device specific data sheet for more information. The CPU can operate at eight distinct frequencies. Each lower frequency saves power. A common mistake is to set the CPU to run at 24 MHz, while the chip is powered by 3.3V. Unexpected results may occur in this configuration. Make sure the maximum CPU speed is 12 MHz when running under 4.75V. January 20, 2009 Document No. 001-33759 Rev. *B 1 [+] Feedback AN2221 Another common mistake is the difference between the CPU clock and SYSCLK. The CPU clock is derived from SYSCLK. SYSCLK is almost always 24 MHz, while the CPU clock is adjustable, and must be adjusted for lower voltages. For more information on Digital Clocks, refer to the Technical Reference Manual Chapter 25, “Digital Clocks.” 32K_Select This parameter enables the designer to choose the source for 32 kHz clock. The 32 kHz clock remains operational even when the PSoC is in sleep mode. Any digital block that must be operational while the chip is in sleep can be clocked either from the 32 kHz clock source or an external unsynchronized signal. The 32 kHz clock can be selected from either the internal low speed oscillator or an external crystal connected to P1[0] and P1[1]. For more information, refer to AN2027, “Using the PSoC Microcontroller‟s External Crystal Operator” or the Technical Reference Manual Chapter 10, “External Crystal Oscillator.” The internal 32 kHz oscillator was built for driving the sleep timer clock, and the Watchdog. Due to this, the internal 32 KHz Oscillator is 50 percent accurate, and the frequency varies from chip to chip, and over temperature. If a more accurate 32 KHz signal is required, an accurate external crystal should be used. When this option is selected, all the appropriate registers are automatically set in boot.asm. Figure 2. Overview of PSoC Clock Sources January 20, 2009 Document No. 001-33759 Rev. *B 2 [+] Feedback AN2221 PLL_Mode VC3 Source PLL_Mode can be set to ‟Ext Lock‟ to phase lock loop (PLL) the internal main oscillator (IMO) with an external crystal. With this setting, the IMO is generated by multiplying an external 32.768 KHz crystal by 731 to generate a 23.968 MHz system clock. The VC3 clock source is user selectable, making it different from VC1 and VC2. Its source can be VC1, VC2, Sysclk, and Sysclk*2. Note The external crystal must be stable before enabling the PLL. For more information on PLL, refer to AN2027 and the Technical Reference Manual Chapter 11, “Phase-Locked Loop (PLL).” When this option is selected, boot.asm automatically creates code to perform this operation; there are no extra steps needed. Sleep_Timer The sleep timer is generated from the 32 KHz clock source. The sleep timer is used to drive an interrupt that periodically wakes up CPU when the CPU is in sleep mode. This parameter enables the user to select the frequency of this interrupt. The sleep timer need not be used only in conjunction with sleep. It can be used as a general purpose timing interrupt even when the CPU is not in sleep mode. The proper interrupt masks must be enabled for this interrupt to work. The user must edit the sleep timer interrupt vector to achieve desired interrupt functionality. Note The sleep timer interrupt is generated by the sleep timer using the 32 KHz clock source and can be inaccurate when the internal 32 KHz clock is used. Note that changing the sleep timer interval affects the WatchDog Timer interval also. Refer to the section on the WatchDog Timer. For more information on Sleep_Timer, refer to Chapter 12 in the Technical Reference Manual, “Sleep and WDT.” VC1 = SysClk/N VC3 Divider VC3 source is divided down by this parameter setting to generate the VC3 clock. The divide-by value can be set from 1 to 255. VC3 is used as a general purpose clock for the digital blocks VC3 signal can also generate an interrupt. The proper interrupt mask needs to be enabled, and the VC3 Interrupt vector needs to be edited for proper interrupt functionality SysClk Source This parameter enables the user to select the source for System Clock (SysClk). The system clock can be generated by the IMO, which is accurate to 2.5 percent. If a more accurate system clock is required, the user has two options: an external system clock connected to P1[4] or an external crystal connected to P1[0] and P1[1], and set PLL_MODE to Enable. The drive mode of P1[4] must be „High Z‟ when using an external clock. For more information on Digital Clocks, refer to Chapter 25 in the Digital Clocks Technical Reference Manual. SysClk*2 Disable This parameter allows the user to enable or disable the internal system clock doubler. Disabling this parameter reduces the power consumption of the PSoC. Enabling the SysClck*2 allows users to clock a digital block at a rate equal to 48 MHz, if the SysClck is set to Internal 24 MHz. Note Devices that use USB must have this option enabled. Note The global bus can only be run at a rate of 12 MHz or The system clock is divided down by this parameter setting to generate the VC1 clock. The divisor value can be set from 1 to 16. Setting VC1 divisor to the highest possible value reduces power consumption. VC1 is used as a general purpose clock for digital and analog blocks less. For more information on Digital Clocks, refer to Chapter 24 in the Digital Clocks Technical Reference Manual. Analog Power VC2 = VC1/N The Analog Power parameter sets the power supplied to the analog references and determines if switched capacitor (SC) circuits are turned ON or OFF. The VC2 clock, is the VC1 clock divided by this parameter. The divide-by value can be set from 1 to 16. SC OFF/REFHI means the SC blocks are turned off and the analog references are set to High Power. Setting VC2 divisor to the highest possible value reduces power consumption. Setting VC1 divisor to a higher value and VC2 to a lower divisor value consumes less power than vice versa. SC blocks running at a high clock rate require high power. The reference power setting should be greater than or equal to the user module power settings for the project. For example, to generate a 1 MHz clock source, setting VC1 to 12 and VC2 to 2 saves more power than setting VC1 to 2 and VC2 to 12. The VC2 clock is also used as a general purpose clock for digital and analog blocks. January 20, 2009 A higher setting of this parameter enables SC blocks to run at higher clock rates. A good rule of thumb is to start designing with the analog reference power set to REFHI. Analog power set to „low‟ reduces the power consumption of the chip. Each user module using the reference and the op-amp associated with it adds slightly to the power consumed by the part. To Document No. 001-33759 Rev. *B 3 [+] Feedback AN2221 learn how much additional power is consumed, refer to AN2216, “Estimating Power Consumption.” For detailed information about the Analog Power, refer to AN2219,”Selecting PSoC Ground and Reference.” For more information on Analog References, refer to Chapter 29 in the Technical Reference Manual, “Analog References.” Ref Mux This parameter enables the user to change the analog ground and the input range of the analog blocks. For more information on Analog References, refer to Chapter 21 in the Technical Reference Manual, “Analog References.” A_Buff_Power This setting determines the power level of the analog output buffers. Setting the buffer power to “low” reduces power consumption but also reduces the drive capability of the pin. Setting the buffer to power “high” increases power consumption and improves drive capacity. Setting RefMux to Vdd/2 +/- Bandgap sets analog ground to Vdd/2, RefHi to Vdd/2 + Bandgap, and RefLo to Vdd/2 – Bandgap. If Vdd = 5V and Bandgap = 1.3V, this means that the allowed input range is from 1.2V to 3.8V. Switch Mode Pump (SMP) Setting RefMux to Vdd/2 +/- Vdd/2 enables ratiometric operation but the accuracy of the PSoC depends on the noise level on the supply lines. For more information on the PSoC Switch Mode Pump, refer to Chapter 31 in the Technical Reference Manual, “Switch Mode Pump(SMP).” A bandgap reference circuit is built into the part with Vbandgap = 1.3V. For more accurate measurements, an external reference can be connected to P2[4]. P2[6] can also be used as an external voltage for a more accurate value of REFHI and REFLO. Trip Voltage[LVD(SMP)] For detailed information about analog power, refer to AN2219. For more information on Analog References, refer to Chapter 21 in the Technical Reference Manual, “Analog References.” AGndBypass When AGND Bypass is set to Enabled, pin P2[4] is tristated. An external capacitor connected between P2[4] and VSS reduces the noise at the AGND input by approximately 18 dB. Typical values for the bypass capacitor are 0.01 uF and should not exceed 0.1 uF. For detailed information about noise levels and noise reduction, refer to AN2224, “Lower Noise Continuous Time Signal Processing with PSoC.” For more information on Analog References, refer to Chapter 21 in the Technical Reference Manual, “Analog References.” Op-Amp Bias This parameter changes the op-amp bias level. Set the op-amp bias to low when starting a design. Table 1 describes the properties of op-amp bias level options. Table 1. Op-amp Bias Levels Properties Bias Level Low Bias Less power consumption and high voltage swing. High Bias High frequency operation and faster slew rate. Lower output impedance. Typically used for filters where the center frequency or corner frequency is greater than 50 KHz January 20, 2009 This parameter turns ON and OFF the internal boost converter used to generate supply voltage from a low voltage battery and a few external components. This parameter sets the trip voltage for Low Voltage Detect (LVD) and SMP, respectively. LVD is triggered when the Vdd value falls below the value selected for this parameter. If the LVD value is selected as 4.64V, when Vdd falls below 4.64V, the LVD interrupt is triggered. The LVD interrupt vector in the vector table holds a „halt‟ instruction by default. If this interrupt is triggered, the only way to come out of „halt‟ is to reset the PSoC. The user can edit this halt and put in custom code when an LVD interrupt occurs. The SMP level denotes the target Vdd voltage by the system. If the Vdd level is below this value, the SMP begins operation. LVD Throttleback When enabled, this parameter automatically reduces the CPU speed when low voltage conditions are detected. The processor cannot be run at 24 MHz when the power supply falls below 4.75V. For more information on the PSoC Low Voltage Detect, refer to Chapter 32 in the Technical Reference Manual, “POR and LVD.” Watchdog Enable The WatchDog Timer (WDT) can be enabled or disabled in PSoC Designer using this parameter. The WDT is based on a counter that counts three sleep timer events. The WDT circuit is designed to assert a hardware reset on the device after the three sleep timer interrupts, unless the watchdog is periodically cleared in firmware. This reboots the system when CPU crashes. It can also restart the system from the CPU halt state. Once the WDT is enabled, it can only be disabled by an external reset (XRES) or a POR. A WDT reset leaves the WDT enabled. Therefore, if the WDT is used in an Document No. 001-33759 Rev. *B 4 [+] Feedback AN2221 application, all code (including initialization code) must be written as though the WDT is enabled. For more information on the PSoC WDT, refer to Chapter 12 in the Technical Reference Manual, “Sleep and WDT.” Summary This application note describes the Global Resource settings in PSoC Designer, which enable users to configure system level registers through an easy to use graphical user interface. This is a unique feature enabling rapid system level configuration. Appendix Table 2. Global Resource Parameter Registers Parameter Register Power Setting [Vcc/SysClk freq ] VLT_CR, CPU_SCR1 CPU_Clock OSC_CR0 32K_Select OSC_CR0 PLL_Mode OSC_CR0 Sleep_Timer OSC_CR0 VC1= SysClk/N OSC_CR1 VC2=VC1/N OSC_CR1 VC3 Source OSC_CR4 VC3 Divider OSC_CR3 SysClk Source OSC_CR2 SysClk*2 Disable OSC_CR2 Analog Power ARF_CR Ref Mux ARF_CR AGndBypass ARF_CR Op-Amp Bias ARF_CR A_Buff_Power ABF_CR0 Switch Mode Pump VLT_CR Trip Voltage [LVD(SMP)] VLT_CR LVD ThrottleBack VLT_CR Watchdog Enable CPU_SCR0 January 20, 2009 Document No. 001-33759 Rev. *B 5 [+] Feedback AN2221 About the Author Name: Mohana Koteeswaran Title: Staff Applications Engineer Contact: kot@cypress.com Document History ® Document Title: Design Aids – Global Resources in PSoC Designer™ Document Number: 001-33759 Revision ECN Orig. of Change Description of Change Submission Date ** *A 1499983 2641995 JVY TDU 09/24/07 01/21/09 *B 2919598 VVSK 04/20/10 New publication of existing application note. Added part CY8C21xxx and removed parts CY8C25xxx and CY8C26xxx Updated software version to PSoC Designer 5.0 Updated the “Global resources” figure to depict latest PSoC Designer settings, Changed parameter description flow according to modified figure In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. PSoC is a registered trademark of Cypress Semiconductor Corp. "Programmable System-on-Chip," PSoC Designer, and PSoC Express are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com/ © Cypress Semiconductor Corporation, 2007-2010. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress‟ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. January 20, 2009 Document No. 001-33759 Rev. *B 6 [+] Feedback