The Technion – Israel Institute of Technology
Faculty of Computer Science
Home work 5
VLSI circuit design
236354
Winter semester, 2008
Moore F.S.M.
Submission time – Wednesday, 10/4/2008, 23:59
Design the following Moore Final State Machine:
The input alphabet is ΣI = { 0,1,2,3,4,s }.
The output alphabet is ΣO = { 0,1,2,3,4 }.
The output is the sum of the input sequence, modulo 5, from the last appearance of s and not including
the current input symbol.
The encoding of ΣI and ΣO is of your choice. The timing of the input and output is also of your choice.
Hint: The choice of the encoding is important.
Restrictions:
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The output having the sum up to x, including x, should became valid at most 1.5 clock period
from the time that x is required to be valid, as depicted below.
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The system is built only from complimentary gates and synchronic transmission gates.
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The above semantic of s has to hold even when the system is in an invalid (including nonlogical) state. That is, s resets the system.
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The system is designed under the two-phase nonoverlapping clocking technique.
The clock is symmetrical.
Transition time of the clocks is 0.1ns, the gaps are 0.3ns.
In the simulation, make the pulse-generators of the clocks without resistance (This is due to the
large load of the clock signals), all the other inputs are supplied through 7KΩ resistors.
The load of any output should be 30E-15 F.
As a safety margin, it is required that outputs of closed T.G. should be in the extreme 10% interval
(i.e more than 4.5V or less than 0.5V)
The only measure of quality is a small, well justified clock period.
To submit:
1.
2.
3.
4.
5.
The encoding of the input and output alphabets
A clear printout of the system schematic.
A simulation that includes all the possible combinations of input and state. Make sure that
all of the combinations are clearly visible. (As in ex. 2)
If the simulation requires much time, use the ‘MOS 0’ model as described in the
hierarchical layout tutorial.
Your clock period, together with a substantial justification.
There is no need to simulate the initialization semantics of s when the machine is in an
invalid state.
Good luck!