MegaCore IP Library Release Notes 2013.12.05 RN-IP Subscribe Send Feedback These release notes cover versions 12.1, 13.0, 13.1, and 13.1 Arria 10 Edition of the Altera® MegaCore® IP Library. The topics in these release notes describe the revision history for each product in the MegaCore IP Library. These release notes use the following Altera trademarks: Arria® devices Avalon® interface Cyclone® devices HardCopy® devices MegaCore function MegaWizard™ Plug-In ModelSim® simulator Nios® II processor Quartus II software SignalTap® II logic analyzer Stratix® devices Related Information • Altera Knowledge Base • Altera Software Installation and Licensing Errata Errata are functional defects or errors, which may cause the product to deviate from published specifications. Documentation issues include errors, unclear descriptions, or omissions from current published specifications or product documents. From v11.1 onwards, for full information on errata and the versions affected by errata, refer to the Knowledge Base page of the Altera website. © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com 101 Innovation Drive, San Jose, CA 95134 ISO 9001:2008 Registered 2 RN-IP 2013.12.05 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY Revision History 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY Revision History Table 1: Product Revision History The table shows the revision history for the 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core. Version Date Description 13.1 November 2013 Verified in the Quartus II software v13.1 13.0 SP1 July 2013 Added the following new features: 13.0 May 2012 • Added registers for UNH-IOL testing. • Removed reset_ch_bitmask (0x41), reset_control and reset status (0x42) registers. • Updated definition of VMAXRULE parameter and updated ber_time default to accommodate this change. • Added seq_lt_timeout status bit (0xB0, bit[2]. 12.1 SP1 February 2013 Removed Enable SGMII bridge logic parameter. This logic is always enabled. 12.0 July 2011 Initial release. • Forward error correction (FEC) • Sync-E support • RX equalization Related Information • Altera Transceiver PHY IP Core User Guide • Errata for 1G/10GbE and Backplane Ethernet 10GBASE-KR PHY IP core in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 10-Gbps Ethernet (10GbE) MAC Revision History 3 10-Gbps Ethernet (10GbE) MAC Revision History Table 2: Product Revision History The table shows the revision history for the 10-Gbps Ethernet (10GbE) MAC MegaCore function. Version Date 13.1 November 2013 Description • Removed support for the following devices: • Arria GX • HardCopy IV GX • Stratix II GX • Removed 1G/10GbE MAC and 10M-10GbE MAC with IEEE 1588v2 design examples from the directory. • The 10GbE MAC with 10GBASE-R PHY and IEEE 1588v2 configuration supports only Arria V GT device with speed grade 3_H3. • Increased the width for path delay interface signals such as tx_path_delay_10g_ data (16 bits), tx_path_delay_1g_data (22 bits), rx_path_delay_10g_data (16 bits), and rx_path_delay_1g_data (22 bits) 13.0 May 2013 • Added device support for Arria SoC and Cyclone SoC. • Added new 10/100M/1G/10G Ethernet (10M-10GbE) option for Arria V GZ and Stratix V FPGA devices. • Added ToD synchronizer feature. • Changed the 1G/10GbE MAC with IEEE 1588v2 design example to 10M-10GbE MAC with IEEE 1588v2 design example. 12.1 November 2012 • Added 1G/10GbE option for Arria V GZ and Stratix V devices. • Added IEEE 1588v2 time synchronization option. • Added design examples for 10GbE MAC with IEEE 1588v2 and 1G/10GbE MAC with IEEE 1588v2. 12.0 July 2011 Preliminary support for Arria V GT devices. Related Information • 10-Gbps Ethernet (10GbE) MAC MegaCore Function User Guide • Errata for 10-Gbps Ethernet (10GbE) MAC MegaCore Function in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 4 RN-IP 2013.12.05 10GBASE-R PHY Revision History 10GBASE-R PHY Revision History Table 3: Product Revision History The table shows the revision history for the 10GBASE-R PHY IP core Version Date 13.1 November 2013 Verified in the Quartus II software v13.1 13.0 SP1 July 2013 Verified in the Quartus II software v13.0 SP1 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Added the following new features: July 2011 • • • • • • • 12.0 Description • Added support for IEEE 1588 Precision Time Protocol. • Added Arria V GZ support. • The RCLR_BER_COUNT (0x81, bit 3) and HI_BER (0x82, bit 1) register bits for Arria V GZ and Stratix V devices. Added Arria V device support. Added the following QSF settings to all transceiver PHY: XCVR_TX_PRE_EMP_PRE_TAP_USER XCVR_TX_PRE_EMP_2ND_POST_TAP_USER Added 11 new settings for GT transceivers. Added optional pll_locked status signal for Arria V and Stratix V devices. Added optional rx_coreclkin port. Related Information • Altera Transceiver PHY IP Core User Guide • Errata for 10GBASE-R PHY in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Revision History 5 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function Revision History Table 4: Product Revision History The table shows the revision history for the 40- and 100-Gbps Ethernet MAC and PHY MegaCore function. Version Date Description 13.1 November 2013 • Added 40GBASE-KR4 option with FEC and with auto-negotiation and link training mode options. • Added Synchronous Ethernet clock support option in Stratix V devices. The option separates the TX PLL and RX CDR input reference clocks (tx_ref_clk and rx_ ref_clk signals replace ref_clk for these variations) and exposes the RX recovered clock. • Exposed link fault signals remote_fault_status and local_fault_status in duplex variations. • Exposed PHY status signals tx_lanes_stable and lanes_deskewed in MAC&PHY variations. • Updated and simplified the example design and testbench. The testbench stimulus is simpler and the user no longer needs to configure the DUT with a specific name and clock rate. 13.0 May 2013 • Added preamble pass-through option. • Added transmitter average inter-packet gap (IPG) adjustment option. 12.1 November 2012 Verified with the Quartus II software v12.1. Related Information • 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function User Guide • Errata for 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function in the Knowledge Base 50G Interlaken MegaCore Function Revision History Table 5: Product Revision History The table shows the revision history for the 50G Interlaken MegaCore function. Version Date Description 13.1 December Arria 2013 10 Edition Added support for Arria 10 devices. 13.1 November 2013 Verified in the Quartus II software v13.1. 13.0 May 2013 Initial release. MegaCore IP Library Release Notes Send Feedback Altera Corporation 6 RN-IP 2013.12.05 100G Interlaken MegaCore Function Revision History Related Information • 50G Interlaken MegaCore Function User Guide • Errata for 50G Interlaken MegaCore Function in the Knowledge Base 100G Interlaken MegaCore Function Revision History Table 6: Product Revision History The table shows the revision history for the 100G Interlaken MegaCore function. Version Date Description 13.1 December Arria 2013 10 Edition Added support for Arria 10 devices. 13.1 • Added optional ECC feature on M20K blocks in Stratix V devices. • Added bit error injection testing feature to check CRC24 error detection. • Changed implementation of single segment mode: November 2013 • Changed parameter name from Received data format to Data format. • If you select Single segment mode, the IP core can no longer handle incoming dual segment traffic on the TX client data interface. • Added four new parameters to optionally include advanced error reporting and handling, Stratix V M20K block ECC feature, diagnostic features, and in-band flow control functionality. Excluding the features improves resource utilization. 13.0 May 2013 • • • • • Added dual segment mode. Added packet mode option in parameter editor. Improved error handling. Added PRBS capability. Added CRC-32 error injection capability. 12.1 November 2012 Initial release. Related Information • 100G Interlaken MegaCore Function User Guide • Errata for 100G Interlaken MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 Arria V Hard IP for PCI Express Revision History 7 Arria V Hard IP for PCI Express Revision History Table 7: Product Revision History The table shows the revision history for the Arria V Hard IP for PCI Express. Version Date Description 13.1 November 2013 Added support for Gen2 Configuration via Protocol (CvP) using an .ini file. Contact your sales representative for more information. 13.0 SP1 July 2013 Verified in the Quartus II software v13.0 SP1 13.0 May 2013 Added ×2 support 12.1 November 2012 Added the following new features: • Root Port support for Avalon-MM Hard IP for PCI Express. • Multiple MSI and MSI-X messages for the Avalon-MM Hard IP for PCI Express. • Revised example design including the Transceiver Reconfiguration Controller Qsys component and a driver for this component. Additional changes in the 12.1 release: • busy_xcvr_reconfig is no longer a top-level signal of the IP core. • You must include the Transceiver Reconfiguration Controller IP Core in your design to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. • When opening an existing 12.0 Qsys design using the Avalon-MM interface, all base address registers (BARs) will be disabled in 12.1. You should re-enable each used BAR before regenerating in 12.1. 12.0 July 2011 • • • • Added ×1, ×4, and ×8 Gen1 support for Endpoints using the Avalon-MM interface Added ×1 and ×4 Gen2 support for Endpoints using the Avalon-MM interface Added support for dynamic reconfiguration of transceiver settings Added support for VHDL simulation Related Information • Arria V Hard IP for PCI Express User Guide • Errata for Arria V Hard IP for PCI Express in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 8 RN-IP 2013.12.05 Arria V GZ Hard IP for PCI Express Revision History Arria V GZ Hard IP for PCI Express Revision History Table 8: Product Revision History The table shows the revision history for the Arria V GZ Hard IP for PCI Express. Version Date 13.1 November 2013 The following features have changed for 13.1: May 2013 Added the following new features: 13.0 Description • Support for a Avalon-MM 256-Bit Hard IP for PCI Express Gen3 ×8 with DMA is final. • Support for Gen2 CvP is removed. • Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions • Preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that can run at the Gen3 ×8 data rate. • Support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core, 12.1 November 2012 Added Gen3 PIPE simulation support. 12.0 July 2011 Initial release. Related Information • Arria V GZ Hard IP for PCI Express User Guide • Errata for Arria V GZ Hard IP for PCI Express in the Knowledge Base Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function Revision History Table 9: Product Revision History The table shows the revision history for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore function. Version Date 13.1 December Arria 2013 10 Edition Description Initial release. Related Information • Arria 10 Transceiver PHY User Guide • Errata for the Arria 10 1G/10GbE and 10GBASE-KR PHY MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 Arria 10 Hard IP for PCI Express MegaCore Function Revision History 9 Arria 10 Hard IP for PCI Express MegaCore Function Revision History Table 10: Product Revision History The table shows the revision history for the Arria 10 Hard IP for PCI Express MegaCore function. Version Date 13.1 December Arria 2013 10 Edition Description Initial release. Related Information • Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface • Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped Interface • Arria 10 Hard IP for PCI Express User Guide for the Avalon Memory-Mapped DMA Interface • Errata for the Arria 10 Hard IP for PCI Express MegaCore Function in the Knowledge Base ASI MegaCore Function Revision History Table 11: Product Revision History The table shows the revision history for the ASI MegaCore function. Version Date Description 13.1 November 2013 Verified in the Quartus II software v13.1. 13.0 May 2013 Verified in the Quartus II software v13.0. 12.1 November 2012 Verified in the Quartus II software v12.1. Attention: The ASI MegaCore function is scheduled for product obsolescence and discontinued support as described in PDN1306. Therefore, Altera does not recommend using this IP core in new designs. For more information about Altera's current IP offering, refer to Altera's Intellectual Property website. Related Information • Product Discontinuance Notification (PDN) 1306 Provides obsolescence schedule for the ASI MegaCore function. • Altera Intellectual Property website • ASI MegaCore Function User Guide • Errata for ASI MegaCore Function in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 10 RN-IP 2013.12.05 CIC MegaCore Function Product Revision History CIC MegaCore Function Product Revision History Table 12: Product Revision History The table shows the revision history for the CIC MegaCore function Version Date Description 13.1 November 2013 Removed support for the following devices: 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Verified in the Quartus II software v12.1 • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Related Information • CIC MegaCore Function User Guide • Errata for CIC MegaCore Function in the Knowledge Base CPRI MegaCore Function Revision History Table 13: Product Revision History The table shows the revision history for the CPRI MegaCore function. Version Date 13.1 November 2013 • Removed support for HardCopy IV GX device family. • Improved the demonstration testbench. • Improved resource utilization. 13.0 May 2013 • Added new parameter for user control of inclusion or exclusion of software interface to full control words. • Added new parameter for user control of inclusion or exclusion of round-trip delay calibration feature. • Reduced resource utilization in 28-nm devices. 12.1 SP1 February 2013 • Added support for CPRI line rate and autorate negotiation up to 9.8304 Gbps in Arria V GZ devices. • Added support for autorate negotiation up to 9.8304 Gbps in Arria V GT devices. Altera Corporation Description MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 Cyclone V Hard IP for PCI Express Revision History Version Date 12.1 November 2012 11 Description • Added support for CPRI line rates and autorate negotiation up to 3.072 Gbps in Cyclone V GX devices. • Added support for CPRI line rates and autorate negotiation up to 6.144 Gbps in Arria V GZ devices. • Added dynamic switching between slave and master operation modes. Support includes new field in CPRI_CONFIG register. • Added support for slave operation mode self-bringup with no connection to CPRI master, to support link synchronization testing in slave operation mode. • Added access to full control words through software interface at all CPRI line rates. Support includes modifications to the CPRI_CTRL_INDEX, CPRI_RX_CTRL, and CPRI_ TX_CTRL registers. Related Information • CPRI MegaCore Function User Guide • Errata for CPRI MegaCore Function in the Knowledge Base Cyclone V Hard IP for PCI Express Revision History Table 14: Product Revision History The table shows the revision history for the Cyclone V Hard IP for PCI Express MegaCore function Version Date Description 13.0SP1 July 2013 Verified in the Quartus II software v13.0 SP1. 13.0 May 2013 Added ×2 support. 12.1 November Added the following new features: 2012 • Root Port support for Avalon-MM Hard IP for PCI Express. • Multiple MSI and MSI-X messages for the Avalon-MM Hard IP for PCI Express. • Revised example design including the Transceiver Reconfiguration Controller Qsys component and a driver for this component. Additional changes in the 12.1 release: • busy_xcvr_reconfig is no longer a top-level signal of the IP core. • You must include the Transceiver Reconfiguration Controller IP Core in your design to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. • When opening an existing 12.0 Qsys design using the Avalon-MM interface, all base address registers (BARs) will be disabled in 12.1. You should re-enable each used BAR before regenerating in 12.1. MegaCore IP Library Release Notes Send Feedback Altera Corporation 12 RN-IP 2013.12.05 DisplayPort MegaCore Function Revision History Version Date 12.0 Description July 2011 • • • • Added ×1, ×4, and ×8 Gen1 support for Endpoints using the Avalon-MM interface Added ×1 and ×4 Gen2 support for Endpoints using the Avalon-MM interface Added support for dynamic reconfiguration of transceiver settings Added support for VHDL simulation Related Information • Cyclone V Hard IP for PCI Express User Guide • Errata for Cyclone V Hard IP for PCI Express in the Knowledge Base DisplayPort MegaCore Function Revision History Table 15: Product Revision History The table shows the revision history for the DisplayPort MegaCore function. Version Date 13.1 November 2013 Description • • • • • • Added support for Cyclone V devices. Added HBR2 support for Arria V devices. Added dual and quad pixel mode support. Added quad symbol (40-bit) transceiver data interface support. Added fast link training support. Enhanced hardware demonstration designs: • Arria V device hardware demonstration design now demonstrates HBR2 functionality. • Hardware demonstration designs now demonstrate fast link training. • Hardware demonstration designs are now available for the Arria V FPGA Starter Kit development board and the Cyclone V GT development board. • Updated register map and API functions. 13.0 May 2013 Initial release. Related Information • DisplayPort MegaCore Function User Guide • Errata for DisplayPort MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 DDR2 and DDR3 SDRAM Controller with UniPHY Revision History 13 DDR2 and DDR3 SDRAM Controller with UniPHY Revision History Table 16: Product Revision History The table shows the revision history for the DDR2 and DDR3 SDRAM Controller with UniPHY IP core. Version Date Description 13.1 November 2013 • Verified in the Quartus II software v13.1 • Removed support for HardCopy III and HardCopy IV devices 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 • Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer • Added Arria V GZ support for DDR2 and DDR3 • Added Ping Pong PHY for quarter-rate DDR3 designs on Stratix V and Arria V GZ devices • Added 933 MHz DDR3 support for selected Stratix V C1 and C2 devices • Added simulation and compilation support for soft interfaces on Arria V SoC devices for DDR2 and DDR3 • Added simulation support for HPS interfaces on Arria V SoC devices for DDR3 and LPDDR2 • Added simulation, compilation, and timing closure support for soft interfaces on • Cyclone V SoC devices, for DDR2 and DDR3 • Added simulation, compilation, and timing closure support for hard interfaces on • Cyclone V SoC devices, for DDR3 • Added simulation and compilation support for HPS interfaces on Cyclone V devices, for DDR2, DDR3, and LPDDR2 12.0 July 2011 • • • • • Added LPDDR2 support Added shadow register support Added new EMIF Toolkit Added compilation support for Arria V soft interfaces Added compilation support for Cyclone V soft and hard interfaces Related Information • External Memory Interface Handbook • Errata for DDR3 SDRAM Controller with UniPHY IP core in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 14 RN-IP 2013.12.05 DDR3 and DDR4 SDRAM Controller for Arria 10 EMIF IP Revision History DDR3 and DDR4 SDRAM Controller for Arria 10 EMIF IP Revision History Table 17: Product Revision History The table shows the revision history for the DDR3 and DDR4 SDRAM Controller for Arria 10 EMIF IP core. Version Date 13.1 December Arria 2013 10 Edition Description Initial release. Related Information • External Memory Interface Handbook • http://www.altera.com/support/kdb/kdb-browse.jsp?keyword=ddr2_uni_ki FFT Revision History Table 18: Product Revision History The table shows the revision history for the FFT MegaCore function Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices 13.0 May 2013 Updated bit-accurate model to work with both 32-bit and 64-bit versions of MATLAB software. 12.1 November 2012 Support for Arria V GZ devices. Related Information • FFT MegaCore Function User Guide • Errata for FFT MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 FIR Compiler Revision History 15 FIR Compiler Revision History Table 19: Product Revision History The table shows the revision history for the FIR Compiler. Version Date Description 13.1 November 2013 Removed support for the following devices: 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Added support for Arria V GZ devices. • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Attention: The FIR Compiler is scheduled for product obsolescence and discontinued support as described in PDN1306. Therefore, Altera does not recommend using this IP core in new designs. For more information about Altera's current IP offering, refer to Altera's Intellectual Property website. Related Information • Product Discontinuance Notification (PDN) 1306 Provides obsolescence schedule and replacement IP information for the FIR Compiler MegaCore function. • Altera Intellectual Property website • FIR Compiler User Guide • Errata for FIR Compiler in the Knowledge Base FIR II Compiler Revision History Table 20: Product Revision History The table shows the revision history for the FIR II Compiler. Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices MegaCore IP Library Release Notes Send Feedback Altera Corporation 16 RN-IP 2013.12.05 Interlaken MegaCore Function Revision History Version Date Description 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Added support for Arria V GZ devices. Related Information • FIR II Compiler User Guide • Errata for FIR Compiler II in the Knowledge Base Interlaken MegaCore Function Revision History Table 21: Product Revision History The table shows the revision history for the Interlaken MegaCore function. Version Date Description 13.1 November 2013 Verified in the Quartus II software v13.1. 13.0 May 2013 Verified in the Quartus II software v13.0. 12.1 November 2012 Verified in the Quartus II software v12.1. Related Information • Interlaken MegaCore Function User Guide • Errata for Interlaken MegaCore Function in the Knowledge Base Interlaken PHY IP Core Revision History Table 22: Product Revision History The table shows the revision history for the Interlaken PHY IP Core. Version Date 13.1 November 2013 Verified in the Quartus II software v13.1 13.0 SP1 July 2013 Verified in the Quartus II software v13.0 SP1 13.0 May 2013 Changed RX equalization registers from read only to read and write. Altera Corporation Description MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 IP Compiler for PCI Express Revision History 17 Version Date Description 12.1 November 2012 • Added Arria V GZ support. • Added 12500 Mbps lane rate. • Removed recommendation to use /40 for tx_user_clkout and rx_coreclkin. Data rates between /40 and /67 all work reliably. 12.0 July 2011 • • • • • Added support for custom, user-defined, data rates. Added the following QSF settings for all transceivers: XCVR_TX_PRE_EMP_2ND_POST_TAP_USER XCVR_TX_PRE_EMP_PRE_TAP_USER Added 11 new settings for GT transceivers. Related Information • Altera Transceiver PHY IP Core User Guide • Errata for Interlaken PHY IP Core in the Knowledge Base IP Compiler for PCI Express Revision History Table 23: Product Revision History The table shows the revision history for the IP Compiler for PCI Express. Version Date Description 13.1 November 2013 Removed support for the Arria GX, Cyclone II, HardCopy II, HardCopy III, HardCopy IV, Stratix II, and Stratix II GX device families. 13.0 May 2013 Removed support for the SOPC Builder design flow. 12.1 November 2012 Verified in the Quartus II software v12.1. Related Information • IP Compiler for PCI Express User Guide • Errata for IP Compiler for PCI Express in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 18 RN-IP 2013.12.05 Low Latency 10-Gbps Ethernet (10GbE) MAC Revision History Low Latency 10-Gbps Ethernet (10GbE) MAC Revision History Table 24: Product Revision History The table shows the revision history for the Low Latency 10-Gbps Ethernet (10GbE) MAC MegaCore function. Version Date 13.1 December Arria 2013 10 Edition 13.1 Description Added support for Arria 10 devices. November • Initial release. 2013 • Lowest latency 10G Ethernet MAC with 32-bit user interface mode. • Final support for Arria V GZ and Stratix V devices. Related Information • Low Latency Ethernet 10G MAC MegaCore Function User Guide • Errata for Low Latency Ethernet 10G MAC MegaCore Function in the Knowledge Base Nios II Processor Revision History Table 25: Product Revision History The table shows the revision history for the Nios II processor. Version Date 13.1 November 2013 Description • • • • • Enhanced floating point custom instruction support Added ECC support Added RTL Nios II processor trace simulation support Verified in the Quartus II software v13.1 Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX 13.0 May 2013 • Verified in the Quartus II software v13.0 • Removed support for SOPC Builder 12.1 November 2012 Verified in the Quartus II software v12.1 12.0 July 2011 Verified in the Quartus II software v12.0 Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 Enhanced Floating Point Custom Instruction Support 19 Related Information • Nios II Processor Reference Handbook • Nios II Embedded Design Suite Release Notes • Errata for Nios II processor in the Knowledge Base Enhanced Floating Point Custom Instruction Support In v13.1, Qsys adds an option to select a new floating point custom instruction set component, Floating Point Hardware 2. The component consists of the following custom instructions: • One combinatorial custom instruction—implements comparison, minimum, maximum, negate, and absolute operations • One multi-cycle custom instruction—implements add, subtract, multiply, divide, square root, and conversion operations These custom instructions are binary compatible with the original Nios II floating point custom instructions. They offer better performance, with fewer cycles per operation. Note: Floating point calculation results made with the Floating Point Hardware 2 custom instructions may differ slightly from those calculated by the original custom instructions, because the new instructions use a different rounding algorithm to increase performance. Floating Point Hardware 2 appears in the Embedded Processor section in Qsys. The Floating Point Hardware 2 instructions are available in VHDL only. They are IEEE 754-2008 compliant with the following exceptions: • • • • • Simplified rounding. Simplified NaN handling. No exceptions generated. Exception conditions are indicated by a specific result, such as NaN. No status flags. Subnormal supported only on a subset of operations. To take advantage of software support for the Floating Point Hardware 2 instructions, include altera_nios_custom_instr_floating_point_2.h, which forces GCC to call newlib math functions (rather than GCC built-in math functions). Altera recommends that you recompile newlib with for optimum performance. Note: Do not use the –mcustom -fpu-cfg command-line option for GCC. This option does not support the Floating Point Hardware 2 instructions. The Nios II software build tools (SBT) add individual –mcustom commands to the makefile to support the Floating Point Hardware 2 custom instructions. ECC Support Starting in v13.1, the Nios II Processor parameter editor lets you enable ECC protection for the RAMs in the processor core and the instruction cache. Single-bit soft errors are corrected, and dual-bit soft errors cause either an instruction cache flush or processor exception. ECC support is only available on the Nios II/f core without the data cache. When ECC protection is selected, an Avalon-ST source is added to the processor core to provide ECC status information to external logic. By default, ECC is not enabled on reset. Therefore, software must enable ECC protection. Software can also inject ECC errors into RAM data bits to support testing of the ECC exception handler and event bus. MegaCore IP Library Release Notes Send Feedback Altera Corporation 20 RN-IP 2013.12.05 RTL Nios II Processor Trace Simulation Support The Nios II Hardware Abstraction Layer (HAL) is extended to support ECC initialization and exception handling. Note: ECC is not supported with the data cache. RTL Nios II Processor Trace Simulation Support Starting in v13.1, the Nios II processor adds RTL trace simulation support. This feature enables Nios II processor instruction execution to be recorded during RTL simulation in ModelSim™. Events are recorded and time-stamped during RTL simulation. Examples of recorded events: • • • • • • • • Instruction execution Instruction address Data address Data value Interrupts Exceptions Resets Control register changes The time stamp lets you align hardware simulation data with software execution. This feature is enabled by selecting the appropriate option in the Nios II processor parameter editor. When trace simulation support is enabled, Qsys adds RTL to the Nios II testbench to support the generation of a trace (*.tr) file. The *.tr file can be converted to human readable format with the nios2-display-rtl conversion tool. NCO Revision History Table 26: Product Revision History The table shows the revision history for the NCO MegaCore function Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Verified in the Quartus II software v12.1 Related Information • NCO MegaCore Function User Guide • Errata for NCO MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 PCI Compiler Revision History 21 PCI Compiler Revision History Table 27: Product Revision History The table shows the revision history for the PCI Compiler MegaCore function Version Date 13.1 November 2013 Description • Removed support for the following devices: • • • • Arria GX Cyclone and Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix GX, Stratix II, and Stratix II GX • Removed support for pci_mt64 and pci_t64 variations. 13.0 July 2013 Verified in the Quartus II software v13.0. 12.1 November 2012 Verified in the Quartus II software v12.1. Related Information • PCI Compiler MegaCore Function User Guide • Errata for PCI Compiler MegaCore Function in the Knowledge Base POS-PHY Level 4 Revision History Table 28: Product Revision History The table shows the revision history for the POS-PHY Level 4 MegaCore function Version Date Description 13.1 November 2013 Removed support for the following devices: 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Verified in the Quartus II software v12.1 • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Related Information • POS-PHY Level 4 MegaCore Function User Guide • Errata for POS-PHY4 MegaCore Function in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 22 RN-IP 2013.12.05 QDR II and QDR II+ SRAM Controller with UniPHY Revision History QDR II and QDR II+ SRAM Controller with UniPHY Revision History Table 29: Product Revision History The table shows the revision history for the QDR II and QDR II+ SRAM Controller with UniPHY. Version Date Description 13.1 November 2013 • Verified in the Quartus II software v13.1 • Removed support for HardCopy III and HardCopy IV devices 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 • Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer • Added simulation and compilation support for soft interfaces on Arria V SoC devices 12.0 July 2011 Added new EMIF Toolkit Related Information • External Memory Interfaces Handbook • Errata for QDR II and QDR II+ SRAM Controller with UniPHY in the Knowledge Base RapidIO MegaCore Function Revision History Table 30: Product Revision History The table shows the revision history for the RapidIO MegaCore function. Version Date Description 13.1 November 2013 Removed support for the Arria GX, Cyclone II, HardCopy II, HardCopy III, HardCopy IV E, HardCopy IV GX, Stratix II, and Stratix II GX device families. 13.0 May 2013 • Added 2x mode for Arria V, Cyclone V, and Stratix V devices. • Removed support for SOPC Builder design flow. 12.1 November 2012 Added support for Arria V GZ, Arria V SoC, and Cyclone V SoC devices. 12.0 July 2011 Added support for Cyclone V GT x1 variation at 5.0 Gbaud. Related Information • RapidIO MegaCore Function User Guide • Errata for RapidIO MegaCore Function in the Knowledge Base Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 RapidIO II MegaCore Function Revision History 23 RapidIO II MegaCore Function Revision History Table 31: Product Revision History The table shows the revision history for the RapidIO II MegaCore function. Version Date Description 13.1 November 2013 Verified in the Quartus II software v13.1. 13.0 May 2013 Verified in the Quartus II software v13.0. 12.1 SP1 February 2013 • Added device programming support for Arria V devices. • Added support for Arria V GZ devices. • Added support for Cyclone V devices. Cyclone V GT devices support rates up to 5.0 Gbaud, and other Cyclone V devices support rates up to 3.125 Gbaud. 12.1 November 2012 Initial release. Related Information • RapidIO II MegaCore Function User Guide • Errata for RapidIO II MegaCore Function in the Knowledge Base Reed-Solomon Revision History Table 32: Product Revision History The table shows the revision history for the Reed-Solomon MegaCore function Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Support for Arria V GZ devices. Related Information • Reed-Solomon MegaCore Function User Guide MegaCore IP Library Release Notes Send Feedback Altera Corporation 24 RN-IP 2013.12.05 Reed-Solomon II Revision History • Errata for Reed-Solomon MegaCore Function in the Knowledge Base Reed-Solomon II Revision History Table 33: Product Revision History The table shows the revision history for the Reed-Solomon II MegaCore function Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices Added support for erasures-supporting decoders 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Support for Arria V GZ devices. Related Information • Reed-Solomon II MegaCore Function User Guide • Errata for Reed-Solomon II MegaCore Function in the Knowledge Base RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core Revision History Table 34: Product Revision History The table shows the revision history for the RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP Core Version Date 13.1 November 2013 • Verified in the Quartus II software v13.1 • Removed support for HardCopy III and HardCopy IV devices 13.0 May 2013 Verified in the Quartus II software v13.0 Altera Corporation Description MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 SDI Revision History Version Date 12.1 November 2012 • Added RLDRAM 3 PHY-Only IP • Added EMIF On-Chip Debug Toolkit for 28 nm families with Nios II-based sequencer • Added simulation and compilation support for soft interfaces on Arria V SoC devices for RLDRAM II 12.0 July 2011 Added new EMIF toolkit. 25 Description Related Information • External Memory Interface Handbook • Errata for RLDRAM II Controller with UniPHY and RLDRAM 3 PHY-Only IP in the Knowledge Base SDI Revision History Table 35: Product Revision History The table shows the revision history for the SDI MegaCore function Version Date 13.1 November 2013 Description • Removed support for the following devices: • • • • Arria GX Cyclone and Cyclone II HardCopy III and HardCopy IV Stratix, Stratix GX, Stratix II, and Stratix II GX • Added video format detection support for SDI Rx protocol only option. 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Verified in the Quartus II software v12.1 12.0 July 2011 Preliminary support for multiple-rate SDI in Arria V devices. Related Information • SDI MegaCore Function User Guide • Errata for SDI MegaCore Function in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 26 RN-IP 2013.12.05 SDI II Revision History SDI II Revision History Table 36: Product Revision History The table shows the revision history for the SDI II MegaCore function Version Date Description 13.1 November 2013 • Added support for segmented frame video format. • Added option for easier HD single-rate only reference clock selection. • Added ATX and CMU PLL selections for Arria V GZ and Stratix V devices. 13.0 SP1 July 2013 • Added Tx PLL dynamic switching feature. • Added SD Interface Bit Width parameter. 13.0 May 2013 • Preliminary support for Cyclone V devices. • Added 20-bit interface for SD-SDI standard. • Added RP168 switching feature. 12.1 November 2012 November 2012 Preliminary support for Arria V and Stratix V devices. Related Information • SDI II MegaCore Function User Guide • Errata for SDI II MegaCore Function in the Knowledge Base SerialLite II Revision History Table 37: Product Revision History The table shows the revision history for the SerialLite I MegaCore function Version Date 13.1 November 2013 Description • Removed support for the following devices: • Arria GX • HardCopy IV • Stratix GX and Stratix II GX • OpenCore Plus feature will not be supported for Arria V, Arria V GX, Cyclone V, and Stratix V devices. 13.0 May 2013 Added support for Arria V GZ and Cyclone V devices. 12.1 November 2012 Verified in the Quartus II software v12.1 Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 SerialLite III Streaming Revision History 27 Related Information • SerialLite I MegaCore Function User Guide • Errata for SerialLite II MegaCore Function in the Knowledge Base SerialLite III Streaming Revision History Table 38: Product Revision History The table shows the revision history for the SerialLite III Streaming MegaCore function Version Date 13.1 November 2013 Added support for CRC-32 error injection. May 2013 Initial release. 13.0 Description Added support for FIFO ECC protection. Related Information • SerialLite III Streaming MegaCore Function User Guide • Errata for SerialLite III Streaming MegaCore Function in the Knowledge Base Stratix V Hard IP for PCI Express Revision History Table 39: Product Revision History The table shows the revision history for the Stratix V Hard IP for PCI Express. Version Date 13.1 November 2013 The following features have changed for 13.1: May 2013 Added the following new features: 13.0 Description • Support for a Avalon-MM 256-Bit Hard IP for PCI Express Gen3 ×8 with DMA is final. • Support for Gen2 CvP is removed. • Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions • Preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate. • Support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core, 12.1 SP1 February 2013 MegaCore IP Library Release Notes Send Feedback Added Gen3 PIPE simulation support. Altera Corporation 28 RN-IP 2013.12.05 Triple Speed Ethernet Revision History Version Date 12.1 November 2012 Description Added the following new features: • • • • Root Port support for Avalon-MM Hard IP for PCI Express. Native ×2 support. Multiple MSI and MSI-X messages for the Avalon-MM Hard IP for PCI Express. Revised example design including the Transceiver Reconfiguration Controller Qsys component and a driver for this component. Additional changes in the 12.1 release: • busy_xcvr_reconfig is no longer a top-level signal of the IP core. • rxfc_cplbuf_ovf is a new optional status signal. • You must include the Transceiver Reconfiguration Controller IP Core in your design to compensate for variations due to process, voltage, and temperature (PVT) in 28-nm devices. • When opening an existing 12.0 Qsys design using the Avalon-MM interface, all base address registers (BARs) will be disabled in 12.1. You should re-enable each used BAR before regenerating in 12.1. 12.0 July 2011 Added the following new features: • • • • • Avalon-MM single dword variant. Programmer Object File (.pof) support for Stratix V devices. Gen3 ×1 and ×4 support for Avalon-MM Endpoints. C4 speed grade for all variants except Gen3 ×8 and Gen3 ×4 with 128-bit interface. C1 speed grade is available for all variants. Related Information • Stratix V Hard IP for PCI Express User Guide • Errata for Stratix V Hard IP for PCI Express in the Knowledge Base Triple Speed Ethernet Revision History Table 40: Product Revision History The table shows the revision history for the Triple Speed Ethernet MegaCore function Version Date 13.1 December Arria 2013 10 Edition Altera Corporation Description Added support for Arria 10 devices. MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 Triple Speed Ethernet Revision History Version Date 13.1 November 2013 29 Description • Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix II and Stratix II GX • Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V devices. • Added 1588v2 support for MAC-only variants. • Added ATX and CMU Tx PLL options for variations that include the PCS block targeting Arria V GZ and Stratix V devices. • Added SyncE support by separating Tx PLL and Rx PLL reference clock. • The period in nanosecond for csr registers: tx_period, rx_period, Period, and AdjustPeriod, was changed from bit 16 to 19 to bit 16 to 24. 13.0 SP1 July 2013 Added TX PLL clock network option for Arria V and Cyclone V devices. 13.0 May 2013 • • • • • 12.1 November 2011 Added IEEE 1588v2 time synchronization option. Added a new testbench flow. Created a unified model for Qsys and standalone flow. Enhanced the timing constraint files (.sdc). Enhanced the simulation model—generated using IEEE simulation encryption. Reorganized the core configuration and FIFO option parameters in the parameter editor. Related Information • Triple Speed Ethernet MegaCore Function User Guide • Errata for Triple Speed Ethernet MegaCore Function in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation 30 RN-IP 2013.12.05 Video and Image Processing Suite Revision History Video and Image Processing Suite Revision History Table 41: Product Revision History The table shows the revision history for the Video and Image Processing Suite. Version Date 13.1 November 2013 Description • Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX • Improved the Broadcast Deinterlacer video-over-film mode scene change. 13.0 May 2013 • Added two new MegaCore functions: Broadcast Deinterlacer and Clipper II. • Removed and discontinued support for the Scaler MegaCore function. 12.1 November 2012 • Rewritten Deinterlacer II MegaCore Function IP core’s High Quality mode with a new Sobel edge detection-based algorithm • Added figure of Deinterlacer II MegaCore Function HQ mode Zoneplate 12.0 and 12.1. 12.0 July 2011 • Added Avalon® Streaming (Avalon-ST) Video Monitor MegaCore Function. • Added Trace System MegaCore Function. Related Information • Video and Image Processing Suite User Guide • Errata for the Video and Image Processing Suite in the Knowledge Base Viterbi Compiler Revision History Table 42: Product Revision History The table shows the revision history for the Viterbi Compiler Version Date 13.1 November 2013 Description Removed support for the following devices: • • • • Arria GX Cyclone II HardCopy II, HardCopy III, and HardCopy IV Stratix, Stratix II, Stratix GX, and Stratix II GX Added full support for Arria V and Stratix V devices Altera Corporation MegaCore IP Library Release Notes Send Feedback RN-IP 2013.12.05 XAUI PHY Revision History Version Date 31 Description 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 Support for Arria V GZ devices Related Information • Viterbi Compiler User Guide • Errata for Viterbi Compiler in the Knowledge Base XAUI PHY Revision History Table 43: Product Revision History The table shows the revision history for the XAUI PHY IP Core. Version Date Description 13.1 November 2013 Verified in the Quartus II software v13.1 13.0 SP1 July 2013 Verified in the Quartus II software v13.0 SP1 13.0 May 2013 Verified in the Quartus II software v13.0 12.1 November 2012 • Added Arria V GZ support. • Added constraint for tx_digitalreset when TX PCS uses bonded clocks. 12.0 July 2011 • Added the following QSF settings to all transceiver PHY: • • XCVR_TX_PRE_EMP_PRE_TAP_USER • XCVR_TX_PRE_EMP_2ND_POST_TAP_USER • Added 11 new settings for GT transceivers. Related Information • Altera Transceiver PHY IP Core User Guide • Errata for XAUI PHY IP Core in the Knowledge Base MegaCore IP Library Release Notes Send Feedback Altera Corporation