Registers and Data Paths
Registers and Data Paths
• A data path consists of processing logic
and a collection of registers
• A control unit determines the sequence of
operations within the data path
The CPU Bus
Control Signals
Control
Unit
Data
Path
Status Signals
• Internal CPU bus for register transfers
Control
Inputs
• data path contains transparent registers
Data
Inputs
Control
Outputs
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Memory Access
• The CPU has two dedicated registers:
1. memory address register (MAR)
2. memory data register (MDR)
• the MAR serves the address bus
• the MDR serves the data bus
• READ and WRITE control lines signal
the desired operation to the memory
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Data
Outputs
• Not to be mixed up with memory bus!
• Each register has an input and/or an output connection to the CPU bus
• tri-state logic for input and output gating
• register transfers can be performed by
1. opening output gate of the source register (put data on bus)
2. opening input gate of the destination
register (get data from bus)
• only one register transfer at a time!
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Memory Access
How to Fetch an Instruction?
• memory acknowledges “operation completed”
to CPU using the MFC line:
Read / Write
CPU
MFC
Address Bus
Memory
MAR
Data Bus
MDR
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Sequence for instruction fetch:
1.
2.
3.
4.
5.
6.
7.
Transfer the PC value to MAR
enable READ operation
wait for MFC signal
transfer MDR value to IR
disable READ signal
increment PC
interpret IR
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How to Fetch an Instruction?
“increment PC” involves another sequence:
6. Clear Y for addition
7. set carry-in to 1
8. transfer the PC value to ALU,*
add, and store result in Z
9. transfer Z value to PC
*(one operand is Y, the other is on the bus!)
How to Fetch an Instruction?
1.
2.
3.
4.
5.
PCout, MARin
READon
MFCwait
MDRout, IRin
READoff
6.
7.
8.
9.
Yclear
Cset
PCout, ADD, Zin
Zout, PCin
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set_0
(increment PC)
• PC is on the bus ⇒ feed both into the
MAR register and into the ALU
• while memory access is pending, store incremented PC
1. PCout, MARin, READon,
Yclear, Cset, ADD, Zin
2. Zout, PCin, MFCwait
3. MDRout, IRin, READoff
4. continue . . .
349
Fetch Instruction from Memory
PC
(read instruction)
Optimizing Register Transfers
IR
Fetch Instruction from Memory
IR
PC
Y
350
Fetch Instruction from Memory
IR
PC
Y
Y
Instruction
c_in = 1
MAR
ALU
Address Bus
MAR
ALU
Address Bus
MAR
ALU
In Progress ...
PC + 1
Finished
PC + 1
MDR
Z
Data Bus
MDR
Z
Cycle #1
351
Data Bus
MDR
Z
Cycle #2
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Data Bus
Cycle #3
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ALU Operations
Execute ALU Operation
Execute ALU Operation
• 1st operand is loaded into Y
• 2nd operand is provided on the bus
• the result is stored in Z
Sequence:
IR
IR
SUB Rsrc, Rdst
Y
Y
4. Rsrcout, Yin
Rsrc
Rsrc
5. Rdstout, SUB, Zin
6. Zout, Rdstin
OP
ALU
Rdst
ALU
Rdst
Register File
Z
Register File
Z
Cycle #4
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355
Execute ALU Operation
IR
Multiple Buses
Register-direct subtraction needs six cycles:
Example ALU operation on dual-bus:
2. Zout, PCin, MFCwait
3. MDRout, IRin, READoff
Rsrc
4. Rsrcout, Yin
5. Rdstout, SUB, Zin
Rdst
Register File
356
Summary Subtraction Operation
1. PCout, MARin, READon,
Yclear, Cset, ADD, Zin
Y
ALU
Cycle #5
• one operand on bus A
• second operand on bus B
• result stored in second cycle
1. Rsrcout-A, Rdstout-B,
SUB, resultin
2. resultout-A, Rdstin-A
3 buses ⇒ ALU operation in a single cycle!
6. Zout, Rdstin
Z
Cycle #6
357
358
359
Indirect Addressing
Example:
Complete Instruction Processing
ADD Rsrc, (Rind)
Indexed storage:
MOVE Rsrc, d(Rind)
4. Rindout, MARin, READon
1. PCout, MARin, READon,
Yclear, Cset, ADD, Zin
5. Rsrcout, Yin, MFCwait
2. Zout, PCin, MFCwait
6. MDRout, Zin, ADD, READoff
3. MDRout, IRin, [READoff ]
7. Zout, MDRin, WRITEon, MFCwait
4. PCout, MARin, READon,
Yclear, Cset, ADD, Zin
8. WRITEoff
5. Zout, PCin, MFCwait
The destination address is stored in Rind
(Instruction)
(Extension Word)
6. MDRout, Yin, [READoff ]
7. Rindout, Cclear, ADD, Zin
8. Zout, MARin
(Effective Address)
9. Rsrcout, MDRin, WRITEon, MFCwait
10. [WRITEoff ]
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362