International Journal of Modern Engineering Research (IJMER)
www.ijmer.com
Vol.2, Issue.4, July-Aug. 2012 pp-2672-2675
ISSN: 2249-6645
Efficient High Speed Power Current Comparator in 180 nm
Sushil Kumar
School of Information and Communication Technology, Gautam Buddha University
Greater Noida, UP, INDIA
ABSTRACT: This research paper proposes a new kind of
CMOS based current comparator circuit technique for high
speed power applications. The proposed circuitry has been
simulated properly in 180 nm CMOS process technology
using Cadence Spectre simulator. The current comparator
circuit has impressed with current pulses ranging from mili
amperes to nano amperes. Also, its speed and power
consumption has been successfully simulated and
measured. While comparing with the earlier reported
circuits, the proposed circuit attains very high speed of
operation and acceptable power consumption. The power
consumption of the proposed current comparator is very
much lower than the other earlier proposed circuits for
micron range input currents.
Keywords:
CMOS, Current Comparator,
Spectre, Current Pulse, Speed and Power.
Cadence
power and speed issue of [1], it consumed more power and
took more response time than recently published
approaches. The designs in [5], [6], [7] had come up come
up with high speed circuits, but whenever compared to the
proposed one those consumed significantly more power and
slow in response. The author of the paper [3] had come up
with a new approach in the year 2010 of a low input
impedance current comparator using pulse width
modulation.The circuit in the paper [3] had pre occupied
with more number of MOS and capacitors than any of the
designs. In this paper, the results obtained by the proposed
design are being compared with the earlier proposed design
in published papers [5]and [7].
Proposed and conventional current circuit are
analyzed and simulated in section 2.2 and 2.3. All the
results are discussed and compared in section 2.4.
II CURRENT COMPARATOR ANALYSIS
I INTRODUCTION
Current mode operations have been considered as
an alternative in analog circuit designs as CMOS VLSI
devices are scaled down in size. Comparators are used in
data converters and other front end signal processing
applications. Voltage comparator encounters several
difficulties including operational frequency, input offset
voltage and power consumption. Current comparison has
been done by impressing the current pulse signal at the
input of the comparator and finding whether it is positive or
negative. The output voltage generated by the comparator is
used properly to indicate the result of operation.Circuit uses
source follower input stage and a CMOS inverter as a
positive feedback. First current comparator which is widely
accepted even now a days was proposed by [1]. The circuit
operation is limited by the requirement of minimum input
current 10 μA is a must to perform the comparison. The
comparator provides distorted output signal below this
value. An input current range up to 0.5 μA had been
demonstrated in offset free
currentcomparator [2]. This comparator has some
shortcomings which are , it requires more number of MOS
components and more power consumption.Afterwards,
Soowon Kim and Byungmoo Min had come up with a new
idea of current comparator [3]. It is having the requirement
of an extra current reference generator. The speed of the
operation of the circuit is very less when compared to
present proposed circuit. The authors had come up with a
current amplifier cum comparator in the year 2000, had the
response time of 50 nS for 5 μA input current, which
indicated delayed response very much while being
compared to the response time of the recent designs.
Altogether, a new current comparator had been
proposed by [4] which had one CMOS complementary
amplifier, two resistive load amplifiers and two CMOS
inverters. Although, the circuit given above resolved the
2.1
Current Comparator
The figure 1 shown below,shows the schematic
diagram of a conventional positive feedback current
comparator circuit in [5]. The positive feedback operates at
output nodes of the inverters M2/M5 and M3/M4
respectively. Transistors M0 and M6 are closed and
transistors M1 and M7 are open in the pre decision state.
The inverter M5/M2 begins to switch as the voltage on the
comparator node is affected by input current. As soon as
this slews to either rail, the transistors M0 or M6 are
switched open and then with a delay of about10 ns the
transistors M1 or M7 respectively are switched closed.
Now, the comparator node can significantly speed the
decision process, particularly at the low current inputs as
this latched feedback dumps enough charge on the
comparator. The one of the main drawbacks of this system
is that the input node slews from rail to rail and this can
slow the comparator operations.
Fig.1.Conventional Current Comparator [5]
`
DC and Transient analyses had been performed
using the Cadence Spectre simulator with 180 nm CMOS
technology. The transient response of the current
comparator(Min & Kim, 1998)is shown in figure 2, when
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2672 | Page
International Journal of Modern Engineering Research (IJMER)
www.ijmer.com
Vol.2, Issue.4, July-Aug. 2012 pp-2672-2675
ISSN: 2249-6645
the input current pulse is normally kept at 10 μA.In this
fashion, the current comparator (Min & Kim, 1998) is
subjected to input current pulse range from 10 μA and 400
μA and transient analysis had been performed for the same.
Basically, the current comparator performs the comparison
till 10 μA and below this range output voltage starts getting
distorted. Importantly, the transient analysis could be used
to confirm the operating range of the comparator.
The figure 5 given below shows the transient
response of the current comparator [7]whenever the input
current pulse is at 10 μA. The transient response analysis
had been performed and the current comparator [7]is
subjected to input current pulse ranges from 1 mA to 400
nA. The comparison operation is well performed by the
current comparator till 10 μA and below this range output
gets starting distorted. The calculated 50% propagation
delay of the circuit is 1.493 ns.
To compute the total power consumed by the
comparator [7], DC analysis had been performed. The
power consumption of the comparator [7] whenever the
input current is at 10 μA, is shown in figure 6. The
computed average power consumed by this comparator is
comes out to be 32.6 μW at 10 μA.
Fig.2.Transient Response of Conventional Current
CurrentComparator at 10 Μa
Thus, DC analysis was performed to calculate the
average power consumption of the given comparator [5].
Figure 3 Shows the power plot of the current comparator at
10 μA.
Fig.5.Transient Response of Current Comparator [7]at 10
μA
Fig.6.Current Comparator Power Plot [7] at 10 μA
Fig.3.Current Comparator Power Plot
2.3 Proposed Current Comparator Analysis
The given below figure 7 shows the schematic
diagram of the proposed current comparator. The circuit
contains parts such as power supply, standard current
mirror, CMOS inverter, Wilson current mirror and input
current pulse generator. To reduce the total power
consumed in the circuit, Wilson current mirror was used.
The current comparatorused the high output impedance of
the Wilson current mirror to amplify the small difference in
the input currents to large variations in output voltage.
2.2 Current Comparator[7]
Fig.4.Conventional Current Comparator [7]
Above shown figure 4 is the current comparator
circuit published in [7]. The author [7] had added two more
additional MOS transistors M8 and M9, when compared to
the earlier implemented circuit [5]. These MOS transistors
speed up the decision process in the circuit. Transistors M0
and M6 are closed and transistors M7, M8 and M1, M9 are
open in the pre decision state. The speed of operation of the
comparator [7] is well increased when compared.
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Fig.7. The Proposed Current Comparator
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International Journal of Modern Engineering Research (IJMER)
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Vol.2, Issue.4, July-Aug. 2012 pp-2672-2675
ISSN: 2249-6645
TheTransient response of the proposed current
comparartor for variation of input current pulse from – 10
μA to 10 μA is shown in given below figure 8. The
characteristics curves were plotted and the input current
pulse had been varied from 1 mA to 400 nA during the
Transient analysis. The current comparator had done a
successful comparison till 400 nA and below this value the
output gets starting distorted. The proposed circuit design
goes working till the range of 400 nA unlike the earlier
published papers [5], [7] works till the range of 10
μA.Thus, the input range is increased when compared to
[5]and [7].The proposed circuit has achieved 50%
propagation delay of 550 ps.
improved a lot when the circuited is subjected with the
input current below 100 μA. The proposed current
comparator consumes very less power than[7] from 100 μA
onwards.
TableI. Comparison among the Current Comparators – 50%
Propagation Delay (ps)
Input
Current
1 mA
100 mA
10 μA
1 μA
400 nA
Proposed
Current
Comparator
110
248
550
1564
2408
Current
Comparator
[6]
219
561
1964
Not Worked
Not Worked
Current
Comparator
[8]
229
577
1493
Not Worked
Not Worked
Table II. Comparison among the Current Comparators –
50% Power Dissipation (W)
Input
Current
Fig.8.Transient Response of the Proposed Current
Comparator at 10 μA
The total power consumption by the proposed
comparator had been performed by the DC analysis. The
power consumption by the comparator when the input
current is at 10 μA is shown in figure 9.The average power
consumption by the proposed comparator is 8.7 μW at 10
μA.
1 mA
100 mA
10 μA
1 μA
400 nA
Proposed
Current
Comparator
1.35 m
80 μ
8.8 μ
5.27 μ
21.4 μ
Current
Comparator
[6]
0.763 m
52.7 μ
61.4 μ
Not Worked
Not Worked
Current
Comparator
[8]
1.15 m
81.4 μ
32.6 μ
Not Worked
Not Worked
The figure 10 given below shows the delay time versus
input current graph. The graph vividly states that the
proposed current comparator attains better performance
than its counter parts [5]and [7].
Fig.9.Power Plot of the Proposed Current Comparator at 10
μA
2.4Current Comparators Comparison
The simulation characteristics and parameters of
the conventional and proposed current comparator are
compared and observations are explained in great detail.
It is observed from table I that when compared with the
current comparators [5]and [7], the proposed new current
comparator operates at very high speed. The proposed
current comparator operates well up to the input current of
400 nA, although the comparators [5]and [7]functions only
up to 10 μA.
It is also observed from table II that from 10 μA onwards
the power consumption of the new proposed current
comparator is very low when compared to the power
consumed by the either of the current comparators [5]and
[7]. The proposed comparator consumes a little extra power
than [5] and[7]But, the power consumption has been
Fig.10. DelayTime versus Input Current
The figure 11shows the power dissipation versus
input current graph. The proposed circuit dissipates little
extra power for large current inputs say 1 mA. From 100
μA onwards the proposed comparator dissipates lower
power than the earlier published paper [7]and from 61μA
onwards it dissipates lower power than both [5] and [7].
The circuit power dissipation is far better than its
counterparts as shown in table II below 100 μA.
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International Journal of Modern Engineering Research (IJMER)
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Vol.2, Issue.4, July-Aug. 2012 pp-2672-2675
ISSN: 2249-6645
REFERENCES
[1]
[2]
[3]
[4]
Fig.11.Power Dissipation versus Input Current
III.
CONCLUSION
The goal of this paper was to present a simple idea
of designing a new CMOS based current comparator
topology for high speed applications such as digital
switching circuits and data converters. The proposed
comparator operates at very high speed in figure 10 and 11,
when compared with the performance of the existing
current comparators [5] and [7]. Also, the proposed new
current comparator consumes very low power from 10 μA
onwards when compared to the comparators in [5]and [7].
[5]
[6]
[7]
[8]
[9]
Traff, H. (1992). Novel Approach to High Speed
CMOS Current Comparators. IEEE Proceedings
Electronic Letters, 28(3).
Lin, C. W., & Lin, S. F. (2010). Low Input
Impedance Current Comparator Using in PulseWidth Modulation. IEEE Proceedings - ICCE, 127130.
Banks, D., & Toumazou, C. (2008). Low-power
high- speed current comparator design. IEEE
Proceedings Electronic Letters, 44(3).
Wu, C. Y., Chen, C. C., Tsai, M. K., & Cho, C. C.
(1991). A 0.5uA Offset-Free Current Comparator
For High Precision Current Mode Signal Processing.
IEEE Proceedings – Circuits amd, 1829-1832.
Min, B. m., & Kim, w. S. (1998). High performance
CMOS current comparator using resistive feedback
network. IEEEProceedings-Electronic Letters, 34,
2074-2076.
Ziabakhsh, S., Rad, H. A., Rad, M. A., & Mortazavi,
M. (2009). The Design of a Low-Power High-Speed
Current Comparator in 0.35 um CMOS Technology.
IEEE Proceedings.
Chen, L., Shi, B., & Lu, C. (2000). A High
Speed/Power Ratio Continuous-Time CMOS Current
Comparator.
IEEE
Proceedings–Electronics,
Circuits and Systems, ICECS, 2, 883-886.
Kushwah, B. C., Soni, D., & Gamad, R. S. (2009).
New Design of CMOS Current Comparator. IEEE
Proceedings - ICETET, 125-129.
Palmisano, G., & Pennisi, S. (2000). Dynamic
Biasing for True Low-Voltage CMOS Class AB
Current-Mode Circuits. IEEE Transctions on
Circuits and Systems-II: Analog and Digital Signal
Processing, 47, 1569-1575.
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