Abstract : A tri-valued memory circuit based on two cascoded MOS-BJT-NDR devices is investigated. The MOS-BJT-NDR device is made of metal-oxide-semiconductor field-effect-transistor (MOS) and bipolar-junction-transistor (BJT) devices, but it can show the negative-differential-resistance (NDR) current-voltage characteristic by suitably arranging the MOS parameters. We demonstrate a tri-valued memory circuit using the two-peak
MOS-BJT-NDR circuit as the driver and a resistor as the load. The MOS-BJT-NDR devices and memory circuits are fabricated by the standard 0.35μm SiGe process.
KEYWORDS: memory circuit, MOS, BJT, negative-differential-resistance, SiGe process
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1. Introduction
In the past few years, several novel applications based on the negative differential resistance (NDR) have been developed [1]-[3]. Due to their folding current-voltage (I-V) characteristics, the NDR devices have high potential as functional devices. Especially, the multiple-peak NDR devices offer much promise for multiple-valued memory circuits [4]-[7].
Most of the previously published NDR-based memory circuits are usually utilized the resonant tunneling diode (RTD) as the basic element. The fabrication of such RTD devices and circuits is based on the molecular-beam-epitaxy (MBE) or metal-organic-chemical-vapor-deposition (MOCVD) technique of III-V compound semiconductors, which are not compatible with main stream Si-based CMOS or SiGe-based
BiCMOS process. Also, the fabrication of these RTD devices is more complicated and expensive.
Recently, the Si/SiGe-based resonant interband tunneling diodes (RITD) have been successfully developed and applied is some applications [8]-[9]. However the fabrication of these devices and circuits is utilized the MBE system, which is still not suitable for the standard CMOS or BiCMOS process. Therefore, we proposed a new MOS-BJT-NDR device that is composed of three metal-oxide-semiconductor field-effect-transistor (MOS) devices and one bipolar-junction-transistor (BJT) device. We can obtain the NDR I-V curve by suitably arranging the MOS parameters. Because this NDR device is fully consisted of the
MOS and BJT devices, yet it is much more convenient to combine with other devices and circuits to achieve the system-on-a-chip (SoC) by the standard CMOS or BiCMOS process.
Numerous multiple-peak applications use two or more NDR devices in series to create the multiple-peak I-V characteristics. In this paper, we use two cascoded MOS-BJT-NDR devices to create the two-peak I-V characteristics. The two-peak MOS-BJT-NDR circuit can have three stable states at its positive differential resistance (PDR) segments during suitable
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load design. Using this two-peak MOS-BJT-NDR device with a resistor load, we demonstrate a tri-valued memory circuit by the standard 0.35μm SiGe process.
2. MOS-BJT-NDR Device
The NDR device used in this work is made of MOS and BJT devices. During suitably controlling the MOS parameters, we can obtain the NDR I-V characteristic. Therefore we call this NDR device as MOS-BJT-NDR device. Fig. 1(a) shows the circuit configuration of a
MOS-BJT-NDR device, which is composed of two NMOS, one BJT and one PMOS. The structure of the BJT is belonged to traditional NPN transistor or heterojunction bipolar transistor (HBT) by the standard Si-based CMOS or SiGe-based BiCMOS process, respectively. This circuit is derived from a Λ-type topology described in [10]. Fig. 1(b) shows the simulated N-type I-V curve with respect to the parameters designed as W
MN1
=30μm,
W
MN2
=60μm, W
MP1
=30μm, and Vgg=1.7V. The lengths of all MOS devices are fixed at
0.35μm. The BJT is used the standard ln02 cell based on the standard 0.35μm SiGe process provided by the TSMC foundry. The segment resistance of the I-V characteristic can be distinguished with three regions described as the first PDR region (R
P1
), the NDR region (R
N
), and the second PDR region (R
P2
) in order. The R
P1
, R
N
and R
P2
are also defined and shown in
Fig. 1(b).
The operation of this MOS-BJT-NDR device can be described as follows. The first PDR region describes a situation as MN1 is saturated, MN2 is cutoff, BJT1 is saturated, and MP1 is cutoff. The NDR region indicates the case as MN1 is saturated, MN2 is saturated, BJT1 is active, and MP1 is saturated. The second PDR region corresponds to the state as MN1 is saturated, MN2 is linear, BJT1 is cutoff, and MP1 is saturated. The electrical parameters shown in Fig. 1(b) are V
P
(peak voltage)=0.38V, I
P
(peak current)=0.98mA, V
V
(valley voltage)=0.72V, and I
V
(valley current)=0.016mA. If we replace the BJT1 with a MN3 device,
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yet it will be the type of MOS-NDR circuit [11]-[12]. Comparing to the MOS-NDR device, our novel MOS-BJT-NDR device possesses the smaller peak voltage and better peak-to-valley current ratio (PVCR). That is because of the smaller turn-on voltage and higher current gain of the HBT.
By modulating the parameters of the MOS-BJT-NDR device, we can obtain different
NDR I-V characteristics, as shown in Fig. 2. As shown, this kind of MOS-BJT-NDR device has a wide range of adjustable I-V characteristics. Referring to Fig. 2(a), we can obtain the
Λ-type I-V characteristic if the MP1 device is removed from the MOS-BJT-NDR circuit.
Therefore, the R
P2
value will be affected by the magnitude of the width of the MP1 device.
The wider MP1 widths, the smaller R
P2
values will be. We can obtain different I-V characteristics with respect to the relative parameters W
MN1
and W
MN2
, as shown in Fig. 2(b) and Fig. 2(c), respectively. Fig. 2(d) shows the magnitude of the voltage Vgg can be utilized to modulate the I
P
, which is the important parameter in some logic circuits design based on the monostable-bistable transition logic element [13]-[14].
3. Memory Circuit Design and Result
To demonstrate the tri-valued memory circuit, two stacked MOS-BJT-NDR devices are connected with a resistor, as shown in Fig. 3(a). We can obtain two peaks and valleys in the combined I-V characteristics. The magnitude of the first peak current I
P1
and second peak current I
P2
is different. The relative parameters are described as follows. For the NDR1 device, the widths of the MOS devices are W
MN1
=1μm, W
MN2
=10μm, W
MP1
=30μm, and Vgg=1.8V.
For the NDR2 device, the widths of the MOS devices are W
MN1
=10μm, W
MN2
=60μm,
W
MP1
=30μm, and Vgg=1.7V. The lengths of all MOS are fixed at 0.35μm. The two-peak
MOS-BJT-NDR pair operates as the driver and a 2.7kΩ resistor as the load. The fabrication of the memory circuit is based on the standard 0.35μm SiGe process. The load-line analysis of
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the circuit is shown in Fig. 3(b). The load line will intersect the PDR regions with three stable operation points from P1 to P3. The voltage to be stored is provided by enabling the V
PULSE
in sequence.
The initial operating point of the tri-valued memory is P1 by biasing V
PULSE
with a dc bias of 2.2V. The positive triggering pulse A is then fed to the resistor to momentarily lift the load line past the first peak current I
P1
and the operating point is moved to P2 at the trailing edge of the pulse. As seen, there is a transient state during the pulse A. If we apply a higher triggering pulse B, the load line can pass the second peak current I
P2
. Then the operating point will be moved from P2 to P3. Similarly, the negative pulse C will allow the load line passing the second valley current I
V2
and the operating point will shift from P3 to P2. Finally, we can obtain the operation point shifted from P2 to P1 with a lower negative pulse D. Fig. 4 shows the resulting waveform of the state transitions from V1 to V2, V2 to V3, V3 to V2, and V2 to
V1, effectively demonstrating the tri-valued memory operation. The memory states V1, V2, and V3 correspond to 0.5V, 1.2V, and 1.8V, respectively. Because the power difference between pulse B and initial load line is larger than that of pulse A, It will result in much more rising time from one stable state to another stable state. Therefore, the through rate at transition from V2 to V3 is found to be slower than that of V1 to V2. Similarly, the through rate at transition from V2 to V1 and is found to be slower than that of V3 to V2.
The average power consumption of the memory cell is about 2.24mW. However the lower power consumption can be reduced by decreasing the current or voltage value in the memory design.
The current noise margin is defined as the minimum value of the difference between the load current and peak current, and the difference between the load current and the valley current. The noise margin of V1, V2, and V3 states are estimated to be 0.1mA, 0.4mA, and 0.1mA, respectively. To obtain a higher noise margin, a larger load resistor should be used in the circuit, and it will result in increasing the bias. Furthermore, if we bias the
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two-peak MOS-BJT-NDR device by a constant current source as the load, it should further improve the noise margin up to half of the peak and valley current difference. But we should need more devices as the write and read component. No matter what kind of load is used, our novel MOS-BJT-NDR circuit will be useful in the multi-valued memory circuit design.
4. Conclusion
We have shown the two-peak I-V characteristics with two vertical integrated
MOS-BJT-NDR devices. This MOS-BJT-NDR device has better PVCR value and a wide range of adjustable I-V characteristics. Using the two-peak I-V characteristics with a resistor as a load, a tri-valued memory circuit is demonstrated and fabricated by the standard 0.35μm
SiGe process. Because all of the devices used in this circuit are fully composed of MOS and
BJT devices, this MOS-BJT-NDR memory circuit will be convenient to integrate with other
Si or SiGe-based devices and circuits to achieve the system on a chip.
Acknowledgment
The authors would like to thank the Chip Implementation Center (CIC) of Taiwan for their great effort and assistance in arranging the fabrication of this chip. This work was supported by the National Science Council of Republic of China under the contract no. NSC94-2215-
E-168-001.
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References
[1] S. Sen, F. Capasso, A. Y. Cho and D. Sivco: IEEE Trans. Electron Devices 34 (1987)
2185.
[2] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad: Proc. of the
IEEE 86 (1998) 664.
[3] R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C. L. Chen; L. J. Mahoney,
P. A. Maki and K. M. Molvar: Proc. of the IEEE 87 (1999) 596.
[4] S. J. Wei and H. C. Lin: IEEE J. Solid- State. Circ. 27 (1992) 212.
[5] A. C. Seabaugh, Y. C. Kao and H. T. Yuan: IEEE Electron Device Lett. 13 (1992) 479.
[6] M. H. Shieh and H. C. Lin: IEEE Trans. Circuits & Syst. I: Fundamental Theo. & Appl.
43 (1996) 583.
[7] J. P. A. Van Der Wagt, H. Tang, T. P. E. Broekaert, A. C. Seabaugh and Y. C. Kao: IEEE
Trans. Electron Devices 46 (1999) 55.
[8] N. Jin, S. Y. Chung, R. Yu, S.J. Di Giacomo, P.R. Berger and P.E. Thompson: IEEE
Trans. Electron Devices 52 (2005) 2129.
[9] N. Jin, S. Y. Chung, R M. Heyns, P. R. Berger, R. Yu, P.E. Thompson, S. L. Rommel:
IEEE Electron Device Lett. 25 (2004) 646.
[10] C. Y. Wu and K. N. Lai: IEEE J. Solid-State. Circ. 14 (1979) 1094.
[11] A.F. Gonzalez, M. Bhattacharya, S. Kulkarni and P. Mazumder: IEEE J. Solid- State.
Circ. 36 (2001) 924.
[12] K. J. Gan, C. C. Hsiao, S. Y. Wang, F. C. Chiang, C. S. Tsai, Y. H. Chen, S. H. Kuo, C.
P. Chen and D. S. Liang: Proc. fifth International workshop on system-on-chip for real-time applications (2005) 392.
[13] K. J. Chen, T. Akeyoshi and K. Maezawa: IEEE Electron Device Lett. 16 (1995) 70.
[14] K. Maezawa, H. Matsuzaki, K. Arai, T. Otsuji and M. Yamamoto: Electron. Lett. 33
(1997) 1733.
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Figure Captions
Fig. 1 (a) Circuit configuration of a MOS-BJT-NDR device. (b) The negative-differential-resistance I-V curve under suitable MOS parameters and Vgg values.
Fig. 2 The relative I-V characteristics by modulating the (a) widths of MP1, (b) widths of
MN1, (c)widths of MN2, and (d)values of Vgg; the lengths of all MOS are fixed at 0.35μm.
Fig. 3 (a) Configuration of a tri-valued memory circuit. (b) The load-line analysis with three stable operation points P1, P2, and P3.
Fig. 4 Oscilloscope capture of the resulting waveform with V
PULSE
and Vout showing tri-valued memory operation.
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Fig. 1
V gg
V
MN1 BJT1
MP1
MN2
S
(a)
(V
P
,I
P
)
W
W
MN1
=30
 m,W
MN2
=60
 m
MP1
=30
 m,Vgg=1.7V
R
P1
R
N
R
P2
(V
V
,I
V
)
Voltage (V)
(b)
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1
0.8
0.6
0.4
0.2
0
0
Fig. 2
1
0.8
0.6
0.4
0.2
0
0
1.2
modulating W
MP1
W
MP1
=90
 m
W
MP1
=60
 m
W
MP1
=30
 m without
MP1
0.8
0.4
modulating W
MN1
W
MN1
=60
 m
W
MN1
=30
 m
W
MN1
=10
 m
0.4
0.8
Voltage (V)
1.2
0
0 0.4
0.8
(a) (b)
2 modulating W
MN2
W
MN2
=100
 m
W
MN2
=60
 m
W
MN2
=20
 m
1.6
1.2
0.8
modulating Vgg
Vgg=2.0V
Vgg=1.8V
Vgg=1.7V
1.2
0.4
0.4
0.8
Voltage (V)
1.2
0
0 0.4
0.8
Voltage (V)
(c) (d)
1.2
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Fig. 3
V
PULSE
R
1.2
NDR1
NDR2
(a)
Vou t
0.8
0.4
0
0
D
P1
A
P2
C
1 2
Voltage (V)
(b)
P3
B
3
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Fig. 4
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