University of Portland
School of Engineering
5000 N. Willamette Blvd.
Portland, OR 97203-5798
Phone 503 943 7314
Fax 503 943 7316
Theory of Operations
Team Golden Mantle:
CMOS 8-Bit Analog-to-Digital Converter
Contributors:
Aaron Krizek
Travis Tompkins
Scott Ostrow
Approvals
Name
Date
Dr. Sig Lillevik – Instructor
Dr. Joe Hoffbeck – Primary Advisor
Mr. Howard Voorheis
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
.
Revision History
.
.
Rev.
Date
Author
.
0.9
02/04/05 .A. Krizek, T. Tompkins, S. Ostrow
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
UNIVERSITY OF PORTLAND
REV. 0.9
SCHOOL OF ENGINEERING
PAGE II
Reason for Changes
Rough Draft
TEAM GOLDEN MANTLE
.
.
.
.
.
Table of Contents
.
.
Summary.......................................................................................................................
1
.
.
Introduction ..................................................................................................................
2
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE III
Background .................................................................................................................. 3
Technologies ...........................................................................................................................................3
CMOS ...............................................................................................................................................3
MOSIS ..............................................................................................................................................3
B2Logic v.3.0.15 ...............................................................................................................................3
Tanner's L-Edit (UNIX and Windows) .............................................................................................3
B2Logic to L-Edit Translator (BLT) ..................................................................................................3
Architecture .................................................................................................................. 5
Design Overview.......................................................................................................... 7
System Block Diagram............................................................................................................................7
MOSIS Chip Design ................................................................................................................................7
Macro Model Design ...............................................................................................................................9
Wire Wrap Enclosure Implementation ...................................................................................................9
Signal Path ........................................................................................................................................... 10
Input Jack ............................................................................................................................... 10
AC/DC Select ......................................................................................................................... 10
Pre-Amp Block ....................................................................................................................... 11
Sample and Hold Block ......................................................................................................... 12
Comparator ............................................................................................................................ 13
Bidirectional Counter Block ................................................................................................... 13
DAC Block (Internal and External) ........................................................................................ 13
Timing Diagram..........................................................................................................14
Conclusions ...............................................................................................................16
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
List of Figures.
.
. of BLT system.............................................................................................4
Figure 1. Software architecture
.
. Block Diagram.................................................................................................5
Figure 2. System Functional
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE IV
Figure 3. Digital Output Using Tracking Architecture ...................................................................................6
Figure 4. System Component Diagram ........................................................................................................7
Figure 5. CMOS Integrated Circuit Physical Layout .....................................................................................8
Figure 6. Detail of Wire Wrap Socket ......................................................................................................... 10
Figure 7. 1st Stage Frequency Response ................................................................................................. 11
Figure 8. 2nd Stage Frequency Response ................................................................................................ 12
Figure 9. Functional Diagram of Sample and Hold Block ......................................................................... 12
Figure 10. DAC Voltage Mode Block Diagram .......................................................................................... 14
Figure 11. Count-up Sequence Timing Diagram....................................................................................... 15
Figure 12. B2Logic Timing Simulation Circuit ............................................................................................ 15
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
List of Tables .
.
. Parameters......................................................................................................8
Table 1. CMOS Technology
.
.
Table 2. Macro Model Components
..............................................................................................................9
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
PAGE V
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
1
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 1
Summary
This document outlines the theory of operation for Project Golden Mantle which is to
continuously convert an analog input signal into an 8-bit digital output signal. This will be
accomplished through the use of a tracking ADC architecture which uses a feedback loop
to continuously “track” the analog input by stepping the digital 256-bit output up or down,
one bit at a time. The complete design includes both digital and analog components, with
a semi-custom CMOS chip as its keystone. For demonstration purposes, the overall goal
is to take a microphone signal, convert it into a digital signal, and then convert it back into
an analog signal for speaker broadcast and signal verification.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
2
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 2
Introduction
The purpose of the Theory of Operations document is to provide a technical description of
the design for the 8-bit Analog to Digital Converter. It will serve as a reference for
maintenance and support as well as a starting point for future designs. Team Golden
Mantle is responsible for all aspects of the project including its design, implementation,
and documentation. This document is intended for any university faculty, student, or other
party interested in learning more about Project Golden Mantle and the technical aspects of
its design.
The rest of this document includes the following chapters:
Background- a brief description of information relevant to the project that will
help further the reader’s understanding of the project.
Architecture- explains the tracking architecture of the 8-bit analog to digital design.
Design Overview- explains the functionality of the design through layout,
functionality, and state diagrams.
Conclusion- provides an overview of this document highlighting significant points of
the project and any conclusions derived from this document.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
3
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 3
Background
Technologies
Below are descriptions of the different technologies used in the project’s design.
CMOS
In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P-type
transistors are used to realize logic functions. Today, CMOS technology is the dominant
semiconductor technology for microprocessors, memories and application specific integrated
circuits (ASICs). The main advantage of CMOS over NMOS and bipolar technology is the much
smaller power dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static
power dissipation. Power is only dissipated when the circuit actually switches. This properly allows
the integration of many more CMOS gates on an IC than in NMOS or bipolar technology, resulting
in much better performance.
MOSIS
MOSIS is a low-cost prototyping and small-volume production service for VLSI circuit development.
Since 1981, MOSIS has fabricated more than 50,000 circuit designs for commercial firms,
government agencies, and research and educational institutions around the world. Project Golden
Mantle has access to MOSIS chip technologies through a grant offered to the Engineering Dept at
the University of Portland.
B2Logic v.3.0.15
B2Logic software allows a user to build a model circuit and test it by probing signals at various
points. As the simulation progresses, the signal values change on the probes in the circuit, as well
as in a timing diagram and in a spreadsheet. You can change the input values by clicking directly
on the inputs in the circuit. Information regarding the layout of the circuit is written to a netlist text
file.
Tanner's L-Edit (UNIX and Windows)
L-Edit offers layout editing, verification, and place & route in one powerful suite of tools, so
designers can quickly and easily maneuver through the entire design flow. The .tpr file that L-Edit
uses is merely a reformatted version of the netlist text file, which represents the circuit.
B2Logic to L-Edit Translator (BLT)
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
. Figure 1. Software architecture of BLT system.
.
.
After a circuit is successfully designed and simulated in B Logic, one can save the circuit as a
.
.EDIF netlist file. This file uses an industry standard for text format. The netlist file is then input into
.
BLT through a command prompt, where it is parsed and reformatted into the proper .tpr file format.
. that L-Edit uses to automatically place and route the CMOS Chip.
This is the format
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE 4
2
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
4
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 5
Architecture
The circuit will be realized using the tracking ADC architecture. This architecture was chosen
due to known high performance in areas of speed and resolution. Also, a primary goal in this
project is to integrate most of the digital components on-chip.
The necessary analog
components will be implemented off-chip.
The tracking architecture utilizes a negative feedback loop to control the direction of an
up/down counter (see Figure 2. System Functional Block Diagram). The output of the
up/down counter is a binary number representing the analog voltage value of the input signal
at successive points in time. The counter is continuously clocked, and the up/down control line
is driven by the output of a comparator. When the analog input signal exceeds the DAC output
the counter goes into the "count up" mode, resulting in an increase in the value of the binary
output number. When the DAC output exceeds the analog input, the counter switches into the
"count down" mode. Thus, the DAC output counts in the proper direction to track the value of
the analog voltage input signal.
A sample output and tracking of an analog signal is presented in Figure 3: Digital Output Using
Tracking Architecture. A more detailed account of signal characteristics at various stages of
the circuit will be provided in the Signal Path section.
Figure 2. System Functional Block Diagram
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 6
Figure 3. Reconstructed Analog Output Using Digital Tracking Architecture
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
5
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 7
Design Overview
System Block Diagram
See “Updated Circuit Layout” (Visio file) attached with email. Plan on adding pin numbers
and unit numbers to file by next revision.
100k
AD790JN-ND
LF398N-ND
74F269SPC-ND
Comparator
AD557JN-ND
U/D Counter
25k
800pf
+
Sample
and Hold
Amp
(Unity Gain)
1k
U/D
Reset
D/A Converter
B1
Reset
8
B8
2.5 Vdc
296-1391-5-ND
10mf
-
Carry out
296-1391-5-ND
1k
B8
-
+
GND
ENB
ENB
Enable
Enable
1k
Vin
Vout
(Analog Output)
Vout
Vref
296-1391-5-ND
1k
B1
74F269SPC-ND
+
-2.5 Vdc
*All units equipped with decoupling capacitors
**Digi-Key parts listed in RED
Continuous
Binary Output
Up Counter
+
1k
Reset
U/D
B1
Reset
B8
CTX139-ND
1 MHz
296-1507-5-ND
8-bit Latch
A
Q1
H
Q8
8
Qout
(Latched Binary
Output)
Carry out
ON CHIP COMPONENTS
BACK-UP PARTS SHOWN
ENB
ENB
Enable
Enable
Figure 4. System Component Diagram (OUTDATED)
MOSIS Chip Design
The CMOS Chips was designed in two stages: logical design and physical layout. The
logical design stage was accomplished using B2Logic simulation software. The
functionality of the CMOS circuit was specified at the gate level in B2Logic. The translation
from the working logic level schematic to physical layout was accomplished using the BLT
automated translation program. The BLT program exports a device identification and
wiring netlist which is used by the L-EDIT® automated place-and-route algorithm to
produce the on-chip physical material layout.
The CMOS chip will be fabricated by MOSIS fabrication services. Fabrication will use the
AMI Semiconductor 1.5 micron ABN Process and the layers types shown in Table 1.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
.
.
.
Feature
.
Technology/Lambda
.
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Substrate Type
Layout Size
Bonding Pads
Packaging
Die Thickness (+/- .5 mil)
Layers
REV. 0.9
PAGE 8
Table 1. CMOS Technology Parameters
Value
SCNA Lambda = 0.8 micron
Epi
2200 x 2200 microns
40
DIP 40 pin
10 Mils
250 microns
N_WELL, ACTIVE, POLY,
N_PLUS_SELECT, P_PLUS_SELECT,
CONTACT, METAL1, VIA, METAL2,
GLASS, PADS.
Table 1. CMOS Technology Parameters provides detailed fabrication information about
the characteristics of the specific process utilized by MOSIS in fabrication.
Figure 5. CMOS Integrated Circuit Physical Layout
Figure 5 shows the physical layout of the CMOS integrated circuit generated by L-EDIT
using the netlist extracted from BLT translation program as described in chapter 3.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
.
Macro Model Design
.
.
The macro model
. circuit will be developed as a back-up to the MOSIS integrated circuit.
The macro .
model will contain identical functionality as the CMOS IC, but will be
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE 9
constructed using commercially available integrated circuits. The macro model of the
CMOS integrated circuit will be implemented on a “daughter board” that will allow easy
interchangeability between the macro model with the CMOS IC on the prototype board.
Table 2 lists the integrated circuits used to implement the CMOS IC circuit.
Table 2. Macro Model Components
Unit Name
Quantity
Part Number
8-Bit Bidirectional Binary Counter
2
74F269
Quad Latch
2
74LS75
The macro model “daughter board” will interface with the system prototype board via a
DIP 40 pin wire wrap socket. The prototype board will have a DIP 40 pin socket that can
accept an identical 40-pin socket from the detached board containing either the macro
model components or the CMOS IC. This will eliminate the need for re-wiring on the
prototype board, and allow cross-connects to be made between the CMOS IC and the 40pin socket directly on the detached board to accommodate manufacturer specified pin-out
configuration.
Wire Wrap Enclosure Implementation
The system prototype will be realized using a wire wrap process. Wire wrap is a
technique for component assembly that provides reliable pin connections and has the
flexibility not found in a PCB system. Due to the likelihood that errors will exist in the
prototype assembly it is necessary to allow for re-routing and additional components to be
added to the circuit, a necessity unavailable with a PCB. The wire wrap assembly
requires the use of IC sockets that accept DIP packages from the top and connect the pins
to conducting metal posts that are inserted through the perforated non-conducting board.
Connections between pins are made by wrapping the metal posts with 30-gage insulted
wire that has been stripped to allow contact. The conducting posts have square edges
that pierce any oxide layer present on the wire through the force of the wrapping tool
(electric or hand powered), ensuring adequate metal-to-metal contact.
Figure 6. Detail of Wire Wrap Socket shows the detail dimensions of a typical wire wrap
socket described above.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 10
Figure 6. Detail of Wire Wrap Socket
The wire wrap assembly lacks noise immunity as compared to a PCB, but exceeds the
noise immunity typical of bread board assemblies with virtually equal flexibility. Particular
concerns with wire wrap assembly include continuity of wire traces, integrity of post/wire
connections, selection of adequate gage wire, and proper power and ground bus
connections. Wire connections between pins will generally be made with 30-gage
insulated wire. Power and Ground busses will utilize 18-gage un-insulted wire to allow
adequate power and current flow.
Signal Path
This section will outline the characteristics of signals at various nodes in the overall circuit.
The analysis will follow the logical flow of a signal from the input through to the output
focusing on nodes between individual integrated circuit parts.
Input Jack
The system will accept an input signal by way of a panel mounted 2.5mm audio jack. As
stated in the functional specification the signal can range from 0-2Khz in frequency, and 1100mV peak amplitude.
AC/DC Select
In order to input a DC signal the AC/DC selector switch must be set to DC which bypasses
the filtering and amplification circuitry. If the selector switch is set to DC, the input signal
(ranging from 0-5V) will be applied directly to the input of the sample and hold amplifier.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
Pre-Amp Block
.
.
In the case of.a small signal AC input the selector switch must be set to AC which directs
the input signal
. to the input of the filtering and amplification block. The filtering and
amplification block, known collectively as the pre-amp block, is implemented with
.
operational amplifiers (op amps) and discrete resistors, capacitors, and a potentiometer.
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE 11
The pre-amp block includes a gain adjustment knob in order to amplify the input signal
amplitude to fill the entire 0-5V range. Variable gain is accomplished by adjustment of the
potentiometer shown in Figure 4. Desired operation is only accomplished when the gain is
tuned so the signal applied to the sample and hold amplifier occupies the full 0-5V
spectrum. The pre-amp block filters the input signal to a maximum frequency component
of 2Khz.
Figure 7 displays the frequency response of the first stage of the pre-amp block. Stage 1
provides fixed amplification and frequency filtering. A gain of Vout/Vin = 100 and a pass
band of 25-2000 Hz are fixed in this stage.
Figure 7. 1st Stage Frequency Response
Figure 8 displays an example of the stage 2 frequency response. This stage provides
variable gain controlled by the 100K potentiometer shown in the block diagram Figure 4.
In the frequency response in Figure 6.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 12
Figure 8. 2nd Stage Frequency Response
Stage 2 amplifies the signal from stage 1 to fill the entire 0-5V amplitude range. Stage 3
introduces a DC offset of 2.5V in a unity gain configuration which centers the AC signal
about the virtual 2.5V ground.
Sample and Hold Block
The sample and hold amplifier (S/H) function is implemented using an LF398 Monolithic
Sample and Hold circuit manufactured by National Semiconductor (Error! Reference
source not found.). The use of the S/H circuit ensures that the digital output of the
counter block (CMOS or macro model) is given sufficient time to settle upon the desired
accurate 8-bit binary number corresponding to the value of the analog input signal. The
S/H will momentarily latch (sample) and the analog input signal every 256 clock cycles
and assert (hold) that value to the input of the comparator.
Figure 9. Functional Diagram of Sample and Hold Block
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
.
.
.
.
Comparator.
. AD790 manufactured by Analog Devices, is an essential component to
The comparator,
.
the feedback .loop utilized in the circuit. The output of the comparator controls the direction
of counting in the bidirectional counter blocks. The comparator accepts two analog
.
signals as primary inputs, and asserts a digital logic high or low based upon the magnitude
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
REV. 0.9
PAGE 13
of the signals. The comparator accepts analog signal inputs from the S/H block, and from
the internal DAC output of the counter block. The S/H output is applied to the +input
terminal, while the DAC output is applied to the – input terminal. The DAC output is the
reconstructed analog value of the instantaneous digital output.
The output of the internal DAC is defined by the following relationship:
Vo = VI(D/256)
Where:
Vo = analog output voltage
VI = fixed input reference voltage
D = digital input code converted to decimal
Therefore, if the value asserted by the S/H block is greater than the DAC feedback value
Vo the comparator will instruct the bidirectional counter block to “count-up” until the
instantaneous digital output equals the asserted S/H block input. Conversely, if the value
asserted by the S/H block is less than the DAC feedback value Vo the comparator will
instruct the bidirectional counter block to “count-down” until the signals reach equilibrium.
Bidirectional Counter Block
The bidirectional counter block, referred to as U/D counter, is controlled by the output of
the comparator. The U/D counter accepts a single logic high or low digital input signal
from the output of the comparator. The output of the U/D counter is an 8-bit binary
number. The digital outputs are connected to the internal DAC input and an 8-bit latch
array. The U/D counter block includes two 8-bit bidirectional counters and an 8-bit latch.
One 8-bit counter will be operated as a divide-by-256 function as the clock signal driving
the sample and hold block, and on-chip latch array. Due to the size of discrete
components required to realize these functions this block will be implemented on the
CMOS integrated circuit.
As a safeguard against an error in design or faulty manufacturing the U/D counter block
will also be implemented using macro components. In fact, the system prototype will be
fully functional as detailed in the functional specification before the CMOS integrated
circuit is released for prototype integration.
DAC Block (Internal and External)
The DAC is implemented using a commercially available integrated circuit. The part is an
8-bit multiplying DAC TLC7524C manufactured by Texas Instruments. Although the
default output mode if current the TLC7524C operates in “voltage mode” in the
configuration seen in Figure 10:
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 14
Figure 10. DAC Voltage Mode Block Diagram
The output of the internal DAC is defined by the following relationship:
Vo = VI(D/256)
Where:
Vo = analog output voltage
VI = fixed input reference voltage
D = digital input code converted to decimal
Timing Diagram
The circuit was simulated using B2Logic software to produce a timing diagram of a typical
sequence of operation. The sequence chosen was a “count-up” to 4 hex from a clean
reset start-up. The sample and hold (S/H) and comparator (COMP) components seen in
Figure 12 simulate the functionality of the analog components to be used in the prototype.
The CMOS chip in the simulation in the same design sent for MOSIS fabrication.
Figure 11 shows a timing diagram of a “count-up” sequence. Prior to the rising edge of
the first clock the reset input is assert low to set the system to a known state. Next, the
input was asserted to 4 hex. A short time later the comparator output (Comparator)
asserts logic high to instruct the U/D counter block to begin counting up. The clock output
(Unlatch Out) increases by 1 every rising edge of the clock as long as the comparator
output is asserted high. When Unlatch Out reaches the value of the input signal
Comparator toggles to low. The U/D block continues to toggle between binary state 4 and
state 5 until a new input signal is asserted. The Unlatched Out value is grabbed by the
latch array after 256 rising edges of the system clock pass.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 15
Figure 11. Count-up Sequence Timing Diagram
Figure 12 is the circuit used to generate the timing diagram. An octal buffer with
propagation delay equal to the S/H delay (“S/H”) was used to simulate the S/H block. A
digital 8-bit comparator (“COMP”) was constructed to simulate the analog comparator with
propagation delay set to match the AD790 specified value. The logic schematic used by
BLT to generate the physical layout of the CMOS integrated circuit was inserted as a user
defined part and labeled as “CMOS”. Due to the unknown value of the propagation delay
through the CMOS circuit, delays for simulation purposes were set to typical.
Figure 12. B2Logic Timing Simulation Circuit
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE
THEORY OF OPERATIONS
PROJECT GOLDEN MANTLE
Chapter
6
.
.
.
.
.
.
.
.
.
REV. 0.9
PAGE 16
Conclusions
This document provides operation specifications for the 8-bit Analog-to-Digital
Converter (ADC) that will be implemented in this project. A tracking ADC architecture
was used to achieve this, as discussed in the Background section. Implementation,
material, and physical specifications were also discussed in this section. A keystone
component in the design is the semi-custom CMOS chip, to be manufactured by the
MOSIS® Corporation. Our demonstration goal is to successfully convert and
reconstruct an audio signal to be amplified and broadcast to the audience.
UNIVERSITY OF PORTLAND
SCHOOL OF ENGINEERING
TEAM GOLDEN MANTLE