Functional BIST with Improved Testability
R. Ubar, N.Mazurova, J.Smahtina
Computer Engineering Department, Tallinn Technical University
Raja 15, Tallinn, Estonia, raiub@pld.ttu.ee
Abstract: Binary
1. Introduction
Rapid advances in the areas of deep-submicron electron technology and design automation tools are
enabling engineers to design larger and more complex circuits and to integrate them into one single
chip. System on a Chip (SoC) design methodology is seen as a major new technology and the future
direction for semiconductor industry. The most important challenges of SoC testing are linked to test
cost and fault coverage. According to the ITRS (International Technology Roadmap for
Semiconductors) by 2014 it may cost more to test a transistor than to manufacture it unless techniques
like logic Built-in Self-Test BIST are employed [1]. BIST is a technology to move on board the main
functionalities previously carried out by Automated Test Equipments (ATE). In traditional BIST
architectures, test pattern generation is mostly performed by adhoc circuitry, typically Linear
Feedback Shift Registers (LFSR) [2], cellular automata [3] or multifunctional registers like BILBO
(Built-in Logic Block Observer) [4]. BIST involves using on-chip hardware to apply pseudorandom
test patterns to the Circuit Under Test (CUT) and to analyze its output response. The most widespread
approach is test-per-scan BIST scheme [4]. Unfortunately, many circuits contain random-patternresistant faults [5] which limit the fault coverage that can be achieved with this approach.
Established BIST solutions use special hardware for pattern generation (TPG) and test response
evaluation (TRE) on chip, but this in general introduces significant area overhead and performance
degradation.
To overcome these problems, recently new so called functional BIST methods have been proposed
which exploit specific functional units such as arithmetic units or processor cores for on-chip test
pattern generation and test response evaluation [6-10]. In particular, it has been shown that adders can
be used as TPGs for pseudo-random, pseudo-exhaustive and deterministic patterns. Investigations are
known about properties of test patterns generated by simple adders [8], ones- and twoscomplemented
subtractors [11], and more complex multipliers and MAC circuits [12]. All of them may generate
pseudo-exhaustive or pseudorandom patterns with a similar quality as LFSRs do, and may reach a
comparable fault coverage.
The term "functional BIST" (FBIST) describes a test method to control functional modules so that
they generate a deterministic test set, which targets structural faults within other parts of the system. It
is a promising solution for self-testing complex digital systems at reduced costs in terms of area
overhead and performance degradation.
In this paper we propose a functional BIST for using in microprogrammed data-paths of digital
systems. Differently from the known FBIST approaches the goal is not to generate by FBIST a
predetermined deterministic test set. The idea of the proposed approach consists in using for test
purposes the functional patterns produced by the microprogram itself. No additional external control
for FBIST is needed, which is the advantage of the proposed approach compared to the known FBIST
approaches. The generated functional test data play the same role as pseudorandom test patterns in
traditional BIST approaches. The disadvantage of the proposed approach is the same as of traditional
BIST approaches – low fault coverage because of the random-pattern-resistant faults.
One method for improving the fault coverage of BIST schemes is to modify the CUT by either
redesigning it to improve the fault coverage [13,14] or by inserting test points [15-16].
Fault coverage of traditional BIST can be improved by using weighted pseudorandom sequences [1719]. The disadvantage of the weighting approach is in the need of storing of the weight sets on chip
and also, control logic is required to switch between weights, so the hardware overhead may be large.
Another method to improve the fault coverage is to use a “mixed mode” approach where deterministic
patterns are used to detect the faults that the pseudorandom patterns miss. In [18] a technique based on
reseeding an LFSR was proposed that reduces the storage requirements. In [19] another improved
technique was developed that uses a multi-polynomial LFSR for encoding a set of deterministic test
cubes. More recently, a technique called bit flipping for generating deterministic test cubes using BIST
control logic was proposed in [20]. Further, in [21] a mixed-mode approach was presented in which
deterministic test cubes are embedded in the pseudorandom sequence of bits itself. The disadvantage
of the mixed-mode approaches is in the need of storing the deterministic data which may need a lot of
memory overhead.
In this paper we have chosen the test point insertion approach to keep the hardware overhead low and
to improve the fault coverage of functiona BIST.
The paper is organized as follows. First, in Section 2 a brief overview of the idea of hybrid functional
BIST is explained. Section 3 gives an overview of methods of selecting test points for improving
testability in CUTs. In Section 4 the proposed test point selection method is described to reach 100%
fault coverage in FBIST. In Section 5 we present the experimental results which demonstrate the
feasibility and efficiency of our approach, and in Section 6 we draw some conclusions and discuss
possible future work.
2. General Scheme of Hybrid Functional BIST
Consider a microprogrammed data-path for division of fractional numbers, presented in Fig.1. It
consists of a register block for storing the dividend, divisor, intermediate results of division, the
quotient, and the counter of cycles. All the microoperations needed in the division procedure are
carried out in the Arithmetic and Logic Unit (ALU) which has the role of CUT in this work. The ALU
has data inputs and outputs connected via buses to the register block. The control signals from the
control unit serve as additional inputs for ALU, and few status signals of the ALU serve as additional
output signals connected to the control unit.
During N cycles of the microprogram ALU is excercised with N functional patterns, and the responses
of ALU will be compressed in the signature analyzer which monitors the whole division process.
N cycles
Fault
simulator
K*N
Register
block
Functional
test
ALU
K*N >> K
Fault
coverage
Test patterns are produced
on-line during the working
mode of the system
Signature analyser
K
Data
Fig.1. Functional BIST in the microprogrammed divisor
Instead of using only two operands A and B involved in the division process as the single test pattern
for the divisor, and the quotient C = A/B as the single response to the stimuli A and B, in the FBIST
scheme we will use all the data produced on the inputs of ALU during the N cycles of the division as
input test patterns, and all the data produced on the outputs of ALU during the N cycles as responses
to test patterns. In such a way, we have got a multiplication effect of N times in the number of test
patterns when moving the test access from the instruction level to the microinstruction level.
Denote by L the number of bits in the data operands (dividend and divisor), and by l the number of bits
on the inputs of ALU. Then the reduction in the test data volume through the compression of test data
in the described FBIST scheme is equal to
R
Nl
.
2L
For example (for the system used in the experiments), in the case of 32 bit words for the divisor with
105 inputs and 120 cycles the reduction in the volume of test data is 120*105/64 = 197.
In this scheme the functional patterns produced directly on the inputs of ALU have the similar role as
pseudorandom test patterns in classical BIST schemes. Similarly to the pseudorandom test, the
functional test patterns are not able to cover random-pattern-resistant faults, which limits the fault
coverage that can be achieved with the pure functional BIST approach.
To achieve the desired fault coverage we have to improve the testability of ALU for the given test
sequence by inserting proper test points.
3. Overview of the Test Point Insertion Methods for Improving Testability
Test point insertion (TPI) is a well-known design-for-testability (DFT) technique that inserts
additional logic into a circuit to increase the circuit’s testability. TPI aims particularly at improving the
observability and/or controllability of hard-to-test signal lines in the circuit. Various TPI methods have
been proposed since the 1970s, and nowadays TPI is supported by commercial EDA tools and
commonly applied in industry [22].
The testability improvement offered by TPI results in higher fault coverage, smaller test data volume,
and shorter test application time. Unfortunately, TPI also has some well-known disadvantages: test
points cost additional silicon area, they affect the circuit’s timing, and resolving timing violations due
to TPI complicates the design flow.
Since test points add both area and performance overhead, it is important to try to minimize the
number of test points that are to be inserted to achieve the desired fault coverage. Optimal test point
placement for digital circuits has been shown to be NP-complete [23]. In [24] the first time a
systematic method was proposed for test point insertion to increase pseudo-random pattern testability.
In this paper simulation statistics is used to identify correlation between signals. Thereafter test points
are inserted to break the correlation. In [25,26] the controllability/observability probabilistic (COP)
testability measures [27] are used to guide the placement of test points. Using COP measures the
sectors of hard-to-test faults are identified, and test points are inserted at the origin of the sectors. In
[28] a cost function based on COP testability measures is developed. The gradients of the cost function
are computed in linear time for each potential test point. The gradients are then used to estimate the
global testability impact from inserting a particular test point. Based on this impact, a test point is
inserted, and the COP testability measures are recomputed. The process iterates until the testability is
satisfactory. In [29] the described approach is improved by considering the performance impact of
inserting a particular test point. It was showen that by avoiding control point insertion on critical
timing paths, high fault coverage can be achieved with zero performance degradation. All the
described approaches are based on statistical analysis to improve the testability of circuits in general
independent of that which test sequences actually will be used. In [30] the approach based on COP
testability measures developed so far for Boolean circuits only was extended for three-state circuits.
Recently TPI methods have been introduced to reduce the number of ATPG patterns for scan-based
external testing [31,32]. Reducing the number of patterns leads to less test data volume and shorter test
application time. The similar target for test point insertion is used [33].
Most TPI methods are used with Logic Built-In Self-Test (LBIST) [15,28,29,34,35] or with different
advancements of LBIST like combining TPI with bit-flipping deterministic LBIST [20]. In these cases
pseudorandom test patterns are used and the target of TPI is to improve the testability of the circuit
independent of the test sequence used. In our FBIST approach we take as the basis the predetermined
functional test sequence produced by the system itself. The task is to improve the testability of the
circuit for the given particular test sequence.
In [36] a similar task was formulated, and a test point selection method was proposed for a given test
sequence. In [36] fault simulation is used to identify faults that are not detected by a specific set of test
patterns. For each undetected fault, a path tracing procedure is used to identify the set of test points
that will enable the fault to be detected, i.e. the set of test point solutions for the fault. Given the set of
solutions for each undetected fault, a minimal set of test points to achieve the desired fault coverage is
selected using a set covering procedure.
Differently from [36], we don’t need in our approach costly critical path analysis to determine the
whole set of possible test point solutions for each undetected fault. Instead of that we find a group of
faults which can be activated (provoked [36]) by a single control point. In that way the complexity of
the problem (the number of considered test point solutions) can be considerably reduced. Differently
from [36] we don’t handle all the undetected faults in similar way mixing the controllability and
observability solutions. We first, find the test point solutions for the faults that definitely need fault
activation, and only thereafter solve the problem of observing the faults that remain still not tested. We
also use a different approach to solve the problems of implementing control and observation points,
compared to [36].
4. Overview of the test point insertion method
The problem of interest is given a set of test patterns that will be applied to the Circuit Under Test
(CUT), insert as few test points as necessary to enable all the faults in the circuit to be detected. An
overview of the test point insertion procedure is as follows.
1. Perform fault simulation to identify undetected faults.
Fault simulation is performed for the set of test patterns generated by the functional BIST method for
the given CUT to determine which faults are detected and which ones require improvement either in
controllability or observability.
2. Find the set of faults that cannot be detected without improving their controllability.
Some of the undetected faults cannot be activated (provoked) by the given test set. We call this subset
of undetected faults as the controllability subset. For each fault from the controllability subset possible
test point solutions are found by comparing the needed activation condition with the given set of test
patterns.
3. Select a minimal set of test points needed for improving the controllability of the circuit
Given the set of control point solutions at different test patterns for each fault of the controllability
subset, a set covering procedure is used to find minimal set of control points that allow to activate all
the faults of controllability subset.
4. Synthesize logic to activate the control points
An additional circuitry is designed to improve the controllability of the circuit for activating the
selected subset of controlled undetected faults.
5. Perform fault simulation to identify remaining undetected faults.
The testability has been improved by the described procedures only for the faults of the controllability
subset. Some of these faults may still not be detectable because of the poor observability. For these
faults and for the other undetected faults not yet handled observation test points are determined.
6. Synthesize the output logic for improving the observability of the circuit
An additional circuitry is designed to improve the observability of the circuit for reaching 100% fault
coverage.
5. Finding test point solutions for the faults that need controlling
Denote by T = {t1, t2,..., tn} the set of test patterns generated by the functional BIST circuitry. We
assume that the test coverage of T is below 100% fault coverage.
First, fault simulation is performed for T to determine which faults are detected and which ones
require improvement either in controllability or observability. Denote by R = {r1, r2,..., rm} the set of
faults not detected by T.
Next, the subset RC  R of the undetected faults which cannot be activated (provoked) by the given
test set T will be defined. Let us call this subset of faults controllability subset. Consider, for example,
an AND gate with inputs x1, x2, and, x3. We say that the stuck-at fault (SAF) x1  1 cannot be activated
by T if there exists no test pattern ti  T which produces a pattern x1 x2 x3 = 011 on the inputs of the
AND gate. Similar conditions can be easily formulated for other types of gates and faults.
For each fault rj  RC from the controllability subset possible test point solutions are found by
comparing the needed activation condition with the given set of test patterns. For example, assume
that the test patterns t1, t2 produce, correspondingly, the patterns 111 and 010 on the inputs of the
AND gate under discussion. Then the test point solutions for making the fault controllable will be: x1 =
0 for the test pattern t1, and x3 = 1 for the test pattern t2,
In the next step a minimal set of control points is selected that allow to activate all the faults of the
controllability subset.
The main idea of the test point selection is in the following. The faults of the controllability
subset RC will be partially ordered RC = (r1, r2,..., ri, rj,…, rp) in such a way that for each ri, rj
there will be signal path in the circuit connecting the line of ri with the line of rj, or there will
be no connection between these lines.
We start with the first fault r1 of the ordered set RC, introduce the needed control signal on the
line l1 related to r1, simulate the updated test pattern, and check if some other faults in RC have
got activated by the updated test pattern. Denote this set of activated faults RC(r1,l1,1)  RC. It
may happen that RC(r1,l1,1) = . Then find the closest fanout line l1,2 that feeds l1,1, and repeat
the procedure: introduce the needed control signal on the line l1,2 to activate r1, simulate the
new updated test pattern, and check if some other faults in RC have got activated by the
updated test pattern. Denote this set of activated faults RC(r1,l1,2)  RC. Repeat this procedure
until an input line lk,1 is achieved.
The same is repeated for all the faults in RC. Then a matrix M = mi,j is built where i =
1,2,...,p, and j = l1,1, l1,2,..., l1,k1, l2,1, l2,2,..., l2,k2,..., lp,1, lp,2,..., lp,kp. In the matrix M, a set
covering procedure is used to find minimal set of control points that allow to activate all the
faults of controllability subset.
Input l3
RC(r1,l1,3)
Fault r1
RC(r1,l1,1)
Line l1
Line l2
RC(r1,l1,2)
Fig.2.
The main idea of the method is illustrated in Fig.2. If the line l1 related to the fault r1 will be
controlled, then a cone denoted by RC(r1,l1,1) illustrates the subset of possible faults controlled
from the line l1. If now the line l2 will be controlled, then a bigger cone denoted by RC(r1,l1,2)
illustrates the new subset of possible faults controlled from the line l2. We may expect that
RC(r1,l1,1)  RC(r1,l1,2), since the second cone is larger than the first one. However, it may be
also opposite. The reason is that controlling the line l2 may cancel activation of faults
activated by controlling the line l1.
In fact not all fault in should be analyzed by the described procedure. If for two faults ri and rj
there will be signal path in the circuit feeding the line of rj from the line rj, then the fault rj
should not be analyzed, the test point solution of ri will be also the test point solution for rj.
Differently from the proposed approach, in [36] for all the faults all the possible sensitized
paths for provoking the fault should be generated and based on these paths all the possible test
point solutions should nbe generated.
As an example for the circuit in Fig.3 for the test sequence represented in Table 1, a matrix M
is represneted in Table 2.
Table 2
node
fault
13
14
15
18
19
20
23
26
29
33
35
47
48
I43>a/0
I43>b/0
I29>a/1
I15>a/1
I15>b/1
I11>a/0
I53>b/1
I51>a/1
I10>b/0
I21>a/1
I3>a/0
I14>a/0
I14>b/0
X1
X2
X3
X4
X5
X6
X7
X8
1
1
1
X10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X9
1
1
1
1
1
1
In Table 2, the rows corresponds to the faults and the columns corresponds to the input nodes. The
entry 1 means that the faults can be activated by controlling the input. All the one’s in a column xi
show which faults can be activated from the input xi. By solving the set coverage task, the set of inputs
X = {x2, x5, x9} is chosen, meaning that by controlling only the inputs x2, x5 and x9 all the faults in
Table 2 can be activated.
Table 3
input
X2
X5
X9
node: fault
18: I15>a/1
19: I15>b/1
47: I14>a/0
48: I14>b/0
33: I21>a/1
35: I3>a/0
13: I43>a/0
14: I43>b/0
15: I29>a/1
20: I11>a/0
23: I53>b/1
26: I51>a/1
29: I10>b/0
val: T1
1
val: T2
1
val: T3
val: T4
0
0
val: T5
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
In Table 3 the test patterns are shown when it is possible to activate a given fault from the given input.
The entry 0 (1) means that the controlling value 0 (1) for activating the fault is needed.
For synthesizing logic to control the test points the similar methods can be used as proposed in [36].
6. Synthesizing output logic for improving the observability
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