Register Number
SATHYABAMA UNIVERSITY
(Established under section 3 of UGC Act,1956)
Course & Branch : M.Tech – VLSI/ W-VLSI
Title of the Paper : Testing of VLSI Circuits
Sub. Code : 782E02- SECX5026 (2008-2009-2010)
Date :06/03/2012
Max. Marks:80
Time : 3 Hours
Session :FN
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1.
PART - A
(6 x 5 = 30)
Answer ALL the Questions
State DFT methods followed in digital Circuits.
2.
Write the deign step for Ad hoc testing with an example.
3.
What is meant by stuck of fault?
4.
State scan design schematic with the help of LSSD.
5.
Draw the block diagram of Built -in -self –test circuit.
6.
Write short notes on Neighbourhood pattern sensitive faults.
7.
PART – B
(5 x 10 = 50)
Answer ALL the Questions
(a) Define the following terms: 1.Observability 2. Controllability
(b) Compute the combinational SCOAP testability measures for
the below given circuit.
8.
(or)
Explain Scan test technique and Boundary scan test technique.
9.
Explain the D algorithm
(or)
10. For a Stuck-at fault testing.
(a) Find only three tests that together test all single stuck-at faults
in a two-input OR gate.
(b) If the OR gate is replaced by another Boolean gate (AND,
NAND, OR, NOR) with the same number of inputs and an
output, then can the three tests determine that the given gate is
not an OR gate?
(c) Are the three tests still sufficient for the above decision, if the
OR gate was replaced by an exclusive-OR (XOR) gate? If not,
why?
11. Define the fault models for any five of the following faults:
(a) State Coupling faults.
(b) Inversion Coupling faults.
(c) Idempotent Coupling faults.
(d) Dynamic Coupling faults.
(e) Transition faults.
(f) Active Neighborhood Pattern Sensitive faults.
(g) Passive Neighborhood Pattern Sensitive faults.
(h) Static Neighborhood Pattern Sensitive faults.
(or)
12. Explain a test generation model for Asynchronous circuits.
13. Briefly explain the circular self-test path BIST configuration with
an aid of Lucent technologies.
(or)
14. Explain the BIST process and the BIST Pattern generation.
15. Strictly prove that the MARCH C– test detects all inversion
coupling faults ;  in Memory test algorithms. Further,
indicate the testing time complexity for MARCH C– in terms
of n, the number of bits in the memory.
(or)
16. (a) State the RAM test hierarchy.
(b) Explain the function RAM Testing with March test SRAM
BIST.