Intro/Background:
The Ethernet is the most widely used of the current Local Area Network (LAN)
technologies. It is a family of closely related protocols which share a common set of
frame formats. With the increasing usage of the Internet and multi-media applications,
higher bandwidth is needed to account for the corresponding rise in network traffic.
Typical Ethernet technologies, such as 10 Mbps Ethernet and 100 Mbps Ethernet (Fast
Ethernet), are inadequate to handle such high data traffic, and it was in response to this
that the IEEE 802.3 Ethernet committee came up with a much faster Ethernet technology
in the mid-1990's, namely the Gigabit Ethernet which was originally defined in the IEEE
802.3z standard.
The purpose of the IEEE 802.3z standard is to provide specifications for the
Media Access Control (MAC) and Physical Layer (layer 1 of the OSI Reference Model)
of Gigabit Ethernet, along with other related issues such as design considerations. The
IEEE 802.3z standard is reliant upon the 802.3 Ethernet frame format and Carrier Sense
Multiple Access / Collision Detection (CSMA/CD) access method, and is also compatible
with 10 Mbps and 100 Mbps standards. Gigabit Ethernet also provides updates in areas of
speed and functionality to the existing IEEE 802.3 standard. Shown below in figure 1 is
the Gigabit Ethernet technology family.
Figure 1. The Gigabit Ethernet technology family
1
Gigabit Ethernet operates at the Data Link layer (layer 2) and provides support for
reliable communications between applications of the Network Layer (layer 3) and the
Transport layer (layer 4). It also operates in the Physical Layer and functions as an
interface between the MAC layer and the transmitters in Gigabit Ethernet hardware. It
allows half-duplex and full-duplex data transmission at speeds of upto 1 Gbps for a
network at lower cost than other technologies of comparable speed. This helps in
reducing complexity, resulting in a stable technology that can be quickly developed.
The other Gigabit Ethernet standard within the IEEE 802.3 Committee, apart from
the 802.3z, is the 802.3ab. The IEEE 802.3z Task Force is working on Gigabit Ethernet
for short- and long-haul fibre (1000BASE-SX and 1000BASE-LX respectively), and
short-haul copper (1000BASE-CX). These are known as the 1000BASE-X technologies.
The IEEE 802.3ab Task Force is working on the long-haul copper standard (1000BASET). Table 1 shows the different media, with respective maximum network lengths,
wavelengths and coding schemes.
Name
1000BASESX
Medium
Multimode fibre
1000BASE- Multimode/SingleLX
1000BASECX
1000BASET
mode fibre
Shielded copper
Maximum Wavelength Encoding/
Length (m)
(nm)
Decoding
300
850
8b/10b
3000
1355
8b/10b
25
800
8b/10b
4D 8-state
4 - Cat 5 UTP
100
None
Trellis
FEC
Table 1. Gigabit Ethernet Standards
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The BASE-X standards use the coding scheme that was developed by IBM, the
8b/10b-coding scheme. It encodes 8 bits of data to 10 bits for transmission. The
1000BASE-SX operates only over multi-mode fibre, utilising short-wavelength laser
transmitters (770 - 850 nm), and is intended for short distances. The 1000BASE-LX
provides a larger backbone for applications, defining the Gigabit transmission from 220 550m, or even up to the maximum length of 3km (single mode), while using longwavelength laser transmitters (1270 – 1355 nm). The 1000BASE-CX is the copper-based
variant of the 1000BASE-X family and operates with the maximum length of 25m. The
1000BASE-T draft standard proposes 5-level PAM (Pulse Amplitude Modulation), and
4-Dimensional, 8-state Trellis coding, in addition to pulse shaping and equalization. The
1000BASE-T can function over a maximum distance of 100m.
Design Project
The purpose of this project is to design, implement and test a Gigabit
Optoelectronic link. The design can be divided into three major components:
- The Transmitter (Tx)
- The Optoelectric module
- The Receiver (Rx)
One of the first goals of this project was to study and evaluate the Maxim
MAX3287 EV kit. It is basically a surface-mount demonstration board that allows optical
and electrical evaluation of the MAX3287 1.25 Gbps laser drivers. The idea was to test
this evaluation kit, understand it’s working and then improve upon its design (in terms of
cost and performance) with the help of reverse engineering. The kit is discussed in
greater depth in a later section of this report.
Vertical-Cavity-Surface-Emitting Laser diodes (VCSELs) are an integral part of
this project and feature in the Tx design. They are a relatively new class of semiconductor
lasers that emit light perpendicularly from the wafer and are composed of layers of
partially reflective mirrors which confine the light. The factors involved in considering
the VCSELs ideally suited to our design will be discussed in the section on design
specifications.
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PDs (PDs) form the beginning of the Rx module. They capture and convert the
optical signal into an electrical one, maintaining the data present in the original stream.
As with previous components, the relevant factors for PDs will be dealt with later.
The optical fibres used are multi-mode types, functioning at the 850 nm
wavelength. As their name implies, multi-mode fibres propagate more than one mode, the
number of which depends on the core size and the numerical aperture (NA) of the fibre.
The higher the previously mentioned parameters are, the easier it is to launch the light
into the fibre, resulting in a reduced need for core-to-core alignment. The core size for the
project fibres is 62.5 m.
The MAX3287 Evaluation Board
The MAX3287 is a high-speed laser driver for fiber optic LAN transmitters,
optimised for Gigabit Ethernet applications. It is comprised of a bias generator, a laser
modulator and numerous safety features. An additional automatic power control (APC)
circuit adjusts the laser bias current to maintain average optical power at a constant level,
irrespective of temperature or laser properties. It operates on a supply voltage of 3.0V to
5.5V and can switch up to 30mA of laser modulation current.
Testing of the Evaluation Board.
Testing of the Maxim evaluation board is important to verify its functionality as it
gives us an idea as to how to design, test, and implement the final layout. The test setup
for the MAX3287EV kit is shown in Figure 2 which is used to accomplish the Bit Error
Rate testing (BERT). The components used to build the setup are as follows:

5 voltage power supply source.

SMA cables with SMA connectors on both ends.

The MAX3287 evaluation board (two SMA inputs and one SMA output).

Tektronix GTS1250 GBIC Test System 1250Mbps function generator - used for
obtaining the inputs and clock signals.

Tektronix TDS7154 Digital Phosphor Oscilloscope – used to see the output,
particularly useful in obtaining and measuring the validity of the eye diagram.
The Maxim board was connected to 5V power supply. The two GTS1250 outputs,
DATA (+) and DATA (-), were connected to the two inputs of the Maxim board, IN+ and
IN-. The output (OUT-) from the Maxim board was connected to channel 1 of the
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oscilloscope and the clock from the function generator was connected to channel 3. The
function generator was set to output PRBS7 mode which is normally used for testing. The
setup was simulated to obtain an eye diagram on the oscilloscope.
Figure 2. Test setup for the Maxim EV board.
Figure 3 indicates the eye pattern obtained by using the above test setup. The eye
pattern in this figure is obtained using a DC coupled maxim board. It is also inverted as
the output is coming from the complementary output, OUT-, of the evaluation board.
Figure 3. The eye pattern observed from the DC coupled output from MAX3287 EV board.
5
This eye pattern is close to a perfect open eye as the opening is very wide; it has a
good height, and does not have much jitter. However, there is a dip at the bottom of the
eye pattern. This dip was also observed in the results of other transmitter groups and so
far we have been unable to identify the reason for its existence. The open form of the eye
signifies that it has a high quality SNR and signal received has very few errors. As the
pattern closely resembles the standard compliance mask, it can be said that the signal
would pass through without any significant errors. Thus, the workability of the Maxim
board is verified.
Eye Pattern
The most important analysis tool in determining the performance of the data
transmission is the eye pattern. It is defined as the oscilloscope display in which a
pseudorandom digital data signal from a receiver is repetitively sampled. It is applied to
the vertical input and the data rate is utilised to trigger the horizontal sweep. Eye pattern
signifies the amount of noise in a signal. A wide, open eye pattern corresponds to
minimal signal distortion and shows that the signal received has low noise along with low
bit error loss whereas a close eye pattern corresponds to very high noise and greater bit
error loss. Closure of the eye pattern appears as the distortion of the signal waveform due
to inter-symbol interference (ISI) and noise.
An eye pattern has three significant characters: the width, height, and the sensitivity. The
width of the eye signifies the time interval over which the signal received can be sampled
with no errors from ISI. The height of the eye can be defined as the noise margin of a
system at a particular time interval. In short it is the measure of the signal-to-noise ratio
(SNR). The rate of closure of the eye as the sampling time is varied determines the
sensitivity of the system to timing errors.
Design Specifications
A detailed analysis was conducted on the various types of VCSELs and PDs
available before ordering the ones we believed were best suited to our project. Only
components, which could realise Gigabit Ethernet compliant data rates, were chosen.
Both connectorised and unconnectorised VCSELs were considered, with the tradeoffs
involved being cost and performance. The unconnectorised components have to be
manually aligned with the optical fibre and require a great deal of precise handling. The
6
slightest miscalculations could result in considerable connector losses. As such, they are
cheaper than the connectorised parts which do away with rigorous manual adjustments.
The above-mentioned guidelines were used in the selection of the PDs as well.
The most important design specifications for the VCSELs include operating
frequency, slope efficiency, divergence angle and threshold current (Ith). Gigabit Ethernet
requires the frequency of the laser emitter to be more than 1 GHz. A wavelength of
850nm is also required for the multi-mode fibre. The slope efficiency, as defined by
Honeywell, is the ratio of the output power wattage to the input current. A higher slope
would correspond to a higher emission of light from the VCSEL. Beam divergence is the
light intensity full width at the 1/e2 level. This parameter should be low enough for the
light to be significantly transmitted to the fibre. Ith is the minimum range of current
needed to drive the VCSEL and its value should be such that it provides a considerable
range of output power or light into the PD, generating sufficient current to activate the
TIA.
The relevant factors for the PD include bandwidth, wavelength, capacitance, dark
current (ID), and most importantly responsivity. The first two mentioned are the same as
the specifications for the VCSELs. The capacitance and the ID are considered as factors
of noise and should be kept low. The responsivity of the PD is the amount of current
generated when a certain amount of photon energy is incident upon the PD. Its value
should be large enough to convert the light into a current which would then drive the
TIA.
Parts Specifications and Searching
The task of selecting parts was mainly influenced by two constraints: The 802.3z
standard and the Maxim 3266 Transimpedance Amplifier (TIA). A listing of these
specifications appears in Table 2. We found the active components first, because the
VCSEL
Photodiode
Dark Current < 5na
Capacitance < 1pF
Passive
Components
Size = 0805
Inductors – Ferrite
Bead from Murata
Table 2. Specifications Constraints due to design criteria.
Cathode Common
Rise Time < 300ps
electrical designs did
not have to be made to select them. The design project dictated that we find both SC
7
connectorized and unconnectorized VCSELs and PDs. The passive components were
picked after finalizing the board designs. All our parts were found on the Internet, using
the Google search engine. The parts we ordered and some of their key features are
shown in Table 3. As discussed farther below, though, the choice for VCSELs might
change.
HFE-4080321
1.5 - 6
0.1 – 0.4
HFE-4384522
1.5 – 6
0.06 – 0.3
Ith (mA)
Slope
Efficiency
(mW/mA)
Beam
5 - 20
N/A
Divergence ()
Table 3a. VCSEL Specifications.
SD008-17-51-211
FCI- 125G-006HR
Active Area diameter (m)
200
150
Capacitance (pF)
0.3
0.66
Responsivity (mA/mW)
0.45
0.36
Table 3b. PD specifications.
Part
Part Number
Quantity
Ferrite Bead Inductors
BLM21AG102SN1D
6
1k Potentiometer
3296W-LC2-102
3
50K Potentiometer
3296W-LC2-503
3
24.9 Ohm Resistor
P24.9CCT-ND
10
115 Ohm Resistor
P115CCT-ND
10
150 Ohm Resistor
P150CCT-ND
10
Table 3c. Passive Component list.
Honeywell was quickly recognized as a leading manufacturer of high-speed
VCSELs. Browsing through a table of a couple dozen different products, we found two
that fit our criteria. The search for PDs proved to be a formidable challenge, though.
Manufacturers of niche semiconductor products mainly do business with other
8
manufacturing companies, thus there is little reason to advertise to the masses online.
Ciena has a list compiled of dozens of companies from whom they do business with. Our
search produced few of the names on that list, and, unfortunately, we as students don’t
have access to them. Most of the companies which Google returned to us after searching
for just ‘PDs’ and ‘silicon detectors’ provided custom orders, but offered no standard line
of their own. Hamamatsu offered the best product of the manufacturers we initially
encountered. Unfortunately, none of the pieces listed conformed to the capacitance
constraint of the TIA. The lowest value we found was 1.2pF at 850nm. After conferring
with Professor Brooke, we decided that this could be made to work, but it might be
pushing the limits of proper performance. We were already a week behind schedule, and
it was not worth modifying our Receiver design unnecessarily with no guarantee that it
would work in the end.
We performed a more comprehensive search of Google, and even ran through
online business lists found on Yahoo!, which offered very little help. Eventually, the
SD008-17-51-211 from Advanced Photonix was stumbled upon. The rise time was a
little high at 350ps, but this would not affect the electrical operation of the receiver. Only
the strict 802.3z standard would be compromised, easily resolved with a better part later,
but sufficient for testing our initial design. The company also offered an SC
Connectorized version of the part, and we chose the Hamamatsu S7912 as our
unconnectorized part for lack of a better option.
The Honeywell site led us to a local distributor, Allied Electronics. They would
not sell in quantities of less than 100, so our wonderful contact, Lindy, ordered samples
direct from the manufacturer. We made sure to keep in contact with her on a regular
basis to make sure our order was being processed. Due to our placing the order for the
two VCSELs at different times, and our lack of experience in the area, there was a mixup,
and we only received the unconnectorized HFE-4080-321. The order was placed again,
but in the meantime, our one VCSEL was stolen from the lab. There was an even bigger
disappointment later when Honeywell decided to stop sending the Georgia Tech groups
any more samples. We must pay for them directly from the plant with an unacceptable
lead time of 4 weeks. Here we found the value of cultivating good relationships with
vendors, for Lindy was sympathetic enough to give me the names of other group
9
members who had ordered extra parts so that we might contact them and share their
surplus.
The wording for the Advanced Photonix diode was misleading, for after two days
of talking to engineers and customer service, it was discovered that the SC connector is
not standard, and would cost well over our budget to obtain just a single piece. Thus we
reluctantly performed an even more comprehensive Google search for 4 hours until the
OSI Fibercomm 125G006HR was discovered. It far surpassed the capacitance and rise
time specifications, but was a little weak in the area of responsivity. It would work fine,
though, as long as our design was not sloppy. The SC connectorized version was in stock
and ready to ship next day as well. We would use the Advanced Photonix SD008-17-51211 as our unconnectorized PD. Unfortunately, the latter part was stolen along with our
one VCSEL. We were forced to order another piece.
We were able to sample most of our passive components as well. Allied
Electronics was a vendor for Murata, and Lindy was more than happy to sample us six of
the Ferrite Bead Inductors which we needed. We called Bourns directly about the
trimmer potentiometers, and they sampled two of each for us. The resistors were ordered
straight out of the Digi-Key catalog.
At this moment, we are waiting for our passive components and first fab board to
arrive. We already have the connectorized Fibercomm PD, and are waiting on a new
shipment of the Advanced Photonix SD008-17-51-211. We need to find an alternate
vendor for the VCSELs, and perhaps have them priority shipped so that we don’t get
more than a week behind.
Soldering
Since no one on the design team had extensive experience with soldering, it was a
group effort learning how to solder and assembling the test receiver board. However,
there were certain characteristics of a well-soldered joint that the group attempted to
achieve. The joints would have to be shiny and smooth and also “suction” to the
component and board (Figure 7).
10
Figure 7. Illustration of desired solder joint.
The locations of the components were identified using the provided schematic. The group
attempted to solder the passives first because the components were less costly in case an
error was made. Early attempts with soldering the passives yielded joints that were rough
and dull. Also lack of experience also led to some of the lines being shorted. However,
the group continued practicing on the first Rx board although it was no longer usable.
Once the desired joint characteristics mentioned earlier were achieved, the group started
the assembly of the second and final Rx board. Some of the problems that the group
encountered earlier were fixed by soldering at a slightly higher temperature. The
assembly of the second board went surprisingly smooth, but one of the passive
components may have been overheated. It had been accidentally shorted and the tip of the
soldering iron was used to cut away the short.
Receiver Test Setup
After the Receiver board (Rx) was assembled, the Rx was about to be tested to
determine whether the Rx could receive data at a Gigabit rate. A functional diagram for
testing Rx is sketched in Figure 4. It shows the transmitter connected to Tektronix TDS
694C Digital Oscilloscope.
11
Figure 4. Functional Rx testing diagram
.
Then SMA cables were used to link the transmitter and the receiver together. In brief, the
set up was arranged such that the signal from the pattern generator could come through
the transmitter, fiber optic cable, the receiver, and then to the oscilloscope so that an eye
pattern could be obtained on the oscilloscope. The test was run from 0 dB to 40 dB at the
data input rate of 1.25 Gigabit per second. And screen captures were taken at 0 dB, 10
dB, 20 dB, 30 dB, and 40 dB.
Eye Mask
While transmitting multiple bits of data through a communication system, there
are some potential errors that cause by noise and inter symbol interference (ISI). An
IEEE standard “eye mask”, as shown in Figure 5, is a quick visual aid to determine
whether data were transmitted properly to the receiver. Basically, the standard states that
any eye pattern formed from the superimposition of the data waveforms must have a least
normalized opening time interval that equal to the opening time interval of the eye mask
(unit interval from 20 to 80 % ) in order for the system to work properly from ISI.
12
Figure 5. Eye Diagram
Results
After second attempt, the output waveforms shown on the scope are shown on
Figure 6. Quick observation indicates the system works well at low dB test. At 0 dB noise
ratio, rather than ISI, seems to pose a slight problem, but tolerable. In region from 0 to 20
dB the eye patterns are clean; and they are big enough to enclose the eye mask indicating
that they would cover the “wide opening eye interval”. However, in the higher region, ISI
seems to be a big problem. Deliberate consideration indicates that is due to poor
soldering joints. At 0 dB noise rather than ISI poses a slight problem. A proposal had
been made to improve the results. But due to budget and time constrains, the
improvement has not been carried out.
13
Figure 6. Eye pattern at various attenuations.
Optical Link Budget
When constructing the optical gigabit Ethernet board, the optical limitations of the
system must be considered during its design. The conglomeration of the laser, the fiber,
the PD, any optical connections/splices, and alignment tolerances all operate within
certain parameters. These parameters will ultimately determine how the overall design
will perform. Thus, an optical link budget which analyzes the specifications of the
optical subsystem (Figure 8) is required.
Figure 8. Optical System Diagram.
14
As is seen above, the Maxim 3287 supplies the modulation current to the VCSEL,
which converts the current into an optical signal that travels through the fiber, which is
received by the PD, which converts the optical input into a current that the Maxim 3266
converts into a differential voltage which is amplified by the Maxim 3264. Since
analyzing the entire system at once would lead to complications, the optical link budget is
divided into three parts: the transmitter section, the optical medium section, and the
receiver section.
VCSEL Transmitter Section
Due to the eye safety standard imposed in IEEE 802.3z, the VCSEL is limited to
an output power of 1 mW. As a result, the slope efficiency ranges for both selected
VCSELs determines the required input current by simply taking the reciprocal of the
slope efficiency and adding the bias current (Ith). The input current ranges are shown in
Table 4.
Table 4. Required Input Current to VCSEL to obtain 1 mW output.
The maximum modulation current provided by the Maxim 3287 is 30 mA, and the
maximum input bias current is well above 12 mA, meaning that the above current ranges
are well within the capabilities of the transmitter circuit.
Beam Divergence
The IEEE standard 802.3z requires that the beam divergence of an optical source
be less than the angle of numerical aperture of the fiber in order to ensure signal
propagation down the optical fiber. The calculations below indicate that the angle of
numerical aperture for a multi-mode fiber (the difference between graded and step index
fibers is negligible) is almost 12 degrees.
n1 ≈ 1.456 ∆ ≈ 1% NA = .205909 sin-1(NA) = 11.88◦ [IEEE]
The worst possible beam divergence angle given by the unconnectorized 4080-321
VCSEL is 20 degrees at full width-half maximum. Since the numerical aperture angle
was calculated at half width, the corresponding divergence angle from the VCSEL is 10
15
degrees. Therefore, since the beam divergence is less than the numerical aperture, signal
propagation is assured.
Optical Medium Section
The optical medium determines the loss associated with the system and
consequently determines whether it is possible for the PD to receive enough power from
the VCSEL in order to operate properly. Thus, all possible losses must be accounted for
and summed to determine total optical loss. Each optical connector averages .3 dB loss,
and since there are two connectors, this contributes .6 dB of loss. Multi-mode fiber
operating at the 850nm wavelength incurs 3.5 dB/km, and since the maximum fiber
length allowed at gigabit operation is 275 meters, the fiber contributes .9625 dB of loss
[3]. Moreover, 6 dB is usually introduced to account for losses that accumulate over the
system’s lifetime. Since the total calculated loss, 7.58, is above the recommended IEEE
optical budget loss, 7.5 dB, 8 dB of loss through the optical medium is assumed instead
to account for the worst case.
Receiver Section
The PD junction capacitance determines the speed limit due to the fact that a
larger capacitance takes longer to discharge current over a load. Therefore, junction
capacitance is a determining factor in the upper bandwidth limit of the system. As shown
in Figure 9, the reverse bias changes with junction capacitance, and with less reverse
bias, less current will flow from the PD.
Figure 9. Voltage vs. PD Junction Capacitance.
With the selected PDs having junction capacitances of.3 and .66 pF, the minimum reverse
bias provided by the Maxim 3266 will be over 3V, allowing for significant current flow.
16
Moreover, junction capacitance and the PD’s resistive load determine the discharge time
constant associated with photodetection. Such a time constant must be at least three
times smaller than the period of the desired operating frequency in order to function
properly. The Maxim 3266 reports an input load of 50Ω, and this multiplied with the
larger capacitance of 0.66 pF yields a time constant of 33 ps. The operating frequency of
1.25 GHz has a period of 800 ps, which is 24.24 times higher than the computed time
constant. Such a large margin ensures the successful operation of both PDs at 1.25 GHz.
Since the PD receives 1 mW with 8 dB of loss, it receives .158 mW of power.
Using the worst responsivity, 50 uA of current is produced from such a system. In order
to ensure adequate operation of the Maxim 3266, an input current of 25 uA is required.
[1] Thus, the successful operation of the receiving end is assured since the PD provides
twice the necessary current in the worst case scenario.
Transmitter and Receiver Circuit Design
The first circuit design for the optical Ethernet link was the transmitter board.
Figure 10 below shows the transmitter circuit schematic.
Figure 10. Transmitter Circuit Schematic.
This circuit consisted of a number of passive elements, the Maxim 3287 chipset that
operates as the differential amplifier, and a Honeywell #HFE4080-321 VCSEL. The
input of this circuit was two voltage data streams that are complimentary to each other.
17
AC coupling was implemented in the path to the differential amplifier from the input to
block dc and low frequency signals that would constitute noise and therefore interfere
with the transmitter operation. Resistor R1 was used as a line matching impedance for
the two inputs. R1 had to be 100 to effectively cancel the transmission line effects
from the inputs so that both inputs are not reflected back out of the circuit. A revision to
the original circuit only included a resistor Rs2 in series with potentiometer Rp2 to act as
an adjustable current source for the differential amplifier and a resistor Rs1 in series with
potentiometer Rp1 to act as the bias circuitry for the VCSEL. The series resistor Rs1 was
used as a protection for the VCSEL because huge biasing current would enter the VSCEL
and would promptly destroy it if there were no dissipation of current between the power
supply and VCSEL. Series resistor Rs2 performed the same function as Rs1 but was
applied to the differential amplifier. Ferrite bead inductors were used to block ac signals
from interfering with the biasing circuitry for the VCSEL and the differential branches.
It was important to design the differential branches so that the impedances matched each
other at high frequencies. Because the inductor in the VCSEL biasing circuitry acts as an
open circuit at these frequencies, only the VCSEL impedance was necessary to match.
This value was found to be 25 from the Honeywell data sheet so a resistance of 24.9
was picked.
The next section of the transmitter circuit that was to be designed was the laser
driver circuitry, or biasing circuitry, for the VCSEL. The function of this circuitry was to
drive the VCSEL to create a laser beam by feeding a dc current through the VCSEL that
was larger than the threshold current of the VCSEL. A potentiometer was used to adjust
the dc biasing current from the maximum safety threshold current of the VCSEL to a
value slightly lower than the minimum required threshold current. The design was
assuming the VCSEL had approximately 2.1V on it and the dc power supply was at 5V.
Turning the potentiometer wiper all the way to the side to which it was not connected
nullified the potentiometer resistance so the maximum current from this biasing circuit
could be found. It is given below in Eq. X1
Rs1 
5V  2.1V
13.3mA
18
A resistance of 150 was calculated for the series resistance and a potentiometer value of
1k was chosen to get a good range for bias current. Because the current is inversely
proportional to the resistance across which it flows, the potentiometer will be able to vary
the current into the VCSEL at a safe level. The current source for the differential
amplifier used the same potentiometer and resistor combination as the laser driver
circuitry. The value for the potentiometer, 50k, was found in the Maxim datasheet for
the Maxim 3287 chip and the series resistor was arbitrarily picked to be 1k so that the
potentiometer would be the dominating resistance.
The final design issue that needed to be addressed for the transmitter circuit was
coupling. The power source needed to be decoupled to ground so the high frequency
noise from the transmitter board would not interfere with the dc input biasing. The input
and differential branches needed to block low frequency signals. The input needed to
block noise in the form of low frequency signals coming in from the input source as
outside interference or leakage. The differential branches need to block the dc biasing
current, which could cause an offset voltage to appear at the output. Capacitors of the
value 0.01F were used for all coupling and decoupling in the transmitter circuit.
The receiver circuit design was borrowed from Professor Brooke and then
modified slightly because the design had proven to work. A schematic of the final
receiver circuit is shown below in Figure 11.
Figure 11. Receiver Circuit Schematic [1].
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The input to this circuit was the output of the transmitter board VCSEL. A photo-diode
acted as a photo-detector converting the laser beam signal into an ac current. The ac
current passed through a TIA where it was converted into two differential and
complimentary voltage signals. The TIA was the Maxim 3266 chip. Figure 12 below
shows the schematic of the chip.
Figure 12. Maxim 3266 Chip Schematic [1].
This chip consisted of a TIA in series with a voltage amplifier. A lowpass filter acted as
a dc cancellation circuit and was the feedback network from the voltage amplifier to the
TIA. The TIA converted the single-ended current into a single-ended voltage. Next, the
voltage amplifier converted the single-ended voltage from the TIA into a differential
voltage. The output stage of this device was an output buffer, used to give a low output
impedance for the chip, in series with 50 on each differential path that led into an
output filter, which was a lowpass filter that limited the bandwidth and noise of the
output. After being converted to a differential voltage, the input signal traveled through a
limiting amplifier. The limiting amplifier boosted the input signal by 55dB and limited
the positive side of the differential signal to 5V and the negative side of the differential
signal to 0V at the output. This configuration gave a digital output that matched the
original transmitter input. The Maxim 3264 chip was used for the limiting amplifier and
is shown in Figure 13 below.
20
Figure 13. Maxim 3264 Chip Schematic [1].
This chip accepted differential voltages as inputs into an input buffer. The input buffer
creates a input impedance of 100 across the input terminals. It was recommended to
use the Maxim 3266 as the input stage to this chip. A gain stage was put in series with
the input impedance and gave the gain of 55dB. Unfortunately, this made dc offsets a
larger threat to performance. A lowpass filter was used as a feedback path from the gain
stage to the input buffer to effectively reduce the dc offset voltages. In series with the
previous components of the limiting amplifier was an output buffer. This output buffer
was used to provide low output impedance with resistors attached to the power supply.
The first important aspect of designing the receiver circuit was to match the
impedance of the photodiode by introducing a 50 resistor to ground. This
implementation would nullify transmission line effects.
Just as in the transmitter, coupling was an important part of the receiver design.
The input to the transimpedance amplifier, connection between the TIA and the limiting
amplifier, and the connection from the limiting amplifier to the output SMA connectors
needed ac coupling to block dc offset voltages and line noise in the form of undesired low
frequency signals coming from the photodiode and preceding stages in this circuit.
Power supply decoupling was also necessary for the same reason described in the
transmitter section. However, one amplifier would create noise that would affect the dc
biasing on the other amplifier. Using two independent power supplies fixed this problem.
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The final point of design for the receiver circuit was the dc biasing resistances for
the limiting amplifier outputs. These resistors acted as pull-down resistors from the
power supply to generate a dc biasing current for accurate output from the limiting
amplifier. The resistors used had a value of 100 each.
Table 5 below is a complete list of all the components and their values used in the
transmitter and receiver design.
Table 5. Component Values of the Transmitter and Receiver
Circuits.
Component Value
Transmitter Circuit
R1
100
R2
24.9
Rp1
1k
Rs1
150
Rp2
50k potentiometer
Rs2
1k
C
0.01F
L
Ferrite Bead Inductor
Receiver Circuit
R1
50
Rb1
100
Rb2
100
C
0.01F
Layout
A PCB printing company called Express PCB was chosen to produce the PCB
boards. The Express PCB software was obtained from the company’s website. Before
designing the layout, a few major concerns were addressed. First the transmitter layout
was designed. The critical path was laid out first, knowing that it would have to be
minimized to avoid transmission line problems. Next, it was important place the VCSEL
as close to the chip as possible. This is so that line noise will not interfere with the
operation of the VCSEL. Any turns with lines carrying an AC signal implemented 45
degree angles to avoid any feedback. Using these general guidelines, a draft was
produced shown in Figure 14 below.
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Figure 14. 1st attempted Tx design on the left (a); Final Tx design on the right (b).
All the passives on the board were 0805 compliant. The spacing of the pinholes for the
VCSEL, and the pots were not available at the time so space was just left for the pots and
a guess was taken for the VCSEL. A review of the draft revealed that some major
revisions had to be implemented. Figure 14 illustrates the major revisions that were
made. It was necessary to rearrange some of the passive components so that the VCSEL
would be as close to the matching resistor on the opposing differential branch as possible
(1). This would allow the feedback loop between the differential branches to be very
short, thus making the VCSEL operation more stable. Secondly, resistors were added in
series with the pots to better protect the circuit from dangerously high levels of bias
current (2). Another stabilizing implementation was the use of 90-degree angles at the
input end of the circuit (3). This would in effect remove unwanted high frequency signals
that would cause jitter in the signal. The power supply connector was also switched out
for the correct version. The pinhole spacing for the VCSEL and pots were obtained from
the accompanying specification sheets for the respective parts and the parts were drawn
into the final version. For the Rx design, Professor Brook’s layout was used with the
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exception of the PD replacing the electrical input. The final Rx board design is shown in
Figure 15.
Figure 15. Rx layout with PD replacing the electrical input.
Group Management:
Division of labor was based upon the engineering skills possessed by each group
member. GANTT charts were used to plan the allocation of resources needed to carry out the
project. This is a useful tool in analyzing the progress made throughout the various stages. A
website was launched specifically for the purpose of facilitating communication between the
group members. Announcements and updates were posted regularly. For any venture to be
successful, its members must possess strong inter-personal communication skills and the
individuals in our group duly exhibit these. Figure 16 demonstrates the current project schedule.
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Figure 16. Latest GANTT Chart
We expect to start work on the design of the 2nd Tx/Rx in case any unexpected problems
occur with the 1st design. We are awaiting the arrival of the pre-fabricated boards and intend to
build and test the 1st design.
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