Status Report
1394b: Gigabit Optoelectronic Data
Communication
Tiffany Lovett, gte291r
Tornya Moore, gte668r
Mareisha Winters, gte824t
ECE 4006 C
Tuesday, Thursday 12-1:30p.m.
Spring 2002
March 26, 2002
Georgia Institute of Technology
College of Engineering
School of Electrical and Computer Engineering
Introduction
As technology advances, the need for higher speed and more efficient data
transport devices has emerged. The birth of the compact disc in the 1980s marked the
beginning of digital technology in consumer electronics. Since then, digital technology
has emerged as the dominant standard in both audio and video applications. Digital
processing generates large amounts of data compared to their analog counterparts. To
transport this large volume of digital data at high-speeds a new interface is needed. IEEE
1394b is a high-speed serial bus that promises to revolutionize the transport of digital
data for computers and consumer electronic products.
Our project focuses on designing a circuit that is compatible with the 1394b
specifications to transport data and Gigabit speeds. The purpose of this portion of the
design project is to search for optoelectronic devices, specifically a PIN photodiode and a
VCSEL, which will be connected to the receiver and transmitter portions of the circuit
respectively. The functionality and compatibility of these devices will be tested to verify
accurate data transfer.
The project can be divided into three main components. The first step is to
remove the optoelectronic module from the 1394b test-bed. The optoelectronic module
will then be connected as a separate component and then tested to make sure it still works
with the 1394b card. Secondly, different PIN photodiodes and VCSELs will be
investigated and compared. The devices that match the specifications of the 1394b as
well as the MAXIM Evaluation Kits will be chosen. These components will then be
connected to the MAXIM boards. The MAXIM evaluation boards will then be wired to a
test-bed and tested. A GTS 1250 pattern generator and an oscilloscope will be used in
the testing. Lastly, if time permits, our group will design our own board similar to the
MAXIM boards, and will test the functionality.
At this point in our design project we are in the second stage of the second
component of the project. A VCSEL has been chosen, mounted it on its own board, and
tested using the Intel/Agilent optoelectronic module from the previous semester’s design.
This report will discuss the steps and results we have obtained thus far.
Design Considerations for the VCSEL
The two VCSEL candidates that were being compared for the OE circuit of the 1394b
test bed were the Honeywell HFE4380-521 and HFE4384-522. When choosing which
VCSEL should be used, there are some determining characteristics that must be
considered. It is necessary to investigate the threshold current, and slope efficiency of the
VCSEL. The following figure shows the design specifications of the two VCSEL
candidates.
HFE4380-521 VCSEL design specifications.
HFE4384-522 VCSEL design specifications.
Figure 1. Design specifications for Honeywell VCSELs.
The only difference between these two VCSELs is their slope efficiencies. One has poor
slope efficiency, while the other has efficiency appropriate for the design of this project.
The HFE4384-522 VCSEL was chosen based upon the link budget calculations.
Link Budget
Link budget analysis is the calculation and verification of the operating
characteristics of a fiber optic system. Prior to implementing or designing a fiber optic
circuit, a loss budget analysis is recommended to make certain the system will work over
the proposed link. The purpose of the link budget analysis (also known as link budget or
link power budget) for this project is to determine whether the transmitter and receiver
system provide sufficient current to drive the post amp. Specifically, it is necessary that
the TX circuit will be able to drive the VCSEL, and that the photodetector’s output
current can drive the trans-impedance amplifier on the RX circuit. In the table below the
results of the link budget calculations are shown.
Table 1. Link Budget Analysis Results
Ith(m
A
)
D
Cbiasoflas
er(m
A
)
S
lopeE
fficiency(m
W
/m
A
)
M
odulationC
urrentofTX(m
A
)
R
angeofP
ow
erO
utput(m
W
)
R
angeofP
ow
erO
utput(w
/ Los
s
)(m
W
)
R
es
pons
ivityofLas
erm
ateP
D(A
/W
)
R
es
pons
ivityofH
am
am
ats
uP
D(A
/W
)
R
angeofC
urrentfromLas
erm
ateP
D(uA
)
R
angeofC
urrentfromH
am
am
ats
uP
D(uA
)
H
FE
4380-521H
FE
4384-522
6
6
7.2
7.2
0.04
0.15
30
30
0.288-1.2
1.08-4.5
0.144-0.6
0.54-2.25
0.4
0.4
0.47
0.47
57.6-240
216-900
67.7-282 253.8-1057.5
This table shows that the HFE4384-522 VCSEL would be a better choice because the
range of current is well over the acceptable range needed for the RX circuit. Even though
80 μA (the minimum current needed for the trans-impedance amplifier) falls in the range
of the HFE4380-521, there is a possibility that the current coming from the photodetector
will be less than that value. Therefore we have chosen the HFE4384-522 to implement
our laser design for testing.
Design of the Laser Board
The figure on the following page is the schematic of the VCSEL circuit that was soldered
onto a board.
Figure 2. Schematic of VCSEL circuit
From information provided by Dr. Brooke the component values in the circuit were
determined. In order to minimize reflections the VCSEL circuit had to have a total
resistance of 50 . Therefore, a surface mount resistor of 25  was placed in series with
the VCSEL, which has a typical resistance of 25 . Since the GTS 1250 pattern
generator has AC coupled outputs, a DC bias T needed to be connected in order to make
the AC coupled outputs DC, to be compatible with the VCSEL.
A 2 k resistor was used in series with the 5V power supply. This value was
chosen based upon the threshold current of the VCSEL, which was chosen as 2.5 mA.
The threshold current range given by the Honeywell specifications is 1.5 to 6 mA. Using
Ohms Law, having a 5V power supply and a current of 2.5 mA gives a resistance of 2
k.
Once all of the components were gathered they were mounted on the board and
soldered in place. A photo of the board is shown below. Since the VCSELs lead solder
temperature could not exceed 500F, and the solder iron could not be placed more than
10 seconds on the VCSEL, a multimeter was used to verify the VCSEL was still
functional after soldering. Once this was verified testing began.
Figure 3. Picture of VCSEL circuit
Testing
In order to test the VCSEL board a Tektronix GTS 1250 pattern generator and a
Tektronix 7000 series oscilloscope were used to produce an eye diagram. The bit error
rate (BER) is the percentage of bits that have errors relative to the total number of bits
received. The acceptable BER for this project is 10-12. This means that out of 1012 bits
transmitted, one bit was in error. The BER is an indication of how often data has to be
transmitted because of an error. The oscilloscope displays the data stream as information
is transmitted. A picture of the Tektronix oscilloscope and the GTS 1250 pattern
generator is shown below.
Figure 4. GTS 1250 pattern generator and 7000 series oscilloscope
The data transmitted creates an eye pattern. An eye pattern is as a synchronized
superposition of all possible realizations of the signal of interest. It provides useful
information pertaining to the performance of a data transmission system. The width of
the eye opening defines the time interval over which the received signal can be sampled
without error. The preferred time for sampling is the instant of time at which the eye is
open the widest. The height of the opening defines the amount of noise in the system.
While the length of the eye opening is determined by the jitter of the transmitter.
Initially to begin testing the Intel/Agilent optoelectronic board from the previous
semester was used. The GTS 1250 was connected to the transmitter portion of the
Intel/Agilent board and the Tektronix 7000 series oscilloscope was connected to the
receiver portion of the board. A fiber cable was used to loop the receiver and transmitter
together. Once power was connected, an eye diagram was visible on the oscilloscope.
The figure on the following page shows the output of the eye on the oscilloscope.
Figure 5. Eye pattern produced by Intel/Agilent optomodule.
In order to test the VCSEL it was used as the transmitter portion of the
Intel/Agilent board. On the next page is a diagram of the setup for testing the VCSEL
board. First the DC power supply was connected between the SMA and the 2 k
resistor. The GTS 1250 was connected to the SMA on the VCSEL board and the
VCSEL was connected to the receiver of the Intel/Agilent board with SC connectorized
cable. The SMA outputs of the Intel/Agilent board were connected to Channels 1 and 2
of the oscilloscope. Channel 3 of the oscilloscope was connected to the clock of the GTS
1250. Last two 5V power supplies were connected to the input power of the Intel/Agilent
board.
Figure 6. Setup for testing the VCSEL board.
Once all connections were made the DC power supply, the GTS 1250, and the
oscilloscope were turned on. The oscilloscope was configured for mask settings and an
eye diagram appeared. In figure 7 on the following page is screen capture of the eye
diagram. It had zero errors for this testing as seen in the far right of the figure.
Figure 7. Eye pattern produced by VCSEL.
The next step was to perform testing using the Maxim transmitter board. The
GTS 1250 was connected to the Maxim board, which was connected to the VCSEL board
by a SMA connector. The VCSEL board was then connected to the Intel/Agilent as in the
previous testing setup. Once power, the GTS 1250, and the oscilloscope were turned on
there was no eye diagram that formed. After discussions with professors it is believed
that a potential problem is that the Maxim transmitter board is DC coupled and it needs to
be AC coupled. This can be corrected by de-soldering a few resistors. Once this is done
then retesting can take place, which hopefully will produce a passable eye diagram.
Future Testing
At this point the VCSEL board has been designed and implemented. A passable
eye diagram has been viewed when the VCSEL board was connected to the Intel/Agilent
optoelectronic board. The next step now is to test the VCSEL board with the MAXIM
transmitter board once the changes to the MAXIM board have been made.
After completion of the VCSEL testing, the next step will be to implement the
design for the photodetector circuit. The design has been completed and is shown below,
but has not yet been implemented at this time due to the fact that the Lasermate
connectorized photodetectors have not been delivered. Although the Hamamatsu unconnectorized photodetectors have been ordered and delivered, it would be easier to
implement the design using the Lasermate connectorized detectors. When using unconnectorized photodetectors additional modifications need to be made to the detector
itself in order to make it connectorized.
Figure 8. Schematic of photodetector circuit.
The resistor value was chosen using Equation 1 below.
R
1
2  f  C det
(Eq. 1)
Cdet is the capacitance of the un-connectorized photodetector. The Hamamatsu data
specifications indicated that the typical capacitance was 1.5pF. This requires a resistance
of 53.1 . The capacitors were chosen for the circuit based upon their frequency
response at 1.25 GHz. According to the data on Murata’s website, the ideal value for both
of the capacitors are .01uF.
Conclusion
At this juncture the overall project is halfway complete. The main objectives
from this point on are to implement and test the photodetector circuit mentioned in this
paper, and to design VCSEL and photodetector Printed Circuit Boards (PCB). These
boards are designed using the SuperPCB layout package. Based upon the layouts created
using this package a board is etched leaving the traces needed to implement the VCSEL
and photodetector circuits. Once these boards are implemented they will be tested to
verify a passable eye pattern.