Srikala Kambhampati
December 6, 2002
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Chapter 1 INTRODUCTION
Abstract: The main aim of this project is to design a 2 to 4 line Decoder/Demultiplexer.
This circuit takes a single data input and one or more address inputs, and selects which of
multiple outputs will receive the input signal. The same circuit can also be used as a
decoder, by using the address inputs as a binary number and producing an output signal
on the single output that matches the binary address input .The Decoder circuit takes an
n-bit binary number and produces an output on one of 2n output lines. It is therefore
commonly defined by the number of addressing input lines and the number of data output
lines. This particular circuit takes two-bit input and a select input and gives a four-bit
output.
Software Used:

LEDIT to draw the layout of the circuit

PSPICE to simulate the circuit
Schematic: The schematic for the 2-to-4 line Decoder/Demultiplexer is as shown in
Figure 1.
Fig 1 Schematic for 2-to-4 line Decoder/Demultiplexer
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December 6, 2002
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Chapter 2
This chapter discusses the basic circuits used in order to build a 2-to-4-line
decoder circuit.
nMOSFET and pMOSFET are the two basic transistors that are used in the vlsi design.
The schematic of the nMOSFET is as shown in figure 2.1
The schematic of the pMOSFET is as shown in figure 2.2
The layout of the nMOSFET and pMOSFET are drawn in L-EDIT using the following
steps:
Steps for drawing the layout of nMOSFET:
The following steps are used for creating the nFET.
1. Construct an ACTIVE
2. Surround ACTIVE with NSELECT. The intersection of the two is called ndiff.
3. Create a POLY box that crosses completely over the ndiff and extends beyond
the active area. This creates the gate.
The nMOSFET is as shown in Fig 2.3.
Fig 2.3 Layout of nMOSFET
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December 6, 2002
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The final layout diagram is checked for errors by running the design rule checker.
To execute a DRC on the layout, we have to choose DRC from the special window in the
menu bar. This action opens a dialog box that allows specifying the format of the output.
The above layout diagram is checked for DRC, this action will check for the different
rule violations such as the minimum spacing and the minimum width. In Fig 4 there were
no such violations therefore the final layouts of the MOSFET has been created.
The DRC file for the nMOSFET is as shown in figure 2.4
Fig 2.4 DRC for nMOSFET
Steps for drawing the layout of pMOSFET:

Create an NWELL region for the pMOSFET.

Construct an Active box/polygon for the transistor.

Surround ACTIVE with PSELECT. The intersection of the two is pdiff.

Draw a POLY box over pdiff for the gate.

Provide an ACTIVE and NSELECT box within NWELL for the n-well contact
(to VDD).
The n+ contact formed in the last step is needed to bias the n-well to the power supply
voltage.
The pMOSFET is as shown in Fig 2.5
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December 6, 2002
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Fig 2.5 pMOSFET
The final layout diagram is checked for errors by running the design rule checker.
The above layout diagram is checked for DRC, this action will check for the different
rule violations such as the minimum spacing and the minimum width. In Fig 2.5 there
were no such violations therefore the final layouts of the MOSFET has been created.
The DRC file for the nMOSFET is as shown in figure 2.6
Fig 2.6 DRC for PMOSFET
from the schematic of the final circuit we can see that the 2-to-4 line
decoder/Demultiplexer basically consists of 4 nand gates and 8 inverters. So this project
can be divided into two parts one that consists of three input nand gate and the other that
consists of an inverter.
Inverter:
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December 6, 2002
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A CMOS inverter is an ingenious circuit, which is built from a pair of nMOS and pMOS
transistors operating as complimentary switches. The schematic of the inverter is as
shown in fig 2.7
Fig 2.7 Schematic of inverter
The main advantage of the CMOS inverter above the other solutions is that it is
exclusively built of the transistors operating as switches without any other passive
elements like capacitors and resistors.
From the Fig 2.7 we can see that the pMOS transistor is connected between Vdd
and output whereas the nMOS is connected between the output and ground.
The principle of operation of the inverter is as follows:
For small values of input voltage the nMOS transistor is switched off whereas the
pMOS transistor is switched on and connects the output mode to Vdd.
For large values of input voltage the pMOS transistor is switched off whereas the
nMOS transistor is switched on and connects the output mode to ground.
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December 6, 2002
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The layout of nMOS and pMOS transistors is saved as cells and they are called as
instances while drawing the layout of inverter. The layout of the inverter is as shown in
fig 2.8
Fig 2.8 Layout of the Inverter
The input to the inverter is given at the poly-poly contact i.e., at the gate of the transistors
and the output is taken at the common source of the inverter. The drain of the pMOS is
connected to VDD whereas the drain of the nMOS is connected to the ground.
The layout of the inverter is then checked for the design rule errors by running the
DRC. The DRC of the inverter is as shown in the fig 2.9
Fig 2.9 DRC for Inverter
CMOS layout drawings performed in L-Edit can be used to generate SPICE-Compatible
circuit file listings using the EXTRACT option in the Special window of the menu Bar.
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December 6, 2002
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We have to specify morbn20.ext file in the working folder for the extract definition
file.The extraction program translates the objects on the layout into devices, producing a
text file in SPICE format. In order to use the element descriptions we must provide
appropriate .MODEL statements.
Running the Extract on the MOSFET shown in Fig 2.9 produces the following
SPICE file:
Fig 2.10 SPC file of the inverter
From the SPC file we can see that there are two transistors in it one nMOS transistor and
the other pMOS transistor .The PMOS transistor is named as M1 and the NMOS
transistor is named as M7.The SPC file also gives the nodes of the transistor.
In order to simulate the transistor we need to add voltage sources to inputs, a model file
to define the nMOS and pMOS transistor models, and then simulation commands to
specify the type and duration of the simulation and the values to plot.
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December 6, 2002
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For the inverter designed above we need to define VDD and Gnd voltages. In order to
do this we need to specify the voltage source and then its constant value .For VDD, the
statement is:
VDD 12 0 DC 5
Which means that a voltage source named VDD is applied between 12 and 0 with a DC
value of 5.
Now the statement for the Gnd would be
VSS 13 0 DC 0
Which means that a voltage source named VSS is applied between nodes 13 and 0 with a
DC value of 0.
The inverter has one input and let us call that input as Va, for the input the statement
would be
VA 10 0 PULSE (0 5 5ns 0.1ns 0.1ns 5ns 10ns)
This specifies that a 100MHz square waveform of 5V, with both rise and fall times of
0.1ns and delayed by 5ns is used.
After adding all these statements we need to add the transistor model parameters .The
model parameter are available in SCNA.SPC file. We need to copy the contents into
INV.SPC file. Then we need to specify the type of simulation. So we need to add the
following statement
.TRAN 2ns 20ns
Which means that the maximum step is 2ns and the simulation length is 20ns.
Finally we need to specify the output so we need to add the following statement
.PROBE
The .END statement is the last statement in the file. This file is then saved with .CIR
extension. The .CIR file is as follows
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December 6, 2002
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Fig 2.11 CIR file of the inverter
After the completion of the CIR file we need to simulate the inverter. The simulated file
of the inverter is as follows:
The simulated output is shown in fig 2.12
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December 6, 2002
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Fig 2.12 Output of the inverter
From the fig 2.12 we can see that when the input is low the output is high and when the
input is high the output is low. Their exists some spikes in the output which is because of
the parasitic capacitance present in the circuit.
Three input nand gate: The nand gate output will be low when all the inputs are high
otherwise the output of the nand gate would be high. A three input nand gate consists of
three nMOS and three pMOS transistors. The nMOS transistors are connected in series
whereas the pMOS transistors are connected in parallel. The schematic of the three input
nand gate is as shown in the figure 2.13.
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December 6, 2002
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Fig 2.13 Schematic of three input nand gate
The layout of the nMOS and pMOS transistors, which is saved as cells, is again used to
design the three input nand gate.
The layout of the three input nand gate is as shown in the following figure
2.14 Layout of three input nand gate
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December 6, 2002
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From the layout of the nand gate we can see that the pMOS transistors are
connected in parallel whereas the nMOS transistors are connected in series. But design
makes it very complicated to design the three input nand gate. So I went for an alternative
design of the nand gate, which is simple when compared to this. The alternative layout is
shown in figure 2.14
Fig 2.15 Layout of the three input nand gate
From the above layout we can see that this is a simple design when compared to the
previous layout. Here the inputs are given at the poly and the output is taken from the
common source. The nand gate layout is then checked for the design rule violation using
the DRC. The DRC file of the three input nand gate is as shown in figure 2.16.
Fig 2.16 DRC file of three input nand gate
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December 6, 2002
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After the design rule check the circuit is extracted in the same procedure as explained for
the inverter. The extracted file of the three input nand gate is as shown in the figure 2.17
Fig 2.17 SPC file of three input nand gate
After the extraction of the three input nand gate the inputs and the voltage sources have to
be added to this file. The voltage source VDD and the Gnd is added as the following
statements
VDD 15 0 DC 5V
Which means that a voltage source named VDD is applied between 15 and 0 with a DC
value of 5.
VSS 16 0 DC 0V
Which means that a voltage source named VSS is applied between nodes 16 and 0 with a
DC value of 0.
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December 6, 2002
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After adding the voltage sources inputs have to be specified. If we assume that the three
inputs would be A B and C where s is the select signal. The statements that are to be
added to the SPC file are
VA 3 0 PULSE (0 5 5ns 0.1ns 0.1ns 5ns 10ns)
This specifies that a 100MHz square waveform of 5V, with both rise and fall times of
0.1ns and delayed by 5ns is used.
VB 6 0 PULSE (0 5 4ns 0.1ns 0.1ns 5ns 10ns)
This specifies that a 100MHz square waveform of 5V, with both rise and fall times of
0.1ns and delayed by 4ns is used.
VC 8 0 PULSE (0 5 10ns 0.1ns 0.1ns 10ns 20ns)
This specifies that a 50MHz square waveform of 5V, with both rise and fall times of 0.1ns
and delayed by 5ns is used.
After the addition of all the statements the SPC file is saved as .CIR file which is as
shown in fig 2.18
Srikala Kambhampati
December 6, 2002
Fig 2.18 CIR file of nand gate
The nand gate is then simulated and the simulated output is as shown in fig 2.19
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December 6, 2002
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Fig 2.19 Output of the nand gate
2-to-4 Demultiplexer/Decoder circuit
A decoder is a combinational circuit with n inputs and at most 2n outputs. Its
characteristic property is that for every combination of input values only one output will
be equal to 1 at the same time. Decoder has a wide variety of applications in digital
technology. They may be used to route input data to a specified output line, as for
example in addressing core memory, where input data re to be stored in a specified
memory location. They serve for some code conversions or they may be used for data
distribution i.e., demultiplexing. The same circuit can also be used as a demultiplexer, by
using the select signal. So out of the three inputs of the nand gate we consider two signals
A and B be to be third input S to be the select signal.
The inverter and the nand gate layouts that were described previously are stored as
cells, which are called as instances in the final project. The layout of the 2-to-4
Demultiplexer is as shown in figure 2.20. Each inverter consists of two transistors and
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December 6, 2002
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each three input nand gate consists of six transistors, as the final layout has 4 three input
nand gates and 8 inverters ,the total number transistors used are