JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 14, 567-586 (1998)
A Logical Fault Model for Library Coherence Checking
Shing-Wu Tung and Jing-Yang Jou*
Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300, Taiwan, R.O.C.
E-mail: swtung@vlsi.ccl.itri.org.tw
*Department of Electronics Engineering
National Chiao Tung University
Hsinchu, 300, Taiwan, R.O.C.
E-mail: jyjou@bestmap.ee.nctu.edu.tw
A library is the basis of modularized design flow. Most operations of CAD tools are based
on cell definitions in a library. In this paper, we first give a definition of a library and describe the
complexity of library verification. A unified automatic test pattern generation and verification
environment is then proposed. The amount of library data coherence checking is reduced to
functional simulation on different views of the cells. In order to reduce the number of test vectors
and the amount of simulation time, a Port Order Fault (POF) model is proposed. Using the POF
model and the sensitized path approach [1] to generate test vectors, the proposed approach could
effectively reduce the complexity of the functional test vectors from O(2n) to O(n) for cells with n
inputs. Using the POF model, the test sequence can also detect timing inconsistency under the
verification environment .
Keywords: verification, fault model, port order fault (POF), cell library, coherence checking, test
pattern generation.
1. INTRODUCTION
In this paper, a library is defined as the basic building blocks for IC design. As the
complexity of IC design has increased, design verification has become a bottleneck in the design
cycle.
The cell-based design methodology is the classical way to shorten the
product-development time and manage the complexity of chips. Use of predesigned and
preverified logic blocks can effectively increase a designer's productivity and reduce the design
time. However, verification still takes more time than does design, especially for complex chips.
As faults resulting from the interaction between blocks are difficult to detect at the block level,
most of the verification time is used in detecting such faults. Fixing the faults which occur in the
blocks at the final integrated design level requires an excessively large amount of simulation time
and debugging effort if blocks are predesigned without complete assurance that they are error-free.
Received October 31, 1997; revised March 18, 1998.
Communicated by Jin-Yang Jou.
Therefore, it is crucial to verify that the "predesigned and preverified" blocks have consistence
behavior through out the design steps. If the faults in cell-based design blocks are eliminated in
the library creation stage, the integrated design verification efforts can focus on chip functionality
and timing specifications rather than building blocks.
This paper focuses on coherence checking instead of the functional testing of cell libraries.
The complexity of library verification is described in section 2. In order to reduce the number of
vectors needed for coherence checking, we will introduce a Port Order Fault (POF) model in
section 3 based on the likely occurrence of design faults in different library views. Based on the
POF model, the vectors generated by the sensitized path approach can detect functional and timing
data inconsistency among different library views. If we are only interested in functional
inconsistency checking, the test set can be further minimized. Details are given in section 4.
Section 5 discusses how the sequential cell can be verified based on POF. A brief comparison
between the stuck fault model and the port order fault model is given in section 6. Section 7
presents experimental results.
2. COMPLEXITY OF LIBRARY VERIFICATION
Each object (or cell) in a library has different views for different CAD tools as shown in Fig. 1.
Each view has a different representation and serves a different purpose in the design flow. For
example, the symbol view is used to represent the schematic design; Verilog-HDL or VHDL views
are typically used for logic simulation. All of the views are linked together to form a single object.
In order to insure the integrity of the library, we not only have to deal with cell functionality and
timing verifications, but also need to check for data coherence among different views. This makes
library verification very complex.
Fig. 2 shows the basic idea of library verification. All of the cell views (specific CAD tool
libraries) are translated into netlists for cell simulation. Test vectors are generated from the truth
table in the data sheet exhaustively [2]. Data in each specific CAD tool library are compared with
expected values in data sheets by simulation.
The complexity of complete library verification is approximately on the order of O(K * 2 n).
The constant value K depends on the number of views, the number of design corners and the
number of cells in a library. The variable n is the maximum number of inputs of library cells.
3. THE PORT ORDER FAULT MODEL
Definition 1. A cell has inputs, X = {xi : 1  i  n}, and outputs, Y = {yi : 1  i  m.
positive integers).
(m and n are
Definition 2. The function of cell (k) is FK (X) = {f1 (X), f2 (X), … , fm (X)}, where X is the inputs
and each fi (X) is the boolean function of each output yi.
Definition 3. The delay of cell (k) is DK (X) = {d1 (X), d2 (X), … , dm (X)}, where X is the inputs
and each di (X) is the set of delays from X to each output yi.
In this section, a few typical library faults will be reviewed first, and the Port Order Fault
(POF) model will then be proposed so that the size of the test set can be reduced.
Based on our working experience, ten of the most commonly occurring design faults among
the different views of all libraries are shown in Fig. 3. They are inconsistent port sequence,
inconsistent pin name, inconsistent cell name, functional fault, inconsistent I/O type, syntax error,
inconsistent timing data, primitive input without drive, floating nets and nets with multiple active
drivers.
Definition 4. A design fault of a library cell (K) is detectable if FK(X)  FK'(X) or DK(X)  DK'(X),
where X are inputs and FK' and DK' represent the function and the delay of the corresponding faulty
cell.
Theoretically, the complete test set used to detect all the functional design faults of a cell in a
library consists of all the possible combinations of its inputs. Performing such exhaustive testing
is a very time consuming process when cells to be verified have lots of inputs. The timing check
of a cell requires another test sequence set which enables the timing events to pass through the
sensitized paths from inputs to outputs. The situation becomes worse when we have to consider
data coherence between various cell views in a library.
In this paper, we will focus on data coherence checking instead of functional testing. We
assume that one of the library views has been verified using the exhaustive test set. Based on the
POF model, the test sequence of a timing check can be used to detect all of the commonly
occurring design faults in a circuit without redundant logic. The test set can be further reduced
when timing checking is of no concern.
Before we introduce the POF model, let us discuss a concept related to test generation first.
Definition 5. A sensitized path from an input xi to an output yi of a cell is a path on which an event
can propagate from input xi to output yi.
The vectors of all the sensitized paths of a cell can be generated as follows. First, evaluate
the cell output function to built the reduced ordered binary decision diagram (ROBDD) [3]. The
sensitized paths from input xi to output yj can be found as the shortest path from the root, through
the vertex xi to the leaf yj = 0 and the shortest path from the root, through the vertex xi to the leaf yj
=1. For the example depicted in Fig. 4, the sensitized paths from each input to each output are
shown in Table 1. The symbol x can be arbitrarily assigned to either 1 or 0. The input sequence
{(A, B, C): 101, 001, 011, 001, 101, 000} is one of the test sequences used to enable all of the
sensitized paths in cell OA21.
Definition 6. A sensitized path test sequence of a library cell is a collection of test vectors which
can enable all of the sensitized paths of a library cell.
Algorithm 1 is the pseudo code for generating the sensitized path test sequence.
Algorithm 1:
sensitized_vector (I_list, O_list) {
input I_list; /* input port list */
input O_list; /* output port list */
foreach out in (O_list)
Building ROBDD G with the corresponding output function;
foreach in in (I_list)
P0 = shortest_path (G (rootinout =0));
/* Find the shortest path P0 from root to leaf out = 0 which traverses vertex in */
P1 = shortest_path (G (rootinout =1));
/* Find the shortest path P0 from root to leaf out = 1 which traverses vertex in */
/* T (inout) enables the sensitized path from input in to output out. */
T (inout) = {the labels on the path P0, the labels on the path P1};
Return (T (inout));
end /* end of foreach in */
end /* end of foreach out */
}
Example 1: The test sequence enables all sensitized paths for 2-input AND gate, AN2 (Z, A, B),
with output function Z = A * B is {(A, B): 1, 1}. The symbol  means an input value change
event. Then, the sensitized path test sequence can be represented as {(A, B): 01, 11, 10, 11}.
Definition 7. The type Ⅱ POF has at least one output yi misplaced with an input xk; that is, cell
inputs X' = {x1, … ,xi,…, yi,…, xn, 1  i  n , i  k} and outputs Y' = {y1, … ,yi,…, xi,…, ym, 1  i  m ,
i  j}.
Fig. 5 shows two examples of the type I POF. Under this fault model, the output of a faulty
cell will float. Any functional test vector can be applied to detect this type of fault. For example,
the cell AN2 in Fig. 5 has output Z misplaced with input IB, which can be modeled as this type of
fault. The faulty AN2 output port acts like a net without a drive. The output, thus, has
high-impedance or an unknown value, depending on the modeling level. Therefore, this fault type
can be detected by applying any one of the vectors in the test set.
Definition 8. The type II POF has at least two misplaced input ports; that is, the inputs of the
fault free cell are X = {x1, …,xi, …,xj,…,xn, i  j} but the inputs of the faulty cell are X' =
{x1, …,xj, …,xi,…,xn, i  j}.
Fig. 6 shows a type II POF. Port order inconsistency only occurs between input ports.
Algorithm 1 can be used to generate test vectors and detect multiple type II POFs in O(n) time
complexity. For example, the order-sensitive test sequence {(IA, IB, IC): 110, 010} enabling the
sensitized path from input IA to output Z in Fig. 6 can detect the POF between IA and any other
inputs. The input sequence {(A, B, C): 10, 10, 00  {(A, B, C): 110, 010, 110, 100, 001,
000}can be applied to detect all possible POFs occurring in AOI21. A special case should be
taken into consideration when port IA and IB in Fig. 6 are exchanged. The faulty cell has the
same output function as the fault free cell; however, the delays from different inputs to the output
may be different. If the number of functional equivalent port order faults of this kind is significant
not negligible, they should also be detected by applying the sequence of sensitized path vectors.
Definition 9. The type III POF has at least two misplaced output ports; that is, the outputs of the
fault free cell are Y = {y1,…,yi,…,yj,…, ym, i  j} but the outputs of the faulty cell are Y' =
{ y1,…,yj,…,yi,…, ym, i  j}.
Fig. 7 shows a type III POF. Port order inconsistency occurs between output ports.
Lemma 1.
The vector enabling the sensitized path from input xi to output yi of a cell can detect
a type I POF between xi and yi and all of the type II POFs between xi and the other input ports.
Proof: According to the definition, a sensitized path is a directed path which is established from
one input to one output. The vector enabling the sensitized path from input port xi to output port yj
not only checks the path direction, but also validates the order of xi in terms of input ports and the
order of yj in terms of output ports. The type I POF misplaces the input port with the output port,
and the type II POF has inconsistent port order between inputs. Therefore, both types of POFs are
detectable by the associated sensitized path vector.
Lemma 2.
Checking only one output port at a time can reduce the type III POF to type II POF.
Proof: A cell with m outputs is logically equivalent to m cells with single outputs. Each output
port has its own output function and delay equations (or delay tables). Therefore, a type III POF
can be reduce to several type II POFs.
Lemma 3.
Proof:
The type II POF is dominated by the other two types of POFs.
This follows from the conclusions of Lemma 1 and 2.
Theorem 1: The sensitized path test sequence that enables all the sensitized paths of a cell can
detect all of the POFs.
Proof:
This also follows from the conclusions of Lemma 1 and 2.
4. TEST GENERATION OF MINIMUM FUNCTIONAL TEST SET
Typically, timing data inconsistency faults will not cause fatal design errors if the accumulated
timing faults do not violate the design timing budget. In addition, complete timing data checking
among libraries with different simulation conditions carried out by comparing the simulated cell
timing delay with the expected data is very time consuming. Therefore, if we are more interested
in detecting POFs with functional faults only, the minimum functional test set can be further
derived by solving the column covering problem typically found in two-level logic optimization
algorithms.
The algorithm to generate all the possible POFs of a cell is shown below.
Algorithm 2:
genPOFlist (Plist, io_list) {
/* output all combinations of io_list with prefix Plist */
Input: io_list; /* I/O port list */
Input: Plist;
if (length (io_list) = = 1) then
/* return port list POF when io_list has only one element */
POF = Plist + io_list;
return(POF);
else
foreach io in (io_list)
/* Move io from io_list to Plist and recursively call genPOFlist to generate all possible
combinations of the reduced port list */
genPOFlist (Plist+io, io_list-io);
end
endif
}
The recursive algorithm genPOFlist can generate all of the possible port order faults of a cell.
The cell I/O-port list is defined as the input variable io_list. The input parameter Plist is a
temporary variable used to keep track of the current POF and will be initialized to an empty set.
The symbol + means concatenation of two lists, and the function length counts the number of
elements in a list. Removing variable io from io_list is expressed as io_list - io.
Example 2: There are 23 possible POFs for a complex gate OA21 (Z, A, B, C) with output
function Z = (A+B) * C. Table 2 shows all of the possible POFs of OA21 and the corresponding
output values of each faulty cell under all possible input vectors. The symbol z means
high-impedance. Five of those POFs are type II and the others are type I. Because the 'output' of
a type I faulty cell is actually an input port, no matter which input vector is applied, a cell with a
type I POF always responds with a z at the 'output'. The cell output delay depends on the
sequence of input vectors applied and the transition of the output state. One of the possible
sensitized path test sequences for detecting all of the type II POFs in OA21 is separately shown in
Table 3, where the initial output state is assumed to be 1. The delays of input A transition to
output Z with state changes from logic low to high and from logic high to low are represented as
tAZLH and tAZHL, respectively. The vector set T (A  Z) which can enable a sensitized path from
input A to output Z is {(A, B, C): 1x1, 001}. Referring to Table 1, T (B Z) is {(A, B, C): 011,
001}and T (C  Z) is {(A, B, C): 1x1, xx0}, where x means 1 or 0. The sensitized test sequence
for OA21 can be formed as the union of T (A  Z), T (B  Z) and T (C  Z). For example, {(A,
B, C): 001, 101, 001, 011, 000, 101} is one of the test sequences for detecting all of the possible
POFs in OA21 if each x is assigned to 0. No matter which vector set is selected, all of the POFs
are detectable if DOA21(T)  D'OA21(T). If it is acceptable to skip some of the timing data
consistence checking, the test set can be reduced to {(A, B, C): 001, 101, 011, 000} by removing
the repeated vectors in the sensitized path test sequence (Table 3). The minimum functional test
set {(A, B, C): 110} can be derived by solving the column covering problem to cover all rows with
bold characters in Table 2. The overall algorithm is shown below.
Algorithm 3:
minFuncTest (T, POFlist) {
/* compute min. functional test set from fault list */
Input: T;
/* T is the input test set as shown in Table 2 and Table 3. */
Input: POFlist; /* POF list */
Removing all Type I POFs from POFlist;
Reducing any Type III POF in POFlist to several Type II POFs;
Let k = the number of faults and n = the number of input vectors;
=F(Ti)));
/* U is the universe of detectable faults */
U=;
/* The min. functional test set is derived by minimizing the terms in U. */
minFuncTest = Logic_Minimization(U);
}
Starting with the exhaustive functional test set, Algorithm 3 can always find the optimal
solution. If one of the sensitized test sequences is used as the input of minFuncTest, it will take
less time to get the final result, but the solution may be local optimal because not all of the possible
sensitized test sets are processed.
5. COHERENCE CHECKING FOR SEQUENTIAL CELL
Definition 10. The state transition graph of a sequential cell is a directed graph G (V, E). The
vertices V of the graph correspond to the states (also the outputs) of the finite state machine (FSM).
The edges E correspond to the state transitions.
In this section, we will discuss the properties of sequential POF. The concept of POF can be
extended to include the sequential cell . The major difference between combinational and
sequential library coherence checking is that an initialization sequence is needed to bring the
sequential cell to a known state before the POF test sequence is applied.
The function of a sequential cell is a FSM, which can be represented by its state transition
graph. Fig. 8 is the state transition graph of a D-type flip-flop (DF0). The symbol R means
clock rising edge. L represents logic 0, H represents logic 1 and - represents don't care. Any
irredundant logic fault in the sequential cell will cause some changes in its state transition graph [4].
A state transition is corrupted if its output label, its destination state, or both are faulty.
Algorithm 4 shows the typical way to verify the full functionality of a sequential cell. The
complexity of Functional_Verification for a sequential cell with N states and M transitions is O(N
* M). Theoretically, M is equal to 2n, where n is the number of inputs. However, we can exploit
the don 掐 care conditions to reduce the number of transitions in the state transition graph. For
example, the number of outward transitions for each vertex in Fig. 8 is 3 rather than 4.
Algorithm 4:
Functional_Verification (SEQcell) {
input SEQcell; /* sequential cell */
generate state transition graph G(V, E)
foreach vertex v in G(V, E)
foreach edge e in G(V, E)
set initialize state = v;
apply e as input stimulus;
compare cell outputs with expected results;
end
end
}
Definition 11. A path in a graph G is a Euler path if every edge of G appears once and only once
in the path.
The length of a test sequence for sequential cell functional verification produced by algorithm
4 is N * (2 * M). M vectors bring the cell to the initial state before the other M vectors are applied
to test all the input combinations. If a Euler path [5] can be found in the graph, we only need to
apply the initialize vector once so the test length can be reduced to N * M + 1.
Theorem 2: The type II sequential POF only changes the input labels on the edges without
changing the structure of the state transition graph. The number of vertices and the number of
edges of the faulty cell are the same as those of the fault free cell. In other words, the faulty edge
will transfer the state to the wrong destination state.
Proof: According to definition 8, the type II POF misplaces inputs. As the POF is a structural
fault model for library coherence checking rather than a functional fault model, the functionality of
the sequential cell is assumed to be fault-free and, only the order of the I/O ports is affected by the
POF. Therefore, the faulty cell has the same state transition graph structure as does the fault free
cell. Only the input labels related to the misplaced ports on the edges are changed.
Example 3: The state transition graph (STG) of DF3, D-type flip-flop with asynchronous set and
reset, is shown in Fig. 9. A type II POF of DF3 with set (SN) and reset (RN) port order exchanged
is shown to the right of the fault free STG. Both the fault free and faulty cells have the same STG
structure. The dotted lines on the faulty STG show the edges which go to incorrect destination
states. By applying either vector in the test set {(CK, D, RN, SN): --LH, --HL} after the
initialization sequence, the fault can be detected.
The symbol -LH for a sequential cell correspond
to x01 in previous examples.
The sequential type I POF causes the cell to not be initialized. Therefore, both the output
label and the destination state of the corresponding edge are wrong. The type III POFs have the
wrong output labels. The type II POF changes the input label on the edges so that some
transitions on the graph will go to wrong destination states. Therefore, the type II POF, dominated
by the other two types of POFs, is also applicable to sequential cells.
Based on the properties of sequential POF, algorithm 5 shows the way a POF test sequence is
generated. The complexity of seqPOF_sequence is approximately on the order of O(N * n).
The exponential term M in algorithm 4 now becomes a linear term n, where n is the number of
inputs.
Algorithm 5:
seqPOF_sequence (SEQcell) {
input SEQcell; /* sequential cell */
generate state transition graph G(V, E);
foreach vertex V in G(V, E);
remove cyclic edges;
end
find the shortest path to visit every vertex and traveling through every edge;
}
Example 4: A cell with n inputs and m outputs has (n + m)! -1 POFs. There are 720 port order
combinations of DF3 shown in Fig. 9. One is fault free, and the other 719 are faulty. The test set
{(CK, D, RN, SN): RHHH, RLHH, --HL, --LH}is one of the possible test sequences for detecting
all the POFs of DF3. Exhaustive Verilog simulation was done to verify that the sequential POF
test sequence generated by algorithm 5 is complete; that is, the generated test sequence can detect
all the POFs of DF3. Due to the large number of faults, Table 4 only lists a few typical POFs of
DF3 and the number of faults detected by the POF test sequence. The symbol T in the "Verf.
LOG" column means the Verilog-HDL logic models with typical design parameters that were tested.
The number in (Pass, Fail) following the symbol T represents the counts of passed and failed test
items. For example, T(10, 8) means 10 test items passed and 8 test items failed. The test item
count is proportional to the test length and the number of checking items per clock cycle.
Depending on the properties of the simulator, many type I POFs, such as F718' and F719' in Table 4,
can be detected during the compilation phase without applying any vector. Only the fault free cell
passes all test items, and all the POFs are detectable by the POF test sequence.
6. COMPARISON OF STUCK AT FAUL AND PORT ORDER FAULT
The stuck at fault (SAF) is the fault model that has been most widely studied and used. On
the other hand, the port order fault belongs to the group of pin-fault models. In this section, we
will compare SAF and POF.
Typically, the SAF assumes that a faulty signal line remains at a fixed logic level. The POF
assumes that a faulty cell has at least two misplaced I/O ports. Both the SAF and POF are
structural fault models. They both assume that components are fault-free, and that only
interconnections can be faulty. However, the POF only considers faults which occur in I/O ports.
Depending on the number of faults which occur simultaneously in a circuit, SAFs is further divided
into two classes : single stuck faults (SSF) and multiple stuck faults (MSF). For a circuit with N1
I/O ports and N2 internal nets, there are a total of 2 (N1 + N2) SSFs and 3 - 1 MSFs. According to
definitions 7, 8 and 9, there are at least two misplaced ports for each type of port order fault. In
other words, multiple faults are inherent in the POF. The POF assumes that N2 internal nets are
fault free; therefore, there is a total of N1! possible POFs.
Definition 12. A set of inputs which detect all possible POFs is called a complete POF test
sequence.
Theorem 3: In an irredundant circuit, any SAF occurring in an I/O port is detectable by the
complete POF test sequence.
Proof: According to definition 5 and theorem 2, the complete POF test the fault effect through a
sensitized path to a primary output. Therefore, any SAF which occurs in an I/O port is detectable
by the complete POF test sequence.
The SAF does not accurately reflect all the faults of the library design. A test set generated
based on the SAF wastes much time testing improbable faults. Moreover, the SAF is not
applicable to detection of timing inconsistency faults. Example 2 has shown that the minimum
functional test set of OA21 under the POF only needs one vector, and the test length is six for the
complete POF test sequence for detecting all functional and timing inconsistency faults in OA21.
Therefore, for reduction of the library coherence checking time, the POF model is more suitable
than the SAF model.
7. EXPERIMENTAL RESULTS
The Data Coherence Check Agent, DACCA, is a unified library design verification
environment. To ease debugging and maintenance, DACCA is imple-mented in shell scripts in a
UNIX environment. DACCA consists of three major functions which are: generating a test set
from the truth table description file, invoking logic simulation and comparing simulation output
results with expected values. Fig. 10 depicts the implementation details of DACCA. The total
execution time for library consistency checking is proportional to the number of vectors, the
number of cell views and the number of design corners in a cell library. Only the Verilog-HDL
logic models with typical design parameters are used as the experimental library because the
number of cell views and the number of design corners depend on the CAD flow rather than the
fault model. Speedup is defined as the quotient of the execution time of full functional test
vectors divided by the execution time of the sensitized path test set for POFs.
The experimental results were measured using a SPARCstation-20 with 128 MB memory.
The verification statistics for three CCL libraries are shown in Table 5. The speedup of the
consistency checking based on the POF model was about 1.67 to 1.96. The length of the test set
used to verify the function of a n-input cell is exponentially proportional to the number of inputs of
the cell as shown in Fig. 11. To get the benefit of the POF model, the input number has to be
larger than 2. The ideal speedup under the POF model are 1.33 for 3-input cells and 2.0 for
4-input cells. The deviation between the experimental results and the ideal cases is related to the
distribution of input numbers in a library. Fig. 12 shows the histogram of the input numbers in the
CL05T5V library. About 62% of the 275 cells in the CL05T5V library have fewer than 4 inputs.
In addition, all of the sequential cells (36 cells with inputs  4) in the library were tested using the
minimum number of functional vectors which could not be further reduced using the POF model.
Only about 25% of the cells in the CL05T5V library showed significant speedup (speedup  2)
under the POF model. This explains why the speedup was nearly 2 in our experiment. The
speedup can be dramatic for libraries which have many cells with many inputs.
8. CONCLUSIONS
Verification usually requires a tremendous amount of effort in any design cycle. In this paper,
a few typical library faults have been presented and a Port Order Fault model proposed. The
DACCA library verification environment with the POF model can potentially reduce the number of
library verification vectors from O(2n) to O(n). Experimental results show that the verification
time can be reduced dramatically.
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Shing-Wu Tung（佟興旡）is an IC design engineer at Computer and Communications
Laboratories (CCL/ITRI),Taiwan. He is also working toward the Ph.D. degree in electronic
engineering at National Chiao Tung University. Tung received a B.S. degree in electrical
engineering from National Cheng Kung University, and an M.S. degree in computer science and
information engineering from National Chiao Tung University in 1987 and 1989, respectively. In
1989, he joined the Industrial Technology Research Institute. His current research activities focus
on design automation and verification of ASIC library. Other areas of interest include computer
architecture, CPU design, and VLSI system implementation. He is a member of IEEE.
Jing-Yang Jou（周景揚）is a professor in the Department of Electronics Engineering at
National Chiao Tung University, Taiwan. He has worked at GTE Laboratories and Bell
Laboratories. His research interests include behavioral and logic synthesis, VLSI designs and
CAD for low power, design verification, synthesis and design for testability, and hardware/software
codesign. Jou received a B.S. degree in electrical engineering from National Taiwan University,
and M.S. and Ph.D. degrees in computer science from the University of Illinois at
Urbana-Champaign. He is a member of Tau Beta Pi and a recipient of the distinguished paper
award of the IEEE International Conference on Computer-Aided Design, 1990. He served as the
technical program chair of The Asia-Pacific Conference on Hardware Description Languages
(APCHDL'97) and has published more than 50 journal and conference papers.