Project Title
Project Title
Sub-Title
Editor
Version 1.0
Status
Reviewed
Supervisor
Date reviewed
Approved
Supervisor
Date approved
TSEK06 VLSI Design Project
Documentation Responsible
Group XX
LIPs

Project Guide
LiTH
PROJECT IDENTITY
Project group nr, Year/Semester,
Linköping University, ISY, Electronic Devices
Name
Name 1
Name 2
Name 3
Name 4
Name 5
Name 6
Responibility
Customer relations (CUS)
Documentation
responsible (DOC)
Design responsible (DES)
Test responsible (TST)
Implementation
responsible (IMP)
Project leader (PL)
Phone
Phone nr.
Phone nr.
E-mail
aaaaa123@student.liu.se
bbbbb456@student.liu.se
Phone nr.
Phone nr.
Phone nr.
ccccc789@student.liu.se
ddddd012@student.liu.se
eeeee345@student.liu.se
Phone nr.
fffff678@student.liu.se
E-mail list for entire group: e-mail list for entire group
Webpage: address to group webpage
Customer: Customer description, 581 00 LINKÖPING,
phone to customer. 013-11 00 00, fax: 013-10 19 02, e-mail address
Customer contact person: name, phone, e-mail address
Course responsible: Atila Alvandpour, atila@isy.liu.se
Supervisor: name, phone, e-mail address
TSEK06 VLSI Design Project
Documentation Responsible
Group XX
ii
LIPs

Project Guide
LiTH
Create a table of contents here
How you create a table of contents:
Insert -> Reference -> Index and Tables …
(Formally; Tab leader: ……; Show levels: 3, Show page numbers: check; Right
align page numbers: check)
-> OK
Table of Contents
Table of Contents ....................................................................................................... 3
1
2
Introduction ......................................................................................................... 5
Time Plan ............................................................................................................ 5
2.1
3
Activities ................................................................................................................................. 5
References .......................................................................................................... 6
TSEK06 VLSI Design Project
Documentation Responsible
Group XX
iii
LIPs

Project Guide
LiTH
Documentation history
Version Date
Changes made
TSEK06 VLSI Design Project
Documentation Responsible
Done by
Group XX
iv
Reviewed
LIPs

Check List for Tollgate 4 / Milestone 8
LiTH
2016-02-17
1 Introduction
Text…
Figure 1-1: Figure caption text
Figure text should always be used for figures and pictures.
Add figure text by righ clicking on the figure/picture and select Caption
Select label: Figure
Change the formatting style to Figure Caption
TABLE 1-1: TABLE CAPTION TEXT
A
3
Item
B
5
C
7
Table text describing all tables should always be used.
Add table caption by selecting the table and choosing:
Insert  Reference  Caption…
Select label: Table
Change the formatting style to TABLE CAPTION
2 Time Plan
2.1 Activities
In Table 2-1 below are some of the activities that are recommended to have in the time plan for tollgate 1-3
(TSEK06).
TABLE 2-1: LIST OF BASIC ACTIVITIES IN THE PROJECT.
Nr
Activities
Description
1
Time plan
Make time plan and keep it up to date
2
Pre-study
Litterateur search, find good potential implementation
structures.
3
High level modeling
Create a high level model for a design that functions according
to the specification
4
Status report for TG1
5
Transistor block design
Create schematics of all blocks and verify that they work
according to specification.
6
Chip designs on transistor level
Complete schematic of chip and verification
TSEK06 VLSI Design Project
Documentation Responsible
Group XX
v
LIPs

Check List for Tollgate 4 / Milestone 8
LiTH
2016-02-17
Nr
7
8
9
10
11
12
13
14
Activities
Status report for TG2
Block layout and verification
PAD frame
Chip core layout
Generate fill and additional layers and
Tape-Out
Verification plan
Project report
Project presentation
Description
DRC, LVS, verification
Layout and decide which pads to use, DRC and LVS.
Global place and route, DRC, LVS, verification.
Decide what should be measured and how.
3 References
Write a reference list like the example below.
[1].
Rabaey Jan M., Chandrakasan Anantha, and Nikolic Borivoje, Digital Integrated Circuits – A design
perspective, Second edition, Prentice Hall, 2003, ISBN 0-13-120764-4.
TSEK06 VLSI Design Project
Documentation Responsible
Group XX
vi
LIPs
