When Lanthana Meets Silicon
H. Wong1, 2 and B. L. Yang2
1
Department Electronic Engineering, City University of Hong Kong, Hong Kong SAR
2
Department of Information Sciences and Electronic Engineering, Zhejiang University, China
E-mail: heiwong@ieee.org
Introduction
Lathanum oxide or lanthana (La2O3) has been considered as one of the most promising
subnanometer-thick (in the sense of equivalent oxide thickness or EOT) gate dielectrics for future
nanoscale CMOS device applications [1-4]. The rare earth lanthanum has features of lower valance
electron energy, larger oxygen chemical potential, and smaller electronegativity when compared
with silicon and the lanthana film is often found to have poorer material properties than the
conventional silicon dioxide. When lanthana is brought into contact with the silicon substrate,
several adverse effects occur [1]. In this talk, the material interactions at the La2O3/Si interface will
be discussed in detail. The electrical characteristic degradations — originated from the material
interaction between lanthana and silicon — of (Al, W)/La2O3/Si capacitors will be reviewed. Finally,
some measures, such as chemical doping, interface buffering, and oxygen chemical potential
control, which have shown to be the effective ways for improving the interface properties, will be
highlighted.
Discussion
Due to the large oxygen chemical potential of lanthanum, the La2O3 films prepared by
sputtering and even by atomic layer deposition (ALD) technique are often found to have high
amount of oxygen vacancies. The oxygen vacancies do not only result in the significant gate oxide
charge trapping and abnormal gate leakage under normal operation of MOS devices, they also
involve in the interface reaction. It was found that the oxygen vacancies can assist in the substrate
Si out-diffusion to the lanthana films and a thick silicate layer between the lanthana/Si interface can
be produced when the lanthana/Si structure underwent some thermal treatments. Lanthanum has
smaller electronegativity, the interfacial La atoms can react with the substrate Si and they may also
be diffused into the Si substrate. The La-Si silicide bonds are interface trap precursors and a
trivalent La atom can be an acceptor for the Si substrate. These effects result in the channel mobility
degradation. Several processes, such as doping, oxygen chemical potential control, buffer layer,
have been proposed to suppress these interface reactions [4-6] and the process details and their
major consequences will be given in the talk.
Conclusions
The electrical properties, such as leakage current, charge trapping, high-field stressing stability,
and channel mobility, of MOS transistors using lanthana as the gate dielectric are strongly governed
by the interface interactions between lanthana and silicon. The electrical properties can be improved
by introducing trace amount of nitrogen and aluminum to the interface. A buffer layer such as
alumina, lanthanum silicate, or silicon oxynitride which inhibits the interface interaction can also
improve the material and electrical properties significantly. Oxygen chemical potential control
which mainly involves in the removal of the oxygen vacancy in the bulk of lanthana would suppress
the out-diffusion of substrate silicon and results in some better electrical properties.
Acknowledgement
This work was supported by SRG Project No.7002761 of City University of Hong Kong.
References
[1] H. Wong, Nano CMOS Gate Dielectric Engineering, CRC Press, (2012).
[2] H. Wong and H. Iwai, Microelectron. Eng., 83, 1867-1904, (2006).
[3] H. Wong, H. Iwai, K. Kakushima, B. L. Yang, and P. K. Chu, J. Electrochem. Soc., 157, G49-G52 (2010).
[4] B. Sen and H. Wong, J. Molina, H. Iwai, J. A. Ng and K. Kakushima, C. K. Sarkar, Solid State Electron., 51, 475-480 (2007).
[5] H. Wong, B. L. Yang, K. Kakushima, H. Iwai, IEEE Electron Device Lett., 32, 1002-1004, (2011).
[6] H. Wong, B. L. Yang, S. Dong, H. Iwai, K. Kakushima, and P. Ahmet, Appl. Phys. Lett. 101, 233507 (2012).