Nationality: Japan
Business Address:
Frontier Research Center
Tokyo Institute of Technology
4259 Nagatsuta, Midori-ku, Yokohama, 226-8502, Japan
Tel: +81-45-924-5471, Fax: +81-45-924-5584
E-mail: iwai.h.aa@m.titech.ac.jp or h.iwai@ieee.org
Education:
The University of Tokyo, 1992 Doctor of Engineering, Electrical Engineering
The University of Tokyo, 1972 B.E. Electrical Engineering
Professional Experiences:
2012.12.22-(a period of three years starting from 22 nd December)
D.J. Gandhi Distinguished Chair Professor, Indian Institute of Technology
Bombay
2012.6.19-present Adjunct professor, Hangzhou University of Electronic Science and
Technology
2012.5-2017.4
Honorary Professor, Institute of Microelectronics, Chinese Academy of Sciences
2011.12.22-(a period of four weeks starting from 22 th December)
D.J. Gandhi Distinguished Chair Professor, Indian Institute of Technology
Bombay
2011.11.2-2013.11.1 Guest Professor, Ningbo Institute of Material Technology and Engineering,Chinese Academy of Sciences
2011.9.1-2015.3.31
Visiting Professor, University of Tsukuba
2010.12.22-(a period of one month starting from 22 th December)
D.J. Gandhi Distinguished Visiting Professor, Indian Institute of Technology
Bombay
2010.5.1-2013.4.30
Visiting Professor, University of Science and Technology of China
2010-2013 Visiting Professor, East China Jiaotong University
2008-2011 Visiting Professor, Xinjiang University
2008-2010 Adjunct Professor, Xiangtan University
2008.12.25-(a period of one month starting from 25 th December)
D.J. Gandhi Distinguished Visiting Professor, Indian Institute of Technology
Bombay
2007.12.28-( a period of one month starting from 28 th December)
1
D.J. Gandhi Distinguished Visiting Professor, Indian Institute of Technology
Bombay
2006-2008 Consultant Professor, Huazhong University of Science and Technology
2006-present Adjunct Professor, Lanzhou Jiaotong University
2002 – present Professor, Frontier Collaborative Research Center,
Tokyo Institute of Technology
2001 – 2004 Research Planning Officer, Research Strategy Office,
Tokyo Institute of Technology
1999 – present Professor, Interdisciplinary Graduate School of Science and Engineering,
Tokyo Institute of Technology
1996 – 1999 Chief Specialist, Microelectronics Engineering Lab., Toshiba Corp.
1989 – 1996 Senior Research Scientist, ULSI Research Labs., Toshiba Corp.
1979 – 1989 Deputy manager, Semiconductor Engineering Device Lab.,
Toshiba Corp.
1983 – 1984 Visiting Scholar, IC Lab., Stanford University
1977 – 1979 NEC-Toshiba Information System Inc.
1973 – 1979 Researcher, IC Lab., R & D Center, Toshiba Corp.
Development of the first generation of Toshiba's NMOS LSI technology
Development of several generations of high density static and dynamic RAM's and logic LSI's.
Research on device physics, process technologies related to small-geometry MOSFETs
Development of sub-50 nm CMOS technologies
Development of RF BiCMOS and RF CMOS technologies.
Research on Emerging Technologies: High–k gate insulator, plasma doping, Ni salicide, RF CMOS modeling, Ge transister, GaAs MOSFETs, GaN Power MOSFETs. Re-RAM, Diamond semiconductor devices.
Professional Academic Activities:
[1] 1995 Guest Editor, IEEE Trans. on ED, Special Issue
[2] 1994-1999 Member, Organizing Committee, IEEE, SISPAD
[3] 1996, 1999 Publication Chair, IEEE/JSAP SISPAD'96 and '99 (Int Conf. Simulation of Semicond.
Proc.and Dev.)
[4] 1997, 1999 ECS Symp on ULSI Science and Technology
[5] 1998 Guest Editor, IEEE Trans. on ED, Special Issue
[6] 1998 Moderator, Rump session, Symp on VLSI Tech/Circ
[7] 1998 Moderator, Rump session, SSDM
[8] 1996-1998 Subcommittee Chair, IEEE BCTM
[9] 1999 Member, Advance Workshop on ‘Frontiers in Electronics’ Committee
[10] 1999 Co-organizer, ECS Symp on ULSI Process Integration '99
[11] 1995-2000 Elected Member, IEEE EDS AdCom
[12] 1995,1996,1999,2000 Member, Committee, IEEE, IEDM, Mar.1995, 1998 Guest Editor,
Special Issues on IEEE Trans on Election Devices
[13] 1995, 1996, 1999, 2000 Program Committee Member, IEEE IEDM'95, '96, '99, '00
(International Election Devices Meeting)
[14] 1994-1999 Editor, IEEE EDS Newsletter
[15] 1997,2000 Program Vice Chair, IEEE MIEL '00 and97 (International Conference on
2
Microelectronics)
[16] 1999 Session Organizer, IEEE WOFE'99 (Advanced Workshop on 'Frontiers in Electronics)
[17] 1999 Publication Chair, IEEE BCTM'99 (Bipolar/BiCMOS Circuit and Technology Meeting)
[18] 1999,2000 Program Committee Member, ESSDERC'99, '00 (European Solid-State Device
Research Conference)
[19] 1997-2000 Member, International Committee, IEEE ASDAM*98
[20] 1999,2001 International Advisor IEEE IPFA '99, '01 (International Symp. on Physical and
Failure Analysis of ICs)
[21] 2000 Program Vice Chair, IEEE BCTM'00 (Bipolar/BiCMOS Circuit and Technology Meeting)
[22] 2001 EDS Vice President, IEEE (Electron Devices Society, The Inst. of Electrical &
Electronics Eng.)
[23] 2001 Technical Program Chair, IEEE BCTM'01 (Bipolar/BiCMOS Circuit and TechnologyMeeting)
[24] 2001 Technical Program Chair, IEEE IWGI (Int. Workshop on Gate Insulator)
[25] 2001 Executive Committee Chair, IEEE IWJT (Int. Workshop on Junction Technology)
[26] 2001 Technical Program Cochair, IEEE ICSIT (Int. Conf. on Solid-State and Integrated
Circuit Technology)
[27] 2001 Technical Program Subcommittee Chair (CIR) IEEE IEDM (International Electron
Devices Meeting)
[28] 2001 Executive Committee member ECS Electronics Division
[29] 2001 Vice Editor-in-Chief, IEICE Trans. on Electronics
[30] 2001 CMOS and Interconnects Reliability, IEEE, IEDM
[31] 2001 Moderator, Rump session, Symp on VLSI Tech/Circ
[32] 2001,2002 Chair, JEITA Ultra-Low Power Operation Integrated Systems Technical
Committee (JEITA: Japan Electronics and Information Technology Industry Association)
[33] 2001 Guest member, LETI, Micro electronics and micro technology CST
[34] 2002 Program Committee Member, IEEE RAB/TAB Section/Chapter Support
[35]
Committee ’02 (Regional Activities Board/Technical Activities Board)
[36] 2002 Committee Member, ECS Symp on Silicon Technology
[37] 1994-present Distinguished Lecturer, IEEE EDS
[38] 1995-present Member, Investigation Committee, the Institute of Electrical Engineers
[39] 1996-present Program Vice Chair, IEEE MIEL
[40] 1996-2015 Member, IEEE EDS Regions/Chapters Committee
[41] 1996-2005 Regional Editor, Microelectronics Reliability
[42] 1998-2003 Asian Coordinator, Advance Research Workshop on Future Trend in
Microelectronics
[43] 1999-present Committee Member, ECS Symp on ULSI Process Integration
[44] 2000-2002 Co-organizer, IEEE Japan Ultra-Small Integrated Devices Investigation
Committee (IEE Japan: the Institute of Electrical Engineers of Japan)
[45] 2000-2002 Chair, IEEE EDS Regions/Chapters Committee
[46] 2000-present Coeditor-in-chief, IJHSES(International Journal of High Speed Electronics and
Systems)
[47] 2001-present Executive Committee member, ECS Electronics Division
[48] 2002-present Member, ECS DS&T Governing Body
[49] 2002 Co-Chair, Technical Program Committee, 2 nd ECS- International Silicon Technology
Conference, Tokyo, Japan, September 11-14, 2002
[50] 2002 Executive Committee Member, 2 nd ECS- International Silicon Technology Conference,
Tokyo, Japan, September 11-14, 2002
[51] 2002 Organizer, ECS 202 nd Meeting, First International Sympo. on High Dielectric Constant
Materials:Materials Science, Processing, Reliability,& Manufacturing Issues Oct. 21-22, 2002,
Salt Lake City, Utah, USA
[52] 2002-2009 Organizer, ECS Meeting, Sympo. on High Dielectric Constant Materials and Gate
Stacks
[53] 2002-2003 Vice President, IEEE EDS
[54] 2002-2003 Member, IEEE RAB/TAB Section Chapter Support Committee
[55] 2002 General Chair, IEEE BCTM
[56] 2002-2003 Editor-in-Chief, IEICE Trans. on Electronics
[57] 2003-2004 Member(Responsible for Technical Symposia Grants), IEEE RAB/TAB
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Section/Chapter Support Committee
[58] 2002-2003 Member, National Institution for Academic Degrees and University Evaluation
[59] 2003 Member, Sub-committee for Device Reliability, Technical Program Steering
Committee (TPSC), IPFA
[60] 2003 Organizer, 203 rd ECS Meeting, Sympo. on ULSI Process Integration III, Apr. 28-29,
2003, Paris, France
[61] 2003 Organizer, 204 th ECS Meeting, Sympo. on Second International Symposium on High
Dielectric Constant Materials: Materials Science, Processing, Reliability, and Manufacturing
Issues, Oct. 13-16, 2003, Orland, Florida, USA
[62] 2003-present International Committee Chair, 2003 IMFEDK (The 2003 International
Meeting for Future of Electron Devices, Kansai )
[63] 2003 Member, IEEE TAB Awards and Recognition Committee
[64] 2002-present Member, Andrew Grove Award Committee
[65] 2003-2008 Member, DIMES, DIMES Scientific Council
[66] 2004-present Member, IEEE TAB
[67] 2004-2005 President, IEEE EDS
[68] 2004 Co-general chair, ICSTST 2004
[69] 2004 Co-program chair , WOFE 2004
[70] 2004 Program co-chair The 4 th International Workshop on Junction Technology:2004,
Shanghai, China, March 15-16, 2004
[71] 2004 E-MRS Spring Meeting, Session IV chair
[72] 2004 Co-organizer, 206 th ECS Meeting, the First International Sympo on Dielectrics for
Nanosystems:Materials Science, Processing, Reliability and Manufacturing, Oct. 4-7,
Honolulu, Hawai,
[73] 2004 Co-Organizer, 206 th ECS Meeting, SiGe: Materials, Processing, and Devices, Oct.4-8,
Honolulu
[74] 2004 General Co-Chairs:7 th International Conference on Solid-State and Integrated Circuits
Technology, Beijing, China
[75] 2004 International Advisory Committee Member, ECS-ISTC2004, Shanghai, China,
September15-17, 2004
[76] 2004-present General Chair, IWJT 2005
[77] 2005 Division Chair, Executive Committee, The 2005Semi-ECS-ISTC, Shanghai, China,
March15-17, 2005
[78] 2005 Semiconductor Technology (ISTC 2005)Assistant Editor
[79] 2005 Co-organizer, 207 th ECS Meeting, Sympo. on Advanced Gate Stack, Source/Drain, and
Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment, May
16-18, 2005, Quebec City Canada
[80] 2005 General Chair The 5 th International Workshop on Junction Technology:(IWJT) 2005,
June7-8,2005, Osaka, Japan
[81] 2005 Advisory Chair, The 9th Workshop and IEEE EDS Mini-colloquia on NAnometer
CMOS Technology Nanoelectronics Workshop in Japan, Yokohama, Japan, Oct. 25, 2005
[82] 2005 Co-Organizer, 208 th ECS Meeting, Third International Sympo. on High Dielectric
Constant Gate Stacks III, Oct. 17-20, 2005, Los Angeles, California, USA
[83] 2005 General Chair, The 9th Workshop and IEEE EDS Mini-colloquia on NAnometer CMOS
Technology Nanoelectronics Workshop in Japan, Yokohama, Japan, Oct. 25, 2005
[84] 2006 General Chair, The International Workshop on Nano CMOS (IWNC), Mishima, Japan,
Jan. 30-31
[85] 2006 Division Chair, ISTC2006, Shanghai, China, March 21-13, 2006
[86] 2006 General Co-Chair, The 6 th International Workshop on Junction Technology:(IWJT) 2006,
Shanghai, China, May 15-16, 2006
[87] 2006 Lanzhou Jiaotong University, Adjunct Professor
[88] 2006-2007 Junior Past President, IEEE EDS
[89] 2006-2007 Member, IEEE EDS Fellow Committee
[90] 2006-2008 Member, IEEE EDS TAB Society Review Committee
[91] 2006 Organizer, ECS 209 th Meeting, Sympo. on Dielectrics for Nanosystems
MaterialsScience:, Processing, Reliability, and Manufacturing II, May 8-10, 2006,
Denver,USA
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[92] 2006, Organizer, 209th ECS Meeting, 10 th International Symposium on Silicon Materials
Science andTechnology, May 10-11, 2006, Denver, USA
[93] 2006 Co-Program Chair , ICSICT2006, Shanghai, China, Oct.22-27
[94] 2006 Organizer, 210 th ECS Meeting, Sympo. on Advanced Gate Stack, Source/Drain, and
Channel Engineering for Si-Based CMOS 2: New Materials, Processes, and Equipment, Oct.
30-Nov.2, 2006, Cancun, Mexico
[95] 2006 Organizer, 210 th ECS Meeting, Sympo. on High Dielectric Constant Gate Stacks 4, Oct.
30-Nov.2, 2006, Cancun, Mexico
[96] 2006-2007 IEEE EDS Nominations and Elections Committee Chair
[97] 2007 Co-Chair, ISTC2007, Shanghai, China, March 18-20, 2007
[98] 2007 Organizer, 211 th ECS Meeting, Sympo. on Advanced Gate Stack, Source/Drain, and
Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment 3, May
7-9, 2007, Chicago, Illinois
[99] 2007 Steering Committee member, 2007 International Workshop on Electron Devices and
Semiconductor Technology, June 3-4, 2007, Beijing, China
[100] 2007 Advisory Committee Chair, The 7 th International Workshop on Junction Technology
2007, June 8 - 9, 2007 Kyoto, Japan
[101] 2007 Organizer, 212 th ECS Meeting, Sympo. on High Dielectric Constant Materials and Gate
Stack 5, Oct. 8-10, 2007, Washington, DC
[102] 2007 Organizer, 212 th ECS Meeting, Sympo. on ULSI Process Integration 5, Oct. 8-11, 2007,
Washington, DC
[103] 2008 DIMES Scientific Council
[104] 2008 Co-Chair, ISTC2008, March 15-17, 2008, Shanghai, China
[105] 2008 Advisory Committee Chair, The 8 th International Workshop on Junction Technology
2008, May 15- 16, 2008 Shanghai, China
[106] 2008 Technical Co-Chair, 213 th Meeting ECS Sympo on Dielectrics for Nanosystems III:
Materials Science, Processing, Reliability and Manufacturing, May 18-23, 2008, Phoenix,
Arizona, USA
[107] 2007 Program chair , WOFE 2007
[108] 2008-2009 IEEE EDS Fellow Committee Chair
[109] 2008-2009 IEEE EDS Award Committee member
[110] 2008-2009 IEEE EDS Senior Past President
[111] 2009 Advisory Committee Member, ISTC2009, March 17-19, 2009, Shanghai, China
[112] 2009 Advisory Committee Chair, The 9 th International Workshop on Junction Technology
2009, June 11- 12, 2009, Kyoto, Japan
[113] 2009IEEE EDS Distinguished Service Award Committee
[114] 2009-2011 IEEE Frederik Philips Award Committee
[115] 2009 IEEE Divisison 1 Delegate-Elect/Director-Elect
[116] 2009-2011 ECS Individual Membership Committee member
[117] 2009-2015 IEEE EDS VLSI Technology and Circuits Committee
[118] 2010-2011 IEEE Division 1 Delegate/Director
[119] 2010 Steering Committee Advisor, ISTC2010, March 18-19, 2010, Shanghai, China
[120] 2010 Advisory Committee Chair, The 10 th International Workshop on Junction Technology
2010, May 10- 11, 2010 Shanghai, China
[121] 2011-2014, ESSDERC Technical Program Committee
[122] 2011-2013 IEEE Fellow Committee
[123] 2011 Program Chair, IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 26), February 9, 2011, Tokyo, Japan
[124] 2011 Technical Program Chair, Taiwan-Japan Workshop on “Nano Devices”, March 3, 2011,
Yokohama, Japan
[125] 2011 Advisory Committee, International Workshop on THE FUTURE OF NANO
ELECTRONICS RESEARCH AND CHALLENGES AHEAD(IWNANO 2011), December
26-28, 2011, Tamilnadu, India
[126] 2012 Strategic Planning Committee of the Fellow Committee
[127] 2012.5.1-2015 IEEE David Sarnoff Award Committee
[128] 2012.8.31
ECS Japan Section/Section Officers Second Vice-Chair
[129] 2013 IEEE EDSSC 2013 International Advisory Committee
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[130] 2013- Editorial Board, SCIENCE CHINA
[131] 2013- Advisory Board of the journal “Facta Universitatis:Series Electronics and Energetics”
[132] 2013.1-2017.12
Member of Advisory Committee, SCIENCE CHINA Information Sciences
Honors:
2011 The Institute of Electrical Engineers of Japan(IEEJ) Fellow
2009 The Institute of Electronics, Information and Communication Engineers(IEICE)
Fellow
2009
The Commendation for Science and Technology by the Minister of
Education, Culture, Science and Technology, Prizes for Science and
Technology, Development Category Award
2008
IEEE 2008 EDS Distinguished Service Award
2007
7th Yamazaki-Teiichi Prize
2007 IEEE BCTM Award
2007 JSAP Fellow
2005 Local Commendation for Invention
from Japan Institute of Invention and Innovation
2002 JSAP Award for the best paper
2001 IEEE EDS J.J. Ebers Award
1998 Electronics Award from Electronics Society, IEICE
1997
1994
1994
1990
Elected to IEEE Fellow
IEEE EDS Paul Rappaport Award
Grand Prize of the 4th Nikkei BP Technology Awards
Local Commendation for Invention
1968 from Japan Institute of Invention and Innovation
Nagoya Mayor Award
Society Memberships:
Membership:
Fellow, IEEE
Fellow, The Japan Society of Applied Physics
Fellow, The Institute of Electronics, Information and Communication Engineers, Japan
Member, Electrochemical Society
Member, The Institute of Electronics, Information and Communication Engineers, Japan
Member, The Institute of Electrical Engineers of Japan
6
7
Biography:
Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of
Tokyo and worked in the research and development of integrated circuit technology for more than
25 years in Toshiba. He is now a professor of Frontier Collaborative Research Center and Dept. of
Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering,
Tokyo Institute of Technology, Yokohama, Japan. Since joining Toshiba, he has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. He has also been engaged in research on device physics, process technologies, and T-CAD related to small-geometry MOSFETs and high speed bipolar transistors.
He has authored and coauthored more than 600 journal and conference papers.
He has served on many committees of conferences and editors of journals, as well as a member of many evaluation committee of public organizations. For example, the President of the IEEE EDS, an elected member of the IEEE EDS AdCom, an editor of IEEE EDS Newsletter, a guest editor of
IEEE Trans. on Electron Devices, and an editor of the Proceedings of ECS Symp. on ULSI Process
Integration. He is now the IEEE Division 1 Director for 2010-11 and ECS Individual Membership
Committee member for 2009-2011. He serves as a visiting professor for many Chinese and Indian universities.
His awards include Local Commendation for Invention from Japan Institute of Invention and
Innovation (1990, 2005), Grand Prize of Nikkei BP Technology Awards (1994), IEEE EDS Paul
Rappaport Award (1994), IEICE ES Electronics Award (1998), IEEE EDS J.J.Ebers Award (2001), and JSAP Award for the best paper (2002), IEEE BCTM Award (2007),
Yamazaki-Teiichi Prize
(2007), IEEE 2008 EDS Distinguished Service Award (2008), The Commendation for
Science and Technology by the Minister of Education, Culture, Science and Technology,
Prizes for Science and Technology, Development Category Award (2009).
His current research interests are Nano CMOS and Emerging Technologies: High–k gate insulator,
Si Nanowire MOSFETs, plasma doping for ultra-shallow junctions, Ni salicide, RF CMOS modeling, and Ge transisters.
Dr. Iwai is, a fellow of IEEE, a member of Electrochemical Society, a fellow of the Japan Society
Applied Physics, and a fellow of the Institute of Electronics, Information and Communication
Engineers of Japan.
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Recent Patent List
[1] H. Iwai, Y. Nishi, “Method of manufacturing semiconductor devices” Unites States Patent
4,327,476, filed Nov. 28, 1980, patented May 4, 1982
[2] H. Iwai, “Method of etching, refilling and etching dielectric grooves for isolating micron size regions,” Unites States Patent 4,394,196, filed July 13, 1981, patented July 19, 1983
[3] S. Sawada, H. Iwai, S. Maeda, , “Method for fabricating a semiconductor device,” Unites
States Patent 4,410,375, filed Oct. 2, 1981, patented Oct. 18, 1983
[4] H. Iwai, “Semiconductor wafer with alignment marks and method for manufacturing semiconductor device,” Unites States Patent 4,418,467, filed June 18, 1982, patented Dec. 6,
1983
[5] H. Iwai, “Method for fabricating semiconductor device,” Unites States Patent 4,419,813, filed
Nov. 27, 1981, patented Dec. 13, 1983
[6] H. Iwai, “Method of manufacturing a self-aligned U-MOS semiconductor device”, United
States Patent 4,455,740, filed Sept. 29, 1982, patented Jun. 26, 1984
[7] H. Iwai, “Method for manufacturing a semiconductor device”, United States Patent 4,491,486, filed Sept. 16, 1982, patented Jan. 1, 1985
[8] H. Iwai, “Wafer exposure method and apparatus”, United States Patent 4,500,615, filed Sept.
22, 1982, patented Feb. 19, 1985
[9] M. Konaka, H. Iwai, Y. Nishi, “MOS Semiconductor device and method of manufacturing the same,” Unites States Patent 4,523,213, filed July 9, 1982, patented June 11, 1985
[10]
H. Iwai, “Method of manufacturing a semiconductor device for forming a deep field region in a semiconductor substrate” Unites States Patent 4,532,696, filed Mar. 16, 1983, patented Aug.
6, 1985
[11] S. Kameyama, S. Shinozaki, H. Iwai, “Method of manufacturing semiconductor device,”
Unites States Patent 4,532,701, filed Aug. 19, 1982, patented Aug. 6, 1985
[12] S. Maeda, H. Iwai, “Semiconductor device and method of manufacturing the same,” Unites
States Patent 4,560,421, filed Oct. 2, 1981, patented Dec. 24, 1985
[13]
H. Iwai, H. Ohtsuka, “Treatment process for semiconductor wafer”, United States Patent
4,575,466, filed Dec. 28, 1983, patented Mar. 11, 1986
[14] H. Iwai, “Semiconductor substrate and method for manufacturing semiconductor device using the same”, United States Patent 4,597,166, filed Feb. 8, 1983, patented July 1, 1986
[15] H. Iwai, “Wafer exposure apparatus”, United States Patent 4,613,230, filed Apr. 30, 1982, patented Sept. 23, 1986
[16] S. Kameyama, S. Shinozaki, H. Iwai, “Method of forming isolation regions containing conductive patterns therein”, United States Patent 4,615,103, filed May 28, 1985, patented Oct.
7, 1986
[17] S. Kameyama, S. Shinozaki, H. Iwai, “Method of forming isolation regions containing conductive patterns therein”, United States Patent 4,615,104, filed May 28, 1985, patented Oct.
7, 1986
[18] H. Iwai, “Semiconductor device with self-aligned gate structure and manufacturing process thereof”, United States Patent 4,737,831. filed Sept. 11, 1986, patented Apr. 12, 1988
[19] S. Maeda, H. Iwai, “Semiconductor device having a semiconductor substrate with a high impurity concentration”, United States Patent 4,755,863, filed Aug. 15, 1986, patented July 5,
1988
[20] S. Maeda, H. Iwai, “Semiconductor device”, United States Patent 4,872,042, filed July 13,
1984, patented Oct. 3, 1989
[21] J. Tsujimoto, M. Matsui, H. Iwai, T. Ohtani, “Semiconductor memory device using partial decoders for redundancy, United States Patent 4,881,202. filed Dec. 29, 1987, patented Nov.
14, 1989
[22] S. Maeda, H. Iwai,” C-MOS device and a process for manufacturing the same”, United States
Patent 5,079,183, filed Jan. 6, 1989, patented Jan. 7, 1992
[23] H. Iwai, T. Morimoto, H. Momose, K. Yamabe, Y. Ozawa, “Semiconductor device with nitrided gate insulating film”, United States Patent 5,237,188, filed November 27, 1991, patented Aug. 17, 1993
[24] T. Yoshitomi, M. Saito, H. Momose, H. Iwai, Y. Ushiku, M. Ono, Y. Akasaka, H. Nii, S.
9
Matsuda, Y. Katsumata, “Semiconductor device and method of manufacturing the same”,
United States Patent 5,434,440, filed May 28, 1993, patented July 18, 1995
[25] H. Iwai, T. Morimoto, H. Momose, K. Yamabe, Y. Ozawa, “Method for fabricating semiconductor device in which threshold voltage shift and charge-pumping current are improved”, United States Patent 5,489,542, filed July 16, 1993, patented Feb. 6, 1996
[26] H. Nakajima, Y. Katsumata, H. Iwai, T. Iinuma, K. Inou, M. Kitagawa, K. Morizuka, A.
Nakagawa. I. Omura, “Semiconductor device and method of manufacturing the same”, United
States Patent 5,510,647, filed March 15, 1994, patented Apr. 23, 1996
[27] H. Nakajima, Y. Katsumata, H. Iwai, T. Iinuma, K. Inou, M. Kitagawa, K. Morizuka, A.
Nakagawa, I. Omura,” Semiconductor device and method of manufacturing the same”, United
States Patent 5,637,909, filed Jan. 2, 1994, patented Jun. 10, 1997
[28] T. Yoshitomi, M. Saito, H. Momose, H. Iwai , Y. Ushiku, M. Ono, Y. Akasaka, H. Nii, S.
Matsuda, Y. Katsumata, T. Ooguro, C. Fiegna” MOSFET with Solid Phase Diffusion”, United
States Patent 5,698,881, filed Dec. 2, 1994, patented Jun. 16, 1998
[29] T. Yoshitomi, M. Saito, H. Momose, H. Iwai , Y. Ushiku, M. Ono, Y. Akasaka, H. Nii, S.
Matsuda, Y. Katsumata,” Semiconductor device and method of manufacturing the same”,
United States Patent 5,766,965, filed Dec. 5, 1995, patented Jun. 16, 1998
[30] T. Yoshitomi, H. Iwai , M. Saito, H. Momose, T. Ohguro, M. Ono, ” Semiconductor device with side wall conductor film”, United States Patent 5,780,901, filed Jun. 30, 1995, patented
Jul. 14, 1998
[31] T. Yoshitomi, M. Saito, H. Momose, H. Iwai , Y. Ushiku, M. Ono, Y. Akasaka, H. Nii, S.
Matsuda, Y. Katsumata,” Semiconductor device having solid phase diffuiosn sources”, United
States Patent 5,898,203, filed Jul. 30, 1997, patented April. 27, 1999
[32] T. Yoshitomi, M. Saito, H. Momose, H. Iwai , Y. Ushiku, M. Ono, Y. Akasaka, H. Nii, S.
Matsuda, Y. Katsumata, T. Ooguro, C. Fiegna” MOSFET with Solid Phase Diffusion Source”,
United States Patent 5,903,027, filed Aug. 13, 1997, patented May 11, 1999
[33] T. Yoshitomi, H. Iwai, M. Saito, H. Momose, T. Ohguro, M. Ono, ” Semiconductor device and manufacturing thereof”, United States Patent 5,995,761, filed Apr. 30, 1998, patented Sept. 21,
1999
[34] H. Momose, H. Iwai, S. Saito, T. Ohguro, M. Ono, T. Yoshitomi, S. Nakamura, “MOSFET with a thin gate insulating film”, United States Patent 5,990,516, filed Sep. 13, 1995, patented
Nov. 23, 1999
[35] H. Momose, H. Iwai, S. Saito, T. Ohguro, M. Ono, T. Yoshitomi, S. Nakamura, “MOSFET with a thin gate insulating film”, United States Patent 6,229,164, filed Nov. 16, 1999, patented
May. 8, 2001
[36] H. Momose, H. Iwai, S. Saito, T. Ohguro, M. Ono, T. Yoshitomi, S. Nakamura, “MOSFET with a thin gate insulating film”, United States Patent 6,410,952, filed Apr. 9, 2001, patented
Jun. 25, 2002
Publication List
Research Papers:
[ 1] T. Inoue, S. Horiuchi, H. Iwai, H. Shimizu, T. Ishida, “Micro-probe Auger analysis of Si migration in Al metallization for LSI”, Japanese Journal of Applied Physics, Vol.15 pp.63-69 ,1976
[ 2] K. Natori, M. Ogura, H. Iwai, K. Maeguchi, S. Taguchi, “A 64k bit MOS dynamic random access memory”, IEEE Journal of Solid-State Circuits, Vol. 14, pp.482-485 , 1979
[ 3] M. Konaka, H. Iwai, Y. Nishi, “Suppression of anomalous drain current in short channel
MOSFET”, Japanese Journal of Applied Physics, Vol.18, Suppl. 18-1, pp.27-33 , 1979
[ 4] L. M. Dang, H. Iwai, Y. Nishi, S. Taguchi, “P-channel versus N-channel in MOS-ICs of submicron channel lengths”, Japanese Journal of Applied Physics, Vol.19, Suppl. 19-1, pp.107-112, 1980
[ 5] L. M. Dang, H. Iwai, “Modeling of the impurity profile in an ion-implanted layer of an
IGFET for the calculation of threshold voltages”, IEEE Transactions on Electron Devices,
Vol.28, pp.116-117, 1981
10
[ 6] K. Taniguchi, M. Kashiwagi, H. Iwai, “Two-dimensional computer simulation models for
MOSLSI fabrication processes”, IEEE Transactions on Electron Devices, Vol.28, pp.574-580 ,
1981
[ 7] H. Otsuka, K. Watanabe, H. Nishimura, H. Iwai, H. Nihira, “The effect of substrate materials on holding time degradation in MOS dynamic RAM”, IEEE ELECTRON DEVICE LETTERS,
Vol. EDL-3, No.7, pp.182-184, 1982
[ 8] H. Iwai, K. Taniguchi, M. Konaka, S. Maeda, Y. Nishi, “Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure”, IEEE Transactions on
Electron Devices, Vol.29, pp.625-630 ,1982
[ 9] H. Iwai, S. Kohyama, “On-chip capacitance measurement circuits in VLSI structures”, IEEE
Transactions on Electron Devices, Vol. 29, pp. 1622-1626, 1982
[ 10] J. Oristian, H. Iwai, J. Walker, R. W. Dutton, “Small geometry MOS transistor capacitance measurement method using simple on-chip circuits”, IEEE ELECTRON DEVICE LETTERS,
Vol.EDL-5, No.10, pp.395-397, October, 1984
[ 11] H. Iwai, H. Otsuka, Y. Matsumoto, K. Hisatomi, K. Aoki, “Comparison of intrinsic gettering and epitaxial wafers in terms of soft error endurance and other characteristics of 64k bit dynamic RAM”, IEEE Transactions on Electron Devices, Vol.31, pp.1149-1151, 1984
[ 12] H. Iwai, M. R. Pinto, C. S. Rafferty, J. E. Oristian, R. W. Dutton, “Velocity saturation effect on short channel MOS transistor capacitance”, IEEE ELECTRON DEVICE LETTERS,
Vol.EDL-6, No.3, pp.120-122, March, 1985
[ 13] J. Oristian, H. Iwai, J. Walker, R. W. Dutton, “A reply to “Comments to `Small geometry
MOS transistor capacitance measurement method using simple on-chip circuits”, IEEE
ELECTRON DEVICE LETTERS, Vol.EDL-6, No.1, pp., January, 1985.
[ 14] H. Iwai, J. E. Oristian, J. T. Walker, R. W. Dutton, “A scaleable technique for measurement of intrinsic MOS capacitance with atto Farad resolution”, IEEE Transactions on Electron Devices,
Vol. ED-32, pp.344-356, 1985
[ 15] H. Iwai, M. R. Pinto, C. S. Raffrety, J. E. Oristian, R. W. Dutton, “Analysis of velocity saturation and other effects on short channel MOS transistor capacitances”, IEEE Transactions on Computer-Aided Design, Vol.6, pp.173-184, 1987
[ 16] M. Matsui, T. Ohtani, J. Tsujimoto, H. Iwai, A. Suzuki, K. Sato, M. Isobe, K. Hashimoto, M.
Saitoh, H. Shibata, H. Sasaki, T. Matsuno, J. Matsunaga, T. Iizuka, “A 25-ns 1-Mbit CMOS
SRAM with loading-free bit lines”, IEEE Journal of Solid-State Circuits, Vol.22, pp.733-740,
1987
[ 17] Y. Hiruta, H. Iwai, F. Matsuoka, K. Hama, K. Maeguchi, K. Kanzaki, “Interface state generation under long term positive bias temperature stress for a p+ poly gate MOS structure”,
IEEE Transactions on Electron Devices, Vol.36, pp.1732-1739, 1989
[ 18] Matsuoka, H. Iwai, K. Hama, H. Itoh, R. Nakata, T. Nakakubo, K. Maeguchi, K. Kanzaki,
“Electromigration reliability for tungsten filled via hole structure”, IEEE Transactions on
Electron Devices, Vol.37, pp.562-568, 1990
[ 19] F. Matsuoka, H. Iwai, H. Hayashida, K. Hama, Y. Toyoshima, K. Maeguchi, “Analysis of hot carrier induced degradation mode on PMOSFETs”, IEEE Transactions on Electron Devices,
Vol. 37, pp.1487-1495, 1990
[ 20] Y. Toyoshima, H. Iwai, F. Matsuoka, H. Hayashida, K. Maeguchi, K. Kanzaki, “Analysis of gate oxide thickness dependence of hot carrier induced degradation in thin gate oxide nMOSFETs”, IEEE Transactions on Electron Devices, Vol.37, pp.1496-1503, 1990
[ 21] Invited Paper: M. Norishima, H. Iwai, Y. Niitsu, K. Maeguchi, “Impurity diffusion behaviors of bipolar transistor under low-temperature furnace annealing and high-temperature RTA and its optimization for 0.5μm Bi-CMOS process”, IEEE Transactions on Electron Devices, Vol.39, pp.33-40, January , 1992
[ 22] B. Baccus, T. Wada, N. Shigyo, M. Norishima, H. Nakajima, K. Inou, T. Iinuma, H. Iwai, “A study of non-equilibrium diffusion modeling; Application to rapid thermal annealing and advanced bipolar technologies”, IEEE Transactions on Electron Devices, Vol.ED-39, No.3, pp.648-661, March, 1992.
[ 23] T. Iijima, A. Nishiyama, Y. Ushiku, T. Ohguro, I. Kunishima, K. Suguro, H. Iwai, “A new contact plug technique for deep-submicron ULSIs employing selective nickel silicidation of polysilicon with a titanium nitride stopper”, IEEE Transactions Electron Devices, Vol. 40, pp.371-377, 1993
11
[ 24] M. Tsuchiaki, H. Hara, T. Morimoto, H. Iwai, “New Charge Pumping Method for Determining the Spatial Distribution of Hot-Carrier-Induced Fixed Charge in p-MOSFET's”, IEEE
Transactions Electron Devices, Vol. 40, pp.1768-1779, 1993
[ 25] M. Saito, T. Yoshitomi, H. Hara, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, H. S. Momose, Y.
Katsumata, H. Iwai, “P-MOSFET's with Ultra-Shallow Solid-Phase-Diffused Drain Structure
Produced by Diffusion from BSG Gate-Sidewall”, IEEE Transactions on Electron Devices,
Vol.ED-40, No.12, pp.2264-2272, 1993
[ 26] S. Matsuda, N. Itoh, C. Yoshino, Y. Tsuboi, Y. Katsumata, H. Iwai, “Mechanical Stress
Analysis of Trench Isolation Using a Two-Dimensional
Simulation”, IEICE
TRANSACTIONS on Electronics, Vol.E77-C, pp.124-128, 1993
[ 27] Y. Tsuboi, C. Fiegna, E. Sangiorgi, B. Ricco, T. Wada, Y. Katsumata, H. Iwai, “Monte Carlo
Analysis of Velocity Overshoot Effects in Bipolar Devices with and without an i-Layer”,
IEICE TRANSACTIONS on Electronics, Vol.E77-C, pp.174-178, 1993
[ 28] H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, H. Iwai, “Electrical Characteristics of
Rapid Thermal Nitride-Oxide Gate n- and p-MOSFET's with Less Than 1 Atom% Nitrogen
Concentration”, IEEE Transactions on Electron Devices, Vol. 41, pp.546-552, 1994
[ 29] H. S. Momose, H. Iwai, “Analysis of the Temperature Dependence of Hot-Carrier-Induced
Degradation in Bipolar Transistors for Bi-CMOS”, IEEE Transactions on Electron Devices,
Vol. 41, pp.978-987, 1994
[ 30] C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, B. Ricco, “Scaling the MOS transistor below 0.1μm: methodology, device structures and technology requirements”, IEEE
Transactions on Electron Devices, Vol. 41, pp.941-951, 1994
[ 31] T. Ohguro, S. Nakamura, M. Koike, T. Morimoto, A. Nishiyama, Y. Ushiku, T. Yoshitomi, M.
Ono, M. Saito, H. Iwai, “Analysis of Resistance Behavior in Ti- and Ni- Salicided Polysilicon
Films”, IEEE Transactions on Electron Devices, Vol. 41, pp.2305-2317, December, 1994
[ 32] T. Iinuma, N. Itoh, H. Nakajima, K. Inou, A. Matsuda, C. Yoshino, Y. Tsuboi, Y. Katsumata,
H. Iwai, “Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture”,
IEEE Transactions on Electron Devices, Vol. 42, pp.399-405, March, 1995
[ 33] H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, H. Iwai, “An Improvement of
Hot-Carrier Reliability in the Stacked Nitride-Oxide Gate n- and p-MISFET's”, IEEE
Transactions on Electron Devices, Vol. 42, pp.704-712,April, 1995
[ 34] T. Morimoto, T. Ohguro, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, I. Katakabe, H.
Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, H. Iwai, “Self-Aligned Nickel-Mono-Silicide
Technology for High-Speed Deep Submicrometer Logic CMOS ULSI”, IEEE Transactions on
Electron Devices, Vol. 42, pp.915-922, May, 1995
[ 35] H. Iwai, H. S. Momose, M. Saito, M. Ono, Y. Katsumata, “The future of ultra-small-geometry
MOSFETs beyond 0.1 micron”, Microelectronic Engineering, Vol.28 pp.147-154, June, 1995
[ 36] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, H. S. Momose, H. Iwai, “Fabrication of sub-50-nm gate length n-metal-oxide semiconductor field effect transistors and their electrical characteristics”, Journal of Vacuum Science and Technology B, Vol.13, pp.1740-1743, July-August, 1995
[ 37] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, H. S. Momose, H. Iwai, “A Study of
Hot Carrier Effects on n-MOSFET's Under High Substrate Impurity Concentration”, IEEE
Transactions on Electron Devices, Vol. 42, pp.1510-1521,August, 1995
[ 38] M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, H. Iwai, “A 40 nm gate length n-MOSFET”, IEEE Transactions on Electron Devices, Vol. 42, pp.1822-1830, October, 1995
[ 39] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, M. Saito, H. Iwai, “Realization of
High-Performance MOSFETs with gate lengths of 0.1μm or Less”, Electronics and
Communication in Japan, Part 2, Vol.79, pp.67-76, October, 1996
[ 40] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “1.5 nm
Direct-Tunneling Gate Oxide Si MOSFET's,” IEEE Transactions on Electron Devices, Vol. 43, pp.1233-1242, August, 1996
[ 41] H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, H. Iwai, “Prospects for Low-power, High-speed MPUs Using 1.5 nm Direct-tunneling Gate Oxide MOSFETs”,
Solid-State Electronics, Vol.41, pp. 707-714, May, 1997
[ 42] H. Iwai, H. S. Momose, “Technology towards low power / low voltage and scaling of
MOSFETs”, Microelectronic Engineering, Vol.39, pp.7-30, December, 1997
12
[ 43] T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. S. Momose, E. Morifuji, T. Morimoto, Y.
Katsumata, H. Iwai, “A hot-carrier degradation mechanism and electrical characteristics in of
S 4 D n-MOSFETs”, IEEE Transactions on Electron Devices, Vol. 44, pp.2053-2058,
November, 1997
[ 44] R. Fujimoto, S. Otaka, H. Iwai, H. Tanimoto, “A 1.5GHZ CMOS low noise amplifier”, IEICE
Transactions on Fundamentals, Vol.E81-A, pp.382-388, March, 1998
[ 45] H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto H. Iwai,
“Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET’s:
Uniformity, reliability, and dopant penetration of the gate oxide”, IEEE Transactions on
Electron Devices, Vol. 45, pp.691-700, 1998
[ 46] T. Ohguro, N. Sugiyama, S. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. Ono, H. Kimijima, H.
S. Momose, Y. Katsumata, H. Iwai, “Undoped epitaxial Si channel n-MOSFET grown by
UHV-CVD with preheating”, IEEE Transactions on Electron Devices, Vol. 45, pp.710-716,
1998
[ 47] T. Ohguro, K. Yamada, N. Sugiyama, S. Imai, K. Usuda, T. Yoshitomi, C. Fiegna, M. Ono, M.
Saito, H. S. Momose, Y. Katsumata, H. Iwai, “0.15-μm buried-channel p-MOSFET’s with ultrathin boron-doped epitaxial Si layer”, IEEE Transactions on Electron Devices, Vol. 45, pp.717-721, March, 1998
[ 48] M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose,
H. Iwai, “0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation”, IEEE Transactions on Electron Devices, Vol. 45, pp.737-742, March, 1998
[ 49] D. Esseni, H. Iwai, M. Saito, B. Ricco, “Non-scaling of MOSFETs linear resistance in deep submicrometer regime”, IEEE ELECTRON DEVICE LETTERS, Vol.19, pp.131-133, April,
1998
[ 50] Invited Paper: H. Iwai, “Downsizing of silicon MOSFETs beyond 0.1μm”, Microelectronics
Journal, Vol.29, pp.671-678, October, 1998
[ 51] T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. S. Momose, E. Morifuji, T. Morimoto, Y.
Katsumata, H. Iwai, “High performance of silicided silicon-sidewall source and drain (S 4 D) structure”, IEEE Transactions on Electron Devices, Vol. 45, pp.1295-1299, June, 1998
[ 52] H. S. Momose, S. Nakamura, Y. Katsumata, H. Iwai, “Application of direct-tunneling gate oxides to high-performance CMOS”, Microelectronics Reliability, Vol.38, pp.1413-1423,
September, 1998
[ 53] Invited Paper: H. Iwai, “CMOS Technology – Year 2010 and beyond”, IEEE Journal of
Solid-State Circuits, Vol.34, pp.357-366, March, 1999
[ 54] H. Nii, C. Yoshino, S. Yoshitomi, K. Inoh. H. Furuya, H. Nakajima, H. Sugaya, H. Naruse, Y.
Katsumata, H. Iwai, “An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f max
and
10-V BV ceo
for RF telecommunication”, IEEE Transactions on Electron Devices, Vol. 46,
No.4, pp.712-721, April, 1999
[ 55] T. Ohguro, H. Naruse, H. Sugaya, E. Morifuji, S. Nakamura, T. Yoshitomi, T. Morimoto, H.
Kimijima, H. S. Momose, Y. Katsumata, H. Iwai, “An 0.18-μm CMOS for Mixed Digital and
Analog Applications with Zero-Volt-Vth Epitaxial-Channel MOSFET's”, IEEE Transactions on Electron Devices, Vol.46, No.6, pp.1378-1383, July, 1999
[ 56] Invited Paper: H. Iwai, “Outlook of MOS Devices into Next Century”, Microelectronic
Engineering, Vol.48, pp.7-14, September, 1999
[ 57] T. Yoshitomi, M. Saito, T. Ohguro, M. Ono, H. S. Momose, E. Morifuji, T. Morimoto, Y.
Katsumata, H. Iwai, “Single-gate 0.15 and 0.12μm CMOS with Co salicide technology”, Solid
State Electronics, Vol.43 No.3, pp.543-546, March, 1999
[ 58] T. Yoshitomi, H. Oguma, T. Ohguro, E. Morifuji, T. Morimoto, H. S. Momose, H. Kimijima,
Y. Katsumata, H. Iwai, “A high performance 0.15μm buried channel pMOSFET with extremely shallow counter doped channel region using solid phase diffusion”, Solid State
Electronics, Vol.43, No.7, pp.1209-1214, July, 1999
[ 59] T. Yoshitomi, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, E. Morifuji, T. Morimoto, H.
S. Momose, Y. Katsumata, H. Iwai, “A study of self-aligned doped channel MOSFET structure for low power and low 1/f noise operation”, Solid State Electronics, Vol.43, No.7, pp.1219-1224, July, 1999
[ 60] H. Iwai, T. Ikoma, Y. Kado, “Overview of the ULSI Session and Chapter”, International
Journal of High Speed Electronics and Systems, Vol.10, No.1, pp.171-173, 2000
13
[ 61] T. Ohguro, M. Saito, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H.
Iwai, “Thermal Stability of CoSi
2
Film for CMOS Salicide”, IEEE Transactions on Electron
Devices, Vol.47, No.11, pp.2208-2213, November, 2000
[ 62] T. Ohguro, M. Saito, E. Morifuji, K. Murakami, K. Matsuzaki, T. Yoshitomi, T. Morimoto, H.
S. Momose, Y. Katsumata, H. Iwai, “Power Si-MOSFET Operating with High Efficiency
Under Low Supply Voltage”, IEEE Transactions on Electron Devices, Vol.47, No.12, pp.2385-2391, December, 2000
[ 63] J.-S. Goo, C.-H. Choi, F. Danneville, E. Morifuji, H. S. Momose, Z. Yu, H. Iwai, T. H. Lee, R.
W. Dutton, “An Accurate and Efficient High Frequency Noise Simulation Technique for Deep
Submicron MOSFETs”, IEEE Transactions on Electron Devices, Vol.47, No.12, pp.2410-2419,
December, 2000
[ 64] H. S. Momose, S. Nakamura, T. Ohguro, T. Yoshitomi, E. Morifuji, T. Morimoto, Y.
Katsumata, H. Iwai, “Hot-carrier reliability of ultra-thin gate oxide CMOS”, Solid-State
Electronics, Vol.44, pp.2035-2044, November,2000
[ 65] H. S. Momose, T. Ohguro, E. Morifuji, H. Sugaya, S. Nakamura, H. Iwai, “Ultrathin Gate
Oxide CMOS with Nondoped Selective Epitaxial Si Channel Layer”, IEEE Transactions on
Electron Devices, Vol.48, No.6, pp.1136-1144, June, 2001
[ 66] H. S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito, H. Iwai, “Cutoff Frequency and Propagation Delay Time of 1.5-nm Gate Oxide CMOS”, IEEE Transactions on Electron
Devices, Vol.48, No.6, pp.1165-1174, June, 2001
[ 67] Invited Paper: H. Iwai, T. Ohguro, H. Ohmi, “NiSi salicide technology for scaled CMOS”,
Microelectronic Engineering, Vol.60, pp.157-169, February, 2002
[ 68] Invited Paper: H. Iwai, S. Ohmi, “Silicon integrated circuit technology from past to future”,
Microelectronics Reliability, Vol.42, pp.465-491, April, 2002
[ 69] H. Iwai, S. Ohmi, “Trend of CMOS downsizing and its reliability”, Microelectronics
Reliability, Vol.42, No.9-11, pp.1251-1258, September-November, 2002
[ 70] H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, H. Iwai, “Ultrathin Gate
Oxide CMOS on (111) Surface-Oriented Si Substrate”, IEEE Transactions on Electron
Devices, Vol.49, No.9, pp.1597-1605, September, 2002
[ 71] J.O.Borland, V.Moroz, H.Wang, W.Maszara, H.Iwai, “High-tilt implant and diffusion-less activation for lateral graded S/D engineering”, Solid State Technology,Vol.2003-06, pp.52-58,
2003
[ 72] F. Lime, K. Oshima, M. Casse, G. Ghibaudo, S. Cristoloveanu, B. Guillaumot, H.
Iwai, “Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dieletric” ,
Solid-State Electronics, Vol.47, pp.1617-1621, October, 2003
[ 73] J.Tonotani, T.Iwamoto, F.Sato, K.Hattori, S.Ohmi, H.Iwai, “Dry etching characteristics of TiN film using Ar/CHF
3
, Ar/Cl
2
, and Ar/BCl
3
gas chemistries in an inductively coupled plasma” ,
Journal of Vacuum Science and Technology B (JVST B), Second Series, Vol.21, No.5, pp.2163-2168, September-October, 2003
[ 74] H.Iwai, “CMOS downsizing toward sub-10nm”, Solid-State Electronics, Vol.48, pp.497-503,
September, 2003
[ 75] C.Ohshima, J.Taguchi, I.Kashiwagi, H.Yamamoto, S.Ohmi, H.Iwai, “Effect of surface treatment of Si substrates and annealing condition on high-k rare earth oxide gate dielectrics” ,Applied Surface Science, Vol.216 pp.302-306, June, 2003
[ 76] H.Nohira, T.Shiraishi, T.Nakamura, K.Takahashi, M.Takeda, S.Ohmi, H.Iwai, T.Hattori,
“Chemical and electronic structures of Lu2O3/Si interfacial transition layer”, Applied Surface
Science,Vol.216, pp. 234-238, June, 2003
[ 77] S.Ohmi, C.Kobayashi, I.Kashiwagi, C.Ohshima, H.Ishiwara, H.Iwai, “Characterization of
La2O3 and Yb2O3 Thin Films for High-k Gate Insulator Application”, Journal of The
Electrochemical Society, Vol.150, No. 7, F134-F140, July, 2003
[ 78] J. O. Borland, H. Iwai, W. Maszara, H. Wang, “Extending the life of planar CMOS with multigate CMOS devices”, Solid-State Technology, Vol.46, pp.26, March, 2003
[ 79] T.Hattori, T.Yoshida, T.Shiraishi, K.Takahashi, H.Nohira, S.Joumori, K.Nakajima, M.Suzuki,
K.Kimura, I.Kashiwagi, C.Ohshima, S.Ohmi, H.Iwai, “Composition,chemical structure, and electronic band structure of rare earth oxide/Si(100) interfacial transition layer” ,Microelectronic Engineering, Vol.72, pp.283-287, April, 2004
[ 80] S.Ohmi, H.Yamamoto, J.Taguchi, K.Tsutsui, H.Iwai, “Effects of Post Dielectric Deposition and Post Metallization Annealing Processes on Metal/Dy2O3/Si(100) Diode
14
Characteristics”,Japanese Journal of Applied Physics,Vol.43, No.4B, pp.1873-1878, April,
2004
[ 81] S.Ohmi, M.Takeda, H.Ishiwara, H. Iwai, “Electrical Characteristics for Lu2O3 Thin Films
Fabricated by E-Beam Deposition Method”, Journal of The Electrochemical Society, Vol.151,
No.4,pp.G279-283, 2004
[ 82] H. Iwai, “The Future of CMOS Downscaling”, Future Trends in Microelectronics The Nano, the Giga, and Ultra, pp.23-33, The Institute of Electrical and Electronics Engineers, Inc., New
York, 2004
[ 83] H. Nohira, T. Shiraishi, K. Takahashi, T. Hattori, I. Kashiwagi, C. Ohshima, S. Ohmi, H. Iwai,
S. Joumori, K. Nakajima, M. Suzuki, K. Kimura, “Atomic-scale depth profiling of composition, chemical structure and electronic band structure of La
2
O
3
/Si(100) interfacial transition layer”,
Applied Surface Science, Vol.234, pp.493-496, July, 2004
[ 84] K. Oshima, S. Cristoloveanu, B. Guillaumot, S. Deleonibus, H. Iwai, “SOI MOSFETs with
Buried Alumina : Thermal and Electrical Aspects”, Journal of The Electrochemical Society,
Vol.151, No.4, pp.G257-G261, 2004
[ 85] K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, S. Deleonibus, “Advanced SOI
MOSFETs with buried alumina and ground plane : self-heating and short-channel effects”,
Solid-State Electronics, Vol.48, pp.907-917, June, 2004
[ 86] Y. Kim, K. Miyauchi, S. Ohmi, K. Tsutsui, H. Iwai, “Electrical properties of vacuum annealed
La
2
O
3
thin films grown by e-beam evaporation”, Microelectronics Journal, Vol.36, No.1, pp.41-49 January, 2005
[ 87] Y. Kim, S. Ohmi, K. Tsutsui, H. Iwai, “Analysis of variation in leakage currents of Lanthana thin films”, Solid-State Electronics, Vol.49, pp. 825-833, May, 2005
[ 88] J.A.Ng, Y. Kuroki, N. Sugii, K. Kakushima, S.-I. Ohmi, K. Tsutsui, T. Hattori, H. Iwai, H.
Wong, “Effects of low temperature annealing on the ultrathin La
2
O
3 gate dielectric; comparison of post deposition annealing and post metallization annealing”, Microelectronic
Engineering, Vol.80, pp. 206-209, June, 2005
[ 89] Y. Sasaki, C.G.Jin, K. Okashita, H. Tamura, H. Ito, B. Mizuno, H. Sauddin, R. Higaki, T.
Satoh, K. Majima, Y. Fukagawa, K. Takagi, I. Aiba, K. Tsutsui, H. Iwai, “New method of
Plasma doping with in-situ Helium pre-amorphization”, Nuclear Instruments and Methods in
Physics Reseach B237, pp.41-45, August, 2005
[ 90] A. Kuriyama, S. Ohmi, K. Tsutsui, H. Iwai, “Effect of Post-Metallization Annealing on
Electrical Characteristics of La
2
O
3
Gate Thin Films”, Japanese Journal of Applied Physics, Vol.
44, No.2, pp.1045-1051, February, 2005
[ 91] Y. Kim, S. Ohmi, K. Tsutsui, H. Iwai, “Space-Charge-Limited Currents in La203Thin Films
Deposited by E-Beam Evaporation after Low Temperature Dry-Nitrogen Annealing”, Japanese
Journal of Applied Physics, Vol. 44, No.6A, pp.4032-4042, June, 2005
[ 92] H. Wong, H. Iwai, “The Road to Miniaturization”, Physics World, Vol. 18, No.9, pp.40-44,
September, 2005
[ 93] D. Misra, H. Iwai, H. Wong, High-k Gate Dielectrics”, Interface, Vol.14, No.2, Summer, 2005
[ 94] H. Nohira, T. Yoshida, H .Okamoto, W. Sakai, K. Nakajima, M. Suzuki, K. Kimura, Ng Jin
Aun, Y. Kobayashi, S. Ohmi, H. Iwai, E. Ikenaga, K. Kobayashi, Y. Takata, T. Hattori,
“ Thermal Stability of Lanthanum Oxide / Si (100) Interfacial Transitionlayer”, Physics and
Chemistry of SiO
2
and the SiO
2
Interface-5, Vol. 1, No. 1, pp.87-95, 2005
[ 95] E.Miranda J.Molina, Y.Kim, H. Iwai,
“
Effects of high-field electrical strees on the conduction properties of ultra-thin La
2
O
3
Films
”,
APPLIED PHYSICS LETTERS, Vol.86, 232104, June,
2005
[ 96] E.Miranda J.Molina, Y.Kim, H. Iwai,
“
Degradation of High-K La
2
O
3
Gate Dielectrics Using
Progressive Electrical Stress
”,
Microelectronics Reliability, Vol.45, pp.1365-1369,
September-November, 2005
[ 97] N. Bresson, S. Cristoloveanu, C. Mazure, F. Letertre, H. Iwai, “Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects”, Solid-State Electronics, Vol.49, pp.1522-1528, September, 2005
[ 98] C. G. Jin, Y. Sasaki, K. Okashita, H. Tamura, H. Ito, B. Mizuno, K. Tsutsui, S. Ohmi, H. Iwai,
“Ultra shallow p + /n junction formation by plasma doping (PD) and long pulse all solid-state laser annealing (ASLA) with selective absorption modulation”, Nuclear Instruments and
Methods in Physics Research B237, pp.58-61, August, 2005
[ 99] K. Tsutsui, R. Higaki, Y. Sasaki, T. Sato, H. Tamura, K. Okashita, B. Mizuno, H. Iwai,
“Doping effects from neutral B2H6 gas phase on plasma pretreated Si substrates as a possible
15
process in plasma doping”, Japanese Journal of Applied Physics Part 1-Regular Papers Short
Notes & Review Papers, Vol.44, 6A, pp.3903-3907, June, 2005
[ 100] J. Tonotani, S. Ohmi, H. Iwai, “Dry etching of Cr2O3/Cr stacked film during resist ashing by oxygen plasma”, Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes &
Review Papers, Vol.44, 1A, pp.114-117, January, 2005
[ 101] E.Miranda, J.Molina, Y.Kim, H. Iwai, “Tunneling in sub-5nm La
2
O
3
Deposited by
E-beam Evaporation ”, Journal of Non-Crystalline Solids, Vol. 352, pp.92-97, January, 2006
[ 102] J.A.Ng, N. Sugii, K. Kakushima, P. Ahmet, K. Tsutsui, T. Hattori, H. Iwai “Effective
Mobility and Interface-state Density of La
2
O
3
nMisFETs after post deposition annealing”,
IEICE 2006 Electronics Express, Vol.3, No.13, pp. 316-321, July, 2006
[ 103] H. Nohira, T. Yoshida, H. Okamoto, S. Shinagawa, W. Sakai, K. Nakajima, M. Suzuki, K
Kimura, NJ. Aun, Y. Kobayashi, S. Ohmi, H. Iwai, E. Ikenaga, Y. Tanaka, K. Kobayashi, T.
Hattori, “Thermal stability of Gd2O3/Si(100) interfacial transition layer”, JOURNAL DE
PHYSIQUE IV, Vol.132, pp.273-277, March, 2006
[ 104] H. Wong, H. Iwai, “On the scaling issues and high -k replacement of ultrathin gate dielectrics for nanoscale MOS transistors ”, Microelectronic Engineering, Vol.83, pp.1867-1904, October, 2006
[ 105] K. Kakushima, H. Wong, H. Iwai, “Challenges for Future Semiconductor Manufacturing”,
International Journal of High Speed Electronics and Systems, Vol.16, No.1, pp.43-81, 2006
[ 106] Y. Kuroki, J.A.Ng, K. Kakushima, N.Sugii, K.Tsutsui, H. Iwai, “Al/La
2
O
3
Analysis of Post
Metallization Annealed MISFETs by XPS”, ECS Transactions,Vol.1, No.5, pp.239-247, 2006
[ 107] J. Molina, K. Kakushima, P.Ahmet, N. Sugii, K. Tsutsui, H. Iwai, “Breakdown and
Reliability of Metal Gate- La
2
O
3
Thin Films After Post-Deposition Annealing In N
2
”, ECS
Transactions, Vol.1, No.5, pp.757-765, 2006
[ 108] H. Wong, H. Iwai, “Modeling and characterization of direct-tunneling current in dual-layer ultrathin-gate dielectric films”, Journal of Vacuum Science and Technology B,
Vol.24, No.4, July-August, 2006
[ 109] K. Kakushima, K. Tsutsui, S. Ohmi, P. Ahmet, H. Iwai, “Rare Earth Oxides in
Microelectronics”, Rare Earth Oxide Thin Films, Topics in Applied Physics, Vol.106, pp.345-365, 2007
[ 110] B. Sen, H. Wong, J.Molina, H. Iwai, J.A.Ng, K.Kakushima, C.K.Sarkar, “Trapping
Characteristics of lanthanum oxide gate dielectric film explored from temperature dependent current-voltage and capacitance-voltage measurements”, Solid-State Electronics, Vol.51, pp.475-480, March, 2007
[ 111] J.Song, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai
,
“CHARACTERISTICS of Ultrathin Lanthanum Oxide Films on Germanium Substrate:
Comparison with Those on Silicon Substrate” , Japanese Journal of Applied Physics, Vol.46,
No.16, pp.L376-L378, April, 2007
[ 112] N.Umezawa, K.Shiraishi, S.Sugino,A.Tachibana, K.Ohmori, K.Kakushima, H.Iwai,
T.Chikyow, T.Ohno, Y.Nara, K.yamada
, “Suppression of Oxygen Vacancy Formation in
Hf-based High-k Dielectrics by Lanthanum Incorporation” , APPLIED PHYSICS LETTERS,
Vol.91, No.132904, September, 2007
[ 113] E.Miranda, H.Iwai, “ Postbreakdown Conduction in Ultrathin La
2
O
3
Gate Dieclectrics ” , IEEE
Transactions on Device and Materials Reliability, Vol.7, No.2, pp.333-339, June, 2007
[ 114] Y. Kobayashi, C. Raghunathan Manoj, K. Tsutsui,Venkanarayan Hariharan, K. Kakushima, V.
Ramgopal Rao, P. Ahmet , H. Iwai, “Parasitic Effects in Multi-Gate MOSFETs”, IEICE
TRANSACTIONS on Electronics, Vol.E90-C, No.10, pp.2051-2056, October, 2007
[ 115] A. Kuriyama, J. Mitard, O. Faynot, L. Brevard, L. Lclerc, A. Tozzo, V. Vidal, S. Deleonibus,
H. Iwai, S.Cristoloveanu, “A systematic investigation of work function in advanced metal gate-HfO2-SiO2 structures with bevel oxide” , Solid-State Electronics, Vol.51, pp.1515-1522,
November-December, 2007
[ 116] B. Sen, B. L. Yang, H. Wong, P. K. Chu, A. Huang, K. Kakushima, H. Iwai, “Aluminium incorporation in lanthanum oxide films by using plasma immersion ion implantation”,
Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits 2007, Taiwan,
Vol. 1, pp. 173.
[ 117] B. Sen, B. L. Yang, H.Wong, C. W. Kok, M. K. Bera, P. K. Chu, A. Huang, K. Kakushima,
H. Iwai, “Electrical stability improvement for lanthanum oxide films by nitrogen incorporation using plasma immersion ion implantation”, Proceedings of IEEE Conference on Electron
Devices and Solid-State Circuits 2007, Taiwan, Vol. 2, pp. 6
16
[ 118] S. Sato, K. Tachi, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai,
“Thermal-stability improvement of LaON thin film formed using nitrogen radicals” ,
Microelectronic Engineering, Vol.84, pp.1894-1897, September-October, 2007
[ 119] J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Improvement of interfacial properties with interfacial layer in La
2
O
3
/ Ge structure”, Microelectronic
Engineering, Vol.84, pp.2336-2339, September-October, 2007
[ 120] T. Kawanago, K.Tachi, J.Song, K. Kakushima, P. Ahmet, K.Tsutsui, N. Sugii, T. Hattori,
H.Iwai, “Electrical characterization of directly deposited La-Sc oxides complex for gate insulator application”, Microelectronic Engineering, Vol.84, pp.2335-2338,
September-October, 2007
[ 121] Y.C.Ong, D.S.Ang, K.L.Pey, S.J.O’Shea, K.E.J.Goh, C.Troadec, C.H.Thung, T. Kawanago,
K. Kakushima, H. Iwai, “Bilayer gate dielectric study by scanning tunneling microscopy”,
APPLIED PHYSICS LETTERS, Vol.91, 102905, September, 2007
[ 122] J. Molina, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Carrier separation and Vth measurements of W-La
2
O
3 gated MOSFET structures after electrical stress”, IEICE Electronics Express, Vol.4, No.6, pp.185-191, March, 2007
[ 123] J. Molina, K. Tachi, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai,
“Effects of N
2
-Based Annealing on the Reliability Characteristics of Tungsten/ La
2
O
3
/Silicon
Capacitors”, Journal of The Electrochemical Society, Vol.154, No.5, pp.G110-G116, March,
2007
[ 124] K. Doi, Y. Mikazuki, S. Shinya, T. Doi, P. Szarek, M. Senami, K. Shiraishi, H. Iwai, N.
Umezawa, T. Chikyo, K. Yamada, A. Tachibana, “Electronic structure study of local dielectric properties of lanthanoid oxide, clusters”, Japanese Journal of APPlied Physics, Vol. 47, pp.205-211, January, 2008
[ 125] K. Kakushima, K. Okamoto, K. Tachi, J. Song, S. Sato, T. Kawanago, K. Tsutsui, N. Sugii, P.
Ahmet, T. Hattori, H. Iwai, “Observation of band bending of metal/high-k Si capacitor with high energy x-ray photoemission spectroscopy and its application to interface dipole measurement”, JOURNAL OF APPLIED PHYSICS, Vol.104, No.10, Article Number:
104908, November, 2008
[ 126] P. Ahmet, T. Shiozawa, K. Nagahiro, T. Nagata, K. Kakushima, K. Tsutsui, T. Chikyow, H.
Iwai, “Thermal stability of Ni silicide films on heavily doped n + and p + Si substrates”
Microelectronic Engineering, Vol. 85, pp 1642-1646, July, 2008
[ 127] K. Kakushima, K. Okamoto, M. Adachi, K. Tachi, J. Song, S. Sato, T. Kawanago, P. Ahmet,
K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Band bending measurement of HfO
2
/SiO
2
/Si capacitor with ultra-thin La
2
O
3
insertion by XPS”, Applied Surface Science, Vol.254, pp.
6106-6108, July, 2008
[ 128] D. S. Ang, Y. C. Ong, S. J. O'Shea, K. L. Pey, C. H. Tung, T. Kawanago, K. Kakushima, H.
Iwai, “Polarity dependent breakdown of the high-kappa/SiOx gate stack: A phenomenological explanation by scanning tunneling microscopy”, APPLIED PHYSICS LETTERS, Vol.92,
Article Number 192904, May, 2008
[ 129] Y. C. Ong, D. S. Ang, K. L. Pey, Z. R. Wang, S. J. O'Shea, C. H. Tung, T. Kawanago, K.
Kakushima, H. Iwai, “Electronic trap characterization of the Sc
2
O
3
/La
2
O
3
high-kappa gate stack by scanning tunneling microscopy”, APPLIED PHYSICS LETTERS, Vol. 92, Article
Number 022904, January, 2008
[ 130] K. Kakushima, K. Okamoto, M. Adachi, K. Tachi, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori,
H. Iwai, “Origin of flat band voltage shift in HfO
2
gate dielectric with La
2
O
3
insertion”,
Solid-State Electronics, Vol. 52, pp. 1280-1284, September, 2008
[ 131] N. Urushihara, S. Iida, N. Sanada, M. Suzuki, D. F. Paul, S. Bryan, Y. Nakajima, T. Hanajiri,
K. Kakushima, P. Ahmet, K. Tsutsui, H. Iwai, “Three dimensional image construction and spectrum extraction from two dimensional elemental mapping in Auger electron spectroscopy”,
Journal of Vacuum Science and Technology A, Vol.26, pp. 668-672, July-August, 2008
[ 132] J. Molina, A. Torres, W. Calleja, K. Kakushima, P. Ahmet, K. Tsutsui, N.Sugii, T. Hattori, H.
Iwai, “Degradation and breakdown of W-La
2
O
3
stack after annealing in N-2”, Japanese Journal of Applied Physics, Vol.47, No.9, pp. 7076-7080, September, 2008
[ 133] K. Tsutsui, Ruifei Xiang, K. Nagahiro, T. Shiozawa, P. Ahmet, Y. Okuno, M. Matsumoto, M.
Kubota, K. Kakushima, H. Iwai, “Analysis of irregular increase in sheet resistance of Ni silicides on transition from NiSi to NiSi2”, Microelectronic Engineering, Vol.85, pp.315-319,
February, 2008
[ 134] K. Tsutsui, T. Shiozawa, K. Nagahiro, Y. Ohishi, K. Kakushima, P. Ahmet, N. Urushihara, M.
Suzuki, H. Iwai, “Improvement of Thermal Stability of Ni Silicide on N+-Si by Direct
17
Deposition of Group III Element (Al, B) Thin Film at Ni/Si Interface”, Microelectronic
Engineering, Vol.85, pp.2000-2004, October, 2008
[ 135] K. Tsutsui, T. Matsuda, M. Watanabe, Cheng-Guo Jin, Y. Sasaki, B. Mizuno, E. Ikenaga, K.
Kakushima, P. Ahmet, T. Maruizumi, H. Nohira, T. Hattori, H. Iwai, “Activated Boron and its
Concentration Profiles in Heavily Doped Si Studied by Soft X-ray Photoelectron Spectroscopy and Hall Measurements”, Journal of Applied Physics, Vol.104, 093709, November, 2008
[ 136] P. Ahmet, K. Nakagawa, K. Kakushima, H. Nohira, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai,
“Electrical characteristics of MOSFETs with La2O3/Y2O3 gate stack”, Microelectronics
Reliability, Vol.48, pp.1769-1771, November-December, 2008
[ 137] D.S.Ang, Y.C.Ong, S.J. O’Shea, K.L.Pey, K.Kakushima, H.Iwai, “Study of trap generation in the Sc
2
O
3
/La
2
O
3
/SiO x gate dielectric stack by scanning tunneling microscopy”, APPLIED
PHYSICS LETTERS, Vol. 93, Article Number 242904, December, 2008
[ 138] H.Iwai, “Roadmap for 22nm and beyond”, Microelectronic Engineering, Vol.86, pp.1520-1528, July-September, 2009
[ 139] J. Song, K. Kakushima, P.Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Post metallization annealing study in La
2
O
3
/Ge MOS structure”, Microelectronic Engineering, Vol.86, pp.1638-1641, July-September, 2009
[ 140] T. Kawanago, J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai,
“Experimental Study for High Efffective Mobility with directly deposited HfO
2
/La
2
O
3
MOSFET”, Microelectronic Engineering, Vol. 86, pp.1629-1631, July-September, 2009
[ 141] B. Sen, H.Wong, B. L. Yang, P. K. Chu, K. Kakushima, H. Iwai, “Effects of nitrogen incorporation into lanthana film by plasma immersion ion implantation”, Solid-State
Electronics, Vol.53, pp.355-358, March, 2009
[ 142] S.-L. Siu, H. Wong, W.-S. Tam, K. Kakusima, H. Iwai, “Subthreshold parameters of radio-frequency multi-finger nanometer MOS transistors”, Microelectronics Reliability, Vol.49, pp.387391, April, 2009
[ 143] T. Koyanagi, K. Tachi, K. Okamoto, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T.
Hattori, H. Iwai, “Electrical Characterization of La
2
O
3
-Gated Metal Oxide Semiconductor
Field Effect Transistor with Mg Incorporation”, Japanese Journal of Applied Physics, Vol.48,
May, 2009
[ 144] K.Kakushima, K. Tachi, J. Song, S. Sato, H. Nohira, E. Ikenaga, P. Ahmet, K. Tsutsui, N.
Sugii, T. Hattori, H. Iwai, “Comprehensive x-ray photoelectron spectroscopy study on compositional gradient lanthanum silicate film”, Journal of Applied Physics, Vol.106,
December, 2009
[ 145] K. Kakushima, K. Okamoto, T. Koyanagi, M. Kouda, K. Tachi, T. Kawanago, J. Song, P.
Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Selection of rare earth silicates for highly scaled gate dielectrics”, Microelectronic Engineering, doi:10.1016/j.mee.2009.11.001, ,2009
[ 146] H. Wong, H. Iwai, K. Kakushima, B.L. Yang and P. K. Chu, “XPS Study of the Bonding
Properties of Lanthanum Oxide/Silicon Interface with a Trace Amount of Nitrogen
Incorporation”, Journal of Electrochemical Society,2010
[ 147] Y.Kobayashi, K. Kakushima, P. Ahmet, V. Rampogal Rao, K. Tsutsui, H. Iwai, “Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness”,
Microelectronics Reliability, Vol.50, pp.332-337, March, 2010
[ 148] K. Kakushima, K. Okamoto, T. Koyanagi, M. Kouda, K. Tachi, T. Kawanago, J. Somg, P.
Ahmet, H. Nohira, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “SrO capping effect for La
2
O
3
/
Ce-Silicate gate dielectrics”, Microelectronics Reliability,Vol.50, pp.356-359,March, 2010
[ 149] Y. Kobayashi, K. Tsutsui, K. Kakushima, P. Ahmet, V. Ramgopal Rao, H. Iwai, “Analysis of
Threshold Voltage Variation in Fin Field Effect Transistors (FinFETs) Separating Role of
Short Channel Effects”, Japanese Journal of Applied Physics, Vol.49, pp.044201-1-044201-6,
April, 2010
[ 150] H. Shimomura, K. Kakushima, H. Iwai, “Effect of High Frequency Noise Current Sources on
Noise Figure for Sub-50 nm Node MOSFETs”, IEICE TRANSACTIONS on Electronics, Vol.
E93-C No.5, pp.678-684, May, 2010
[ 151] K. Kakushima, M. Nakagawa, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H Iwai,
“Radio-frequency performance of a sub-100 nm metal-oxide field-effect transistor with high-k gate dielectric”, Semiconductor Science and Technology, Vol. 25, No. 4, 045029, 2010
[ 152] A. Uedono, K. Tsutsui, S. Ishibashi, H. Watanabe, S. Kubota, Y. Nakagawa, B. Mizuno, T.
Hattori, H. Iwai, “Vacancy-Boron Complexes in Plasama Immersion lon-lmplanted Si Probed by a Monoenergetic Positron Beam”, Japanese Journal of Applied Physics, Vol.49, 051301,
18
May, 2010
[ 153] M. K. Bera, J. Song, P. Ahmet, K. Kakushima, N. Sugii, T. Hattori, H. Iwai,
“Yttrium-scandium oxide as highk gate dielectric for germanium metal-oxide-semiconductor devices”, Semiconductor Science and Technology , Vol.25, No. 6, 065008 ,May, 2010
[ 154] Y. Lee, K. Natori, H. Iwai, K. Kakushima, K. Shiraishi, “Size-Dependent Properties of
Ballistic Silicon Nanowire Field Effect Transistors”, JOURNAL OF APPLIED
PHYSICS,Vol.107, No.11,pp.113705, June, 2010
[ 155] S. Inamoto, J. Yamasaki, E. Okunishi, K. Kakushima, H. Iwai, N. Tanaka, “Annealing effects on a highk lanthanum oxide film on Si(001) analyzed by aberration-corrected transmission electron microscopy/scanning transmission electron microscopy and electron energy loss spectroscopy”, JOURNAL OF APPLIED PHYSICS,Vol.107, 124510, June, 2010
[ 156] K. Kakushima, K. Tachi, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Advantage of further scaling in gate dielectrics below 0.5 nm of equivalent oxide thickness with La2O3 gate dielectrics”, Microelectronics Reliability, Vol.50(6), pp.790-793, June, 2010
[ 157] Y. Lee, K. Kakushima, K. Shiraishi, K. Natori, H. Iwai, “Trade-off between density of states and gate capacitance in size-dependent injection velocity of ballistic n-channel silicon nanowire transistors”, APPLIED PHYSICS LETTERS, Vol.97(3), Art. No. 032101, July 19,
2010
[ 158] K. Kakushima, T. Koyanagi, K. Tachi, J. Song, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H.
Iwai, “Characterization of flatband voltage roll-off and roll-up behavior in La
2
O
3
/silicate gate dielectric”, Solid-State Electronics, Vol. 54, No.7, pp. 720-723, July, 2010
[ 159] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, J. Song, T. Kawanago, P. Ahmet,
K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Interface and electrical properties of La-silicate for direct contact of high-k with silicon”, Solid-State Electronics, Vol. 54, pp. 715-719, July, 2010
[ 160] S. Sato, H. Kamimura, H. Arai, K. Kakushima, P. Ahmet, K. Ohmori, K. Yamada, H. Iwai,
“Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration”, Solid-State Electronics, Vol. 54, No.9, pp. 925-928,
September, 2010
[ 161] H. Shimomura, K. Kakushima, H. Iwai, “Equivalent Noise Temperature Representation for
Scaled MOSFETs”, IEICE TRANSACTIONS on Electronics, Vol. E93-C, No.10, pp.1550-1552, October, 2010
[ 162] K. Kakushima, K. Okamoto, T. Koyanagi, M. Kouda, K. Tachi, T. Kawanago, J. Song, P.
Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Selection of rare earth silicates for highly scaled gate dielectrics”, Microelectronic Engineering, Vol.87, No.10, pp.1868-1871, October,
2010
[ 163] H. Wong, CK Wong, J. Liu, H. Iwai, “Growth of Dielectric-Embedded Silicon
Nanocrystallites for Light-Emitting Device Application”, JOURNAL of NANOSCIENCE and
NANOTECHNOLOGY, Vol.10, No.11, pp.7244-7249, November, 2010
[ 164]
K. Shubhakar, K.L. Pey, S.S. Kushvaha, S.J. O’Shea, N. Raghavan, M. Bosman, M. Kouda, K.
Kakushima, H. Iwai, “Grain boundary assisted degradation and breakdown study in cerium oxide gate dielectric using scanning tunneling microscopy”, APPLIED PHYSICS LETTERS,
Vol.98, Art.No. 072902, February, 2011
[ 165] S. Sato, K. Ohmori, K. Kakushima, P. Ahmet, K. Natori, K. Yamada, H. Iwai, “Experimental
Characterization of Quasi-Fermi Pontential Profile in the Channel of a Silicon Nanowire
Field-Effect Transistor with Four-Terminal Geometry”, Applied Physics Express, Vol.4, Art.
No. 044201, April, 2011
[ 166] D. Zade, S. Sato, K. Kakushima, A. Srivastava, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
K. Natori, T. Hattori, C.K. Sarkar, H. Iwai, “Effects of La
2
O
3 incorporation in HfO2 gated nMOSFETs on low-frequency noise”, Microelectronics Reliability, Vol. 51, pp. 746-750, April,
2011
[ 167] H.Iwai, K. Natori, K. Shiraishi, J. Iwata, A. Oshiyama, K. Yamada, K. Ohmori, K. Kakushima,
P. Ahmet, “Si nanowire FET and its modeling”, Science China, Vol.54, No.5, pp. 1004-1011,
May, 2011
[ 168] S. Sato, K. Kakushima, P. Ahmet, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Structural advantages of rectangular-like channel cross-section on electrical characteristics of silicon nanowire field-effect transistors”, Microelectronics Reliability, Vol. 51, pp.879-884, May 2011
[ 169] K. Tachi, S. Barraud, K. Kakushima, H. Iwai, S. Cristoloveanu, T. Ernst, “Comparison of low-temperature electrical characteristics of gate-all-around nanowire FETs, Fin FETs and fully-depleted SOI FETs”, Microelectronics Reliability, Vol. 51, pp.885-888, May, 2011
[ 170] Y. Lee, K. Kakushima, K. Natori, H. Iwai, “Corner effects on phonon-limited mobility in
19
rectangular silicon nanowire metal-oxide-semiconductor field-effect transistors based on spatially resolved mobility analysis”, JOURNAL OF APPLIED PHYSICS,Vol.109, 113712,
June, 2011
[ 171] H.D.Trinh, G. Brammertz, E. Y. Chang, Senior Member, IEEE, C. I. Kuo, C. Y. Lu, Y. C. Lin,
H. Q. Nguyen, Y. Y. Wong, B.T. Tran, K. Kakushima, H. Iwai, “Electrical Characterization of
Al
2
O
3
/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments”,
IEEE ELECTRON DEVICE LETTERS, Vol.32, No.6, June 2011
[ 172] S. Sato, W. Li, K. Kakushima, K. Ohmori, K. Natori, K.Yamada, H. Iwai, “Eatraction of additional interfacial states of silicon nanowire field-effect transistors”, APPLIED PHYSICS
LETTERS 98, 233506, June, 2011
[ 173] D. Zade, K. Kakushima, T. Kanda, Y.C.Lin, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
E.Y. Chang, K. Natori, T. Hattori, H. Iwai, “Improving electrical characteristics of
W/HfO
2
/In o.53
Ga o.47
As gate stacks by altering deposition techniques”, Microelectronic
Engineering, Vol.88, No.7, pp.1109-1112, July, 2011
[ 174] D. Kitayama, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Effect of thin Si insertion at metal gate/highk interface on electrical characteristics of MOS device with La
2
O
3
”, Microelectronic Engineering, Vol.88,
No.7, pp.1330-1333, July 2011
[ 175] K. Tachi, N. Vulliet, S. Barraud, K. Kakushima, H. Iwai, S. Cristoloveanu, T. Ernst,
“Influence of source/drain formation process on resistance and effective mobility for scaled multi-channel MOSFET”, Solid-State Electronics, Vol.65-66, pp.16-21, November-December,
2011
[ 176] H. Wong, Y. B.L, K. Kakushima,H. Iwai, “Subthreshold Characteristics of MOS Transistors
With CeO(2)/La(2)O(3) Stacked Gate Dielectric”, IEEE ELECTRON DEVICE LETTERS,
Vol.32, No.8, pp.1002-1004, August, 2011
[ 177] H. L. Qin, C.Troadec, K.E.J. Goh, K. Kakushima, H. Iwai, M. Bosman, K.L.Pey, “Electronic properties of ultrathin highk dielectrics studied by ballistic electron emission microscopy”,
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2
Films for Gate Dielectrics Application: Comparative
Study of Chemical Vapor Deposition and Atomic Layer Deposition Processes”, Japanese
Journal of Applied Physics,Vol.50, No.10, pp.10PA06-1-4, October, 2011
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H. Iwai, “Rare Earth Oxide Capping Effect on La
2
O
3
Gate Dielectrics for Equivalent Oxide
Thickness Scaling toward 0.5nm”, Japanese Journal of Applied Physics, Vol.50, No.10, pp.10PA04-1-4, October, 2011
[ 180] A. Abudukelimu, W. Yasenjiang, K. Kakushima, P. Ahmet, M. Geni, K. Natori, H. Iwai,
“Effects of Scattering Direction of Hot Electrons in the Drain of Ballistic n + –i–n + Diode”,
Japanese Journal of Applied Physics,Vol.50, No.10, pp.104301-1-3, October, 2011
[ 181] D. Zade, T. Kanda, K. Yamashita, K. Kakushima, H. Nohira, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Capacitance-Voltage Characterization of
La
2
O
3
Metal-Oxide-Semiconductor Structures on In o.53
Ga
.0.47
As Substrate with Different
Surface Treatment Methods”, Japanese Journal of Applied Physics, Vol.50, No.10, pp.10PD03-1-4, October, 2011
[ 182] D. Kitayama, T. Kubota, T. Koyonagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Silicate Reaction Control at Lanthanum Oxide and
Silicon Interface for Equivalent Oxide Thickness of 0.5nm* Adjustment of Amount of
Residual Oxygen Atoms in Metal Layer”, Japanese Journal of Applied Physics, Vol.50, No.10, pp.10PA05-1-5, October, 2011
[ 183] K. Yamashita, Y. Numajiri, M. Watanabe, K. Kakushima, H. Iwai, H. Nohira, “Study of
Highk /In o.53
Ga
.0.47
As interface by Hard X-ray Photoemission Spectroscopy”, Japanese Journal of Applied Physics, Vol.50, No.10, pp.10PD02-1-5, October, 2011
[ 184] M. Kouda, T. Kawanago, P. Ahmet, K. Natori, T. hattori, H. Iwai, “Interface and electrical properties of Tm
2
O
3
gate dielectrics for gate oxide scaling in MOS devices”, Journal of
Vacuum Science and Technology B, Vol.29, No.6, pp.062202-1-4, November, 2011
[ 185] S. Sato, K. Kakushima, P. Ahmet, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure”, Solid-State
Electronics, Vol.65-66, pp.2-8, November-December, 2011
20
[ 186] S. Sato, K. Kakushima, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Electrical characteristics of asymmetrical silicon nanowire field-effect transistors”, APPLIED PHYSICS LETTERS,
Vol.99, No.22, pp.223518-1-3, November, 2011
[ 187] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “EOT of 0.62 nm and High Electron Mobility in La-silicate/Si
Structure Based nMOSFETs Achieved by Utilizing Metal-Inserted Poly-Si Stacks and
Annealing at High Temperature”, IEEE Transactions on Electron Devices, Vol. 59, No.2, pp.269-276, February, 2012
[ 188] T. Kawanago, T. Suzuki, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Compensation of oxygen defects in La-silicate gate dielectrics for improving effective mobility in high-k/metal gate MOSFET using oxygen annealing process”, Solid-State Electronics, Vol.68, pp.68-72, February, 2012
[ 189] H. Wong, B. L. Yang, K. Kakushima, P. Ahmet, H. Iwai, “Properties of CeOx/La2O3 gate dielectric and its effects on the MOS transistor characteristics”, Vacuum, vol.86, No.7, pp.990-993, February, 2012
[ 190] H. Wong, B. L. Yang, K. Kakushima, P. Ahmet, H. Iwai, “Effects of aluminum doping on lanthanum oxide gate dielectric films,” Vacuum, vol.86, No.7, pp.929-932, February, 2012
[ 191] H.D. Trinh, Y. C. Lin, H.C. Wang, C.H. Chang, K. Kakushima, H. Iwai, T. Kawanago, Y. G.
Lin, C.M. Chen, Y. Y. Wong, G. N. Huang, M. Hudait, E. Y. Chang, “Effect of Postdeposition,
Annealing Temperatures on Electrical Characteristics of Molecular-Beam-Deposited HfO
2 on n-InAs/InGaAs Metal-Oxide-Semiconductor Capacitors”, Applied Physics Express Vol.5,
No.2, pp.021104-1-3, February, 2012
[ 192] T. Kawanago, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Covalent Nature in La-Silicate Gate Dielectrics for Oxygen Vacancy
Removal”, IEEE ELECTRON DEVICE LETTERS, Vol.33, No.3, pp.423-425, March, 2012
[ 193] M. Mamatrishat, M. Kouda, T. Kawanago, K. Kakushima, P. Ahmet, K. Tsutsui, Y. Kataoka,
A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “The effect of remote Coulomb scattering on electron mobility in La
2
O
3
gate stacked MOSFETs”, Semiconductor Science and
Technology, Vol.27, No.4, 045014, March, 2012
[ 194] M. Mamatrishat, M. Kouda, K. Kakushima, H. Nohira, P. Ahmet, Y. Kataoka, A. Nishiyama,
K. Tsutsui, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Valance number transition and silicate formation of cerrium oxide on Si(100)”, Vacuum, Vol.86, No.10, pp.1513-1516, April, 2012
[ 195] Y. Lee, K. Kakushima, K. Natori, H. Iwai, “Gate Capacitance Modeling and
Diamater-Drpendent Performance of Nanowire MOSFETs”, IEEE Transactions on Electron
Deviices, Vol.59, No.4, pp.1037-1045, April, 2012
[ 196] C. Dou, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori,
H. Iwai, “Resistive switching behavior of a CeO
2
based ReRAM cell incorporated with Si buffer layer”, Microelectronics Reliability Vol.32, No.4, pp.688-691, April, 2012
[ 197] W. Feng, R. Hettiarachchi, S. Sato, K. Kakushima, M. Niwa, H. Iwai, K. Yamada, K. Ohmori,
“Advantages of Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors over
Planar Ones in Noise Properties”, Japanese Journal of Applied Physics, Vol.51, pp.04DC06-1-04DC06-5, April, 2012
[ 198] A. Abudukelimu, W. Yasenjiang, K. Kakushima, P. Ahmet, M. Geni, K. Natori, H. Iwai,
“Influence of strained drain on performance of ballistic channel devices”, Semiconductor
Science and Technology, Vol.27, No.5, 055001-1-5, May, 2012
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Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Oxide and interface trap densities estimation in ultrathin W/ La
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O
3
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2
O
3
gate insulators prepared by atomic layer deposition: Optimal growth conditions and MgO/La
2
O
3 stacks for improved metal-oxide-semiconductor characteristics”, Journal of Vacuum Science & Technology A,
Vol.30, No.5, pp.051507-1-8, July, 2012
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Natori, T. Hattori, H. Iwai, “Experimental study of electron mobility characterization in direct contact La-silicate/Si structure based nMOSFETs”, Solid-State Electronics, Vol.74, pp.2-6,
August, 2012
[ 202] B.L. Yang, H. Wong, K. Kakushima, H. Iwai, “Improving the electrical characteristics of
MOS transistors with CeO
2
/ La
2
O
3
stacked gate dielectric”, Microelectronics Realiability,
Vol.52, pp.1613-1616, August, 2012
21
[ 203] S.-L. Siu, W.-S. Tam, H. Wong, C.-W. Kok, K. Kakushima, H. Iwai, “Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors”,
Microelectronics Realiability, Vol.52, pp.1606-1609, August, 2012
[ 204] E. Miranda, T. Kawanago, K. Kakushima, J. Sune, H. Iwai, “Analysis and modeling of the gate leakage current in advanced nMOSFET devices with severe gate–to-drain dielectric breakdown”, Microelectronics Reliability, Vol.52, pp.1909-1912, September-October, 2012
[ 205] E. Miranda, S. Kano, C. Dou, K. Kakushima, J. Sune, H. Iwai, “Nonlinear conductance quantization effects in CeO/SiO-based resistive switching devices”, APPLIED PHYSICS
LETTERS 101, 012910, 2012
[ 206] M. Kouda, T. Suzuki, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Electrical Properties of CeO
2
/La
2
O
3
Stacked Gate Dielectrics Fabricated by Chemical Vapor Deposition and
Atomic Layer Deposition”, Japanese Journal of Applied Physics, Vol.51, pp.121101-1-121101-5, December, 2012
[ 207] H. Wong, B.L. Yang, S. Dong, H. Iwai, K. Kakushima, P. Ahmet, “Current conduction and stability of CeO
2
/La
2
O
3 stacked gate dielectric”, APPLIED PHYSICS LETTERS 101, 233507,
December, 2012
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Nishiyama, N. Sugii, K. Natori, K. Yamada, Y. Kataoka, T. Hattori, H. Iwai, “Influence of
Structural Parameters on Electrical Characteristics of Schottky Tunneling Field-Effect
Transistor and Its Scalability”, Japanese Journal of Applied Physics, Vol.52, pp.04CC28-1-04CC28-5, April, 2013
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Nishiyama, N. Sugii, K. Tsutsui, K. Natori, H. Iwai, “La
2
O
3
/In o.53
Ga
.0.47
As metal-oxide-semiconductor capacitor with low interface state density using TiN/W gate alectrode”, Solid-State Electronics, Vol.82, pp.29-33, April, 2013
[ 210] E. Miranda, S. Kano, C. Dou, J. Sune, K. Kakushima, H. Iwai, “Effect of an ultrathin SiO
2 interfacial layer on the hysteretic current-voltage characteristics of CeO x
-based metal-insulator-metal structures”, Thin Solid Films, Vol.533, pp.38-42, April, 2013
[ 211] R. Tomita, H. Kimura, M. Yasuda, K. Maeda, S. Ueno, T. Tomizawa, Y. Kunimune, H.
Nakamura, M. Moritoki, H. Iwai, “Formation of high resistivity phases of nickel silicide at small area”, Microelectronics Realiability, Vol.53, pp.659-664, April, 2013
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Moritoki, H. Iwai, “Improvement on sheet resistance uniformity of nickel silicide by optimization of silicidation conditions”,Microelectronics Realiability, Vol.53, pp.665-669,
April, 2013
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Iwai, G. Reimbold, “Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs”, Solid-State Electronics, Vol.84, pp.46-52, June,
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[ 214] T. Kawanago, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Comparative study of electrical characteristics in(100) and
(110)surface-oriented nMOSFETs with direct contact La-silicate/Si interface structure”,
Solid-State Electronics, Vol.84, pp.53-57, June, 2013
[ 215] E. Miranda, T. Kawanago, K. Kakushima, J. Sune, H. Iwai, “Analysis and Simulation of the
Postbreakdown I-V Characteristics of n-MOS Transistors in the Linear Response Regime”,
IEEE ELECTRON DEVICE LETTERS, Vol.34, No.6, pp.798-800, June, 2013
[ 216] A. Nakajima, P. Liu, M. Ogura, T. Makino, S. Nishizawa, S. Yamasaki, H. Ohashi, K.
Kakushima, H. Iwai, “Temperature-Independent Two-Dimensional Hole Gas Confined at
GaN/AlGaN Heterointerface”, Applied Physics Express, Vol.6, pp.091002-1-091002-4, 2013
[ 217] C. Dou, T. Shoji,K. Nakajima, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii,
H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Characterization of interface state density of three-dimensional Si nanostructure by charge pumping measurement”, Microelectronics
Realiability, Vol. , pp. , , 2013
[ 218] K. Tuokedaerhan, R. Tan, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Stacked sputtering process for Ti, Ta, and W carbide formation for gate metal application”, APPLIED PHYSICS LETTERS 103,
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Kakushima, H. Iwai, “Temperature-Independent Two-Dimensional Hole Gas Confined at
22
GaN/AlGaN Heterointerface”, Applied Physics Express Vol.6, No.9, pp.091002-1-4,
September, 2013
[ 220] E. Miranda, T. Kawanago, K. Kakushima, J. Sune, H. Iwai, “Modeling of the output characteristics of advanced n-MOSFETs after a severe gate-to-channel dielectric breakdown”,
Microelectronic Engineering, Vol.109, pp.322-325, September, 2013
[ 221] Y. C. Lin, H. D. Trinh, T. W. Chuang, H. Iwai, K. Kakushima, P. Ahmet, C. H. Lin, C. H.
Diaz, H. C. Chang, S. M. Jang, E. Y. Chang, “Electrical Characterization and Materials
Stability Analysis of La
2
O
3
/HfO
2
Composite Oxides on n-In
0.53
Ga
0.47
As MOS Capacitors With
Different Annealing Temperatures”, IEEE ELECTRON DEVICE LETTERS, Vol.34, No.10, pp.1229-1231, October, 2013
[ 222] Y. Sakurai, K. Kakushima, K. Ohmori, K. Yamada, H. Iwai, K. Shiraishi, S. Nomura,
“Photoluminescence characterization in silicon nanowire fabricated by thermal oxidation of nano-scale Si fin structure”, Optics Express, Vol.22, Issue 2, pp.1997-2006, January, 2014
[ 223] K. Tuokedaerhan,K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Atomically flat La-silicate/Si interface using tungsten carbide gate electrode with nano-sized grain”, APPLIED PHYSICS LETTERS 104, 2, January 13, 2014
[ 224] K. Nayak, M. Bajaj, A. Konar, P.J. Oldiges, H. Iwai, K.V.R.M.Murali, V.R. Rao, “Negative differential conductivity and carrier heating in gate-all-around Si nanowire FETs and its impact on CMOS logic circuits”, Japanese Journal of Applied Physics, Vol.53, pp.04EC16-04EC16-7,
February, 2014
[ 225] T. Kawanago, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Gate Technology Contributions to Collapse of Drain Current in
AlGaN/GaN Schottky HEMT”, IEEE Transactions on Electron Deviices, Vol.61, No.3, pp.785-792, March, 2014
[ 226] A. Nakajima, P. Liu, M. Ogura, T. Makino, K. Kakushima, S. Nishizawa, H. Ohashi, S.
Yamasaki, H. Iwai, “Generation and transportation mechanisms for two-dimensional hole gases in GaN/AlGaN/GaN double heterostructures”, JOURNAL OF APPLIED
PHYSICS,Vol.115, 153707, April, 2014
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[34] H. Iwai, F. Matsuoka, H. Oyamatsu, H. S. Momose, K. Hama, Y. Toyoshima, H. Hayashida,
“BT Reliability for thin gate oxide n+ and p+ poly MOSFETs”, 20th IEEE Semiconductor
Interface Specialists Conference, p.II.5, December, 1989, Ft. Lauderdale, Florida, USA
[35] J. Wenstrand, H. Iwai, M. Norishima, H. Tanimoto, T. Wada, R. W. Dutton, “Intelligent simulation for optimization of fabrication process”, Workshop on Numerical Modeling of
Process and Devices for Integrated Circuits: NUPAD III, pp.15-16, June, 1990, Honolulu,
Hawaii, USA.
[36] H. Iwai, H. S. Momose, S. Takagi, T. Morimoto, S. Kitagawa, S. Kambayashi, K. Yamabe, S.
Onga, “Analysis of an ONO gate film effect on n- and p-MOSFET mobilities”, Digest of
Technical Papers, VLSI Symposium on Technology, pp.131-132, June, 1990, Honolulu,
Hawaii, USA
[37] H. S. Momose, T. Morimoto, S. Takagi, K. Yamabe, S. Onga, H. Iwai, “Mechanical sterss induced threshold voltage shifts for nitrided oxide gate n- and p-MOSFETs”, International
Conference on Solid State Device and Materials, pp.279-283, August, 1990, Sendai, Japan
[38] T. Morimoto, H. S. Momose, K. Yamabe, H. Iwai, “Ultra thin nitride gate MISFET operating with tunneling gate current”, International Conference on Solid State Device and Materials, pp.361-364, August, 1990, Sendai, Japan,
[39] H. Iwai, H. S. Momose, T. Morimoto, S. Takagi, K. Yamabe, “Comparison of hot carrier degradations for n- and p-MOSFETs with various nitride-oxide gate films”, ESSDERC 90, pp.287-290, September, 1990, Nottingham, England
[40] H. S. Momose, T. Morimoto, S. Takagi, K. Yamabe, S. Onga, H. Iwai, “New short-channel effects on nitrided oxide gate MOSFETs”, ESSDERC 90, pp.149-152, September, 1990,
Nottingham, England
[41] T. Morimoto, H. S. Momose, K. Yamabe, H. Iwai, “Prevention of boron penetration from pt poly gate by RTP produced thin gate oxide”, ESSDERC 90, pp.73-76, September, 1990,
Nottingham, England
[42] H. S. Momose, T. Morimoto, K. Yamabe, H. Iwai, “Relationship between mobility and residual-mechanical-stress as measuredby Raman spectroscopy for nitrided-oxide-gate
MOSFETs”, IEDM Tech. Dig., pp.65-68, December, 1990
[43] H. Iwai, H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, “Stacked-nitride oxide gate
MISFET with high hot-carrier-immunity”, IEDM Tech. Dig., pp.235-238, December, 1990
[44] T. Morimoto, H. S. Momose, Y. Ozawa, K. Yamabe, H. Iwai, “Effects of boron penetration and resultant limitations in ultra thinpure-oxide and nitrided-oxide gate-films”, IEDM Tech.
Dig., pp.429-432, December, 1990
[45] Invited Talk: H. Iwai, “Hot carreir induced degradation mode in thin gate insulator dual gate
MISFETs”, Workshop on "The Physics of Hot-Carrier Degradation in Silicon MOSFETs" in
1991 INFOS, April, 1991, Liverpool, UK, : also Edited by W. Eccleston and M. Uren,
"Insulating Films on Semiconductors 1991," pp.83-92, 1991, Adam Hilger, Bristol,
Philadelphia and New York
[46] M. Tsuchiaki, H. S. Momose, T. Morimoto, H. Iwai, “New charge pumping method fordirect
25
measurement of spatial distribution of fixed charge”, Digest of Technical Papers, VLSI
Symposium on Technology, pp.19-20, May, 1991, Oiso, Japan
[47] T. Morimoto, H. S. Momose, Y. Ozawa, K. Yamabe, H. Iwai, “Limits on gate insulator thickness for MISFET operation in pure-oxide and nitrided-oxide gate cases”, International
Conference on Solid State Device and Materials, pp.23-25, August, 1991, Yokohama, Japan
[48] Y. Katsumata, I. Katakabe, N. Itoh, E. Tsukioka, Y. Yoshino, H. Iwai, “Stress analysis around trench isolation for bipolar LSIs”, IEEE Bipolar Circuit and Technology Meeting, pp.271-274,
September, 1991, Mineapolis, USA
[49] B. Baccus, T. Wada, N. Shigyo, M. Norishima, H. Iwai, “Impact of ion-implantation damage and transient enhanced diffusion on advanced bipolar technologies - comparisons between experiments and non-equilibrium diffusion modeling”, IEEE Bipolar Circuit and Technology
Meeting, pp.275-278, September, 1991, Mineapolis, USA
[50] H. S. Momose, T. Morimoto, Y. Ozawa, M. Tsuchiaki, M. Ono, K. Yamabe, H. Iwai, “Very lightly nitrided oxide gate MOSFETs for deep-sub-micron CMOS devices”, IEDM Tech. Dig., pp.359-362, December, 1991
[51] T. Morimoto, H. S. Momose, T. Iinuma, I. Kunishima, K. Suguro, H. Okano, I. Katakabe, H.
Nakajima, M. Tsuchiaki, M. Ono, Y. Katsumata, H. Iwai, “A NiSi salicide technology for advanced logic devices”, IEDM Tech. Dig., pp.653-656, December, 1991
[52] T. Iizima, A. Nishiyama, Y. Ushiku, T. Ohguro, I. Kunishima, K. Suguro, H. Iwai, “A novel selective Ni3Si contact plug technique for deep-submicron ULSIs”, VLSI Symposium on
Technology, pp.70-71, June, 1992, Siattle, Washington, USA
[53] T. Iinuma, K. Inou, H. Nakajima, S. Matsuda, I. Kunishima, K. Suguro, Y. Katsumata, H. Iwai,
“A self-aligned emitter base NiSi electrode technology for advanced high speed bipolar LSIs”,
IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.92-95, October, 1992,
Mineapolis, USA
[54] N. Itoh, Yoshino, S. Matsuda, Y. Tsuboi, K. Inou, Y. Katsumata, H. Iwai, “Optimization of shallow and deep trench isolation structureses for ultra-high-speed bipolar LSIs”, IEEE
Bipolar/BiCMOS Circuits and Technology Meeting, pp.104-107, October, 1992, Mineapolis,
USA
[55] K. Inou, M. Kondo, N. Itoh, Y. Tsuboi, Y. Yoshino, H. Nakajima, Y. Katsumata, H. Iwai,
“Analysis of process margins for emitter-base self-aligned structures by combination of simulation and experiment”, IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.113-116, October, 1992, Mineapolis, USA
[56] M. Saito, T. Yoshitomi, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, H. S. Momose, Y.
Katsumata, Y. Ushiku, H. Iwai, “An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics”, in IEDM Tech. Dig., pp.897-900,
December, 1992, San Francisco, USA
[57] Invited Talk: H. Iwai, “Application of T-CAD to Advanced Silicon Devices: Its Usage”,
Requirements and Problem, in Symposium on Semiconductor Modeling and Simulation Tech.
Dig., pp.11-14, March, 1993, Taipei, Taiwan, ROC
[58] C.Fiegna, H.Iwai, T Kimura, S.Nakamura, E.Sangiorgi, B.Riccò, “Monte Carlo Analysis of
Hot Carrier Effects in Ultra Small Geometry MOSFETs”, International Workshop on VLSI
Process and Device Modeling:VPAD, pp.102-103, May,1993. Nara, Japan.
[59] Y.Tsuboi, C. Fiegna, E.Sangiorgi, B.Riccò, T.Wada, Y.Katsumata, H.Iwai, “Analysis of
Collector Signal Delay in Bipolar Devices Using a Monte Carlo Method”, International
Workshop on VLSI Process and Device Modeling:VPAD,pp.98-99,May,1993, Nara, Japan
[60] S.Matsuda N.Itoh, C.Yoshino, Y.Tsuboi, Y.Katsumata, H.Iwai, “Analysis of Mechanical
Stress Associated with Trench Isolation Using a Two-Dimensional Simulation”, International
Workshop on VLSI Process and Device Modeling: VPAD, pp.64-65,May,1993 Nara, Japan
[61] Y.Ushiku, H.Ono, T.Iijima, N.Ninomiya, A.Nishiyama, H.Iwai, H.Hara, “Planarized Silver
Interconnect Technology with a Ti Self-Passivation Technique for Deep Sub-micron ULSIs”,
Digest of Technical Papers, Symposium on VLSI Technology, pp.121-122, May, 1993, Kyoto,
Japan
[62] T.Yoshitomi, M.Saito, H.Oguma, Y.Akasaka, M.Ono, H.Nii, Y.Ushiku, H.Iwai, H.Hara,
“Ultra-Shallow Buried-Channel P-MOSFET with Extremely High Transconductance”, Digest of Technical Papers, Symposium on VLSI Technology, pp.99-100, May, 1993, Kyoto, Japan
[63] S.Matsuda, N.Itoh, H.Nakajima, K.Inou, T.Iinuma,C.Yoshino, Y.Tsuboi, Y.Katsumata, H.Hara,
26
H.Iwai, “A Low Stress Trench Isolation Structure and Its Electrical Characteristics of 20 ps
High-Speed ECL”, Digest of Technical Papers, Symposium on VLSI Technology, pp.73-74,
May, 1993, Kyoto, Japan
[64] C.Fiegna, H.Iwai, T.Wada, T.Saito, E.Sangiorgi, B.Riccò, “A New Scaling Methodology for the 0.1-025µm MOSFET”, Digest of Technical Papers, Symposium on VLSI Technology , pp.33-34, May, 1993, Kyoto, Japan
[65] T.Ohguro,T.Morimoto,Y.Ushiku, H.Iwai, “Analysis of Anomalously Large Junction Leakage
Current of Nickel Silicided N-Type Diffused Layer and Its Improvement”, International
Conference on Solid State Devices and Materials, pp.192-194, August,1993, Chiba, Japan
[66] T.Iijima, H.Ono, N.Ninomiya, Y.Ushiku,T.Hatanaka,A.Nishiyama, H.Iwai, “Analysis of Ti
Self-Passivation on Silver Interconnects for ULSIs Applications”, International Conference on
Solid State Devices and Materials, pp.183-185,August ,1993, Chiba, Japan
[67] N.Itoh, Y.Katsumata, H.Iwai, “Noise figure degradation under emitter-base reverse stress for high-frequency bipolar Ics”, ESSDERC 93, pp. 727-730, September,1993, Grenoble, France
[68] C.Fiegna, H.Iwai, E.Sangiorgi, B.Ricco, “Analysis of Carrier Transport and Heating in
Ultra-Small SOI N-MOSFETs”, ESSDERC 93, pp. 675-678, September,1993, Grenoble,
France
[69] Invited Talk: H.Iwai, “CMOS Device Architecture and Technology for the 0.25Micron to
0.025 Micron Generation”, ESSDERC 93, pp. 513-520, September,1993, Grenoble, France
[70] T.Ohguro,T.Morimoto, A.Nishiyama, Y.Ushiku, H.Iwai, “Comparison of Ti and Ni salicide as regards the electrical conductance of silicided films”, ESSDERC 93, pp. 481-484,
September,1993, Grenoble, France
[71] Y.Katsumata, N.Itoh, H.Nakajima, K.Inou, T.Iinuma, S.Matsuda, C.Yoshino, Y.Tsuboi,
H.Iwai, “Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage”, ESSDERC 93, pp. 133-136, September,1993, Grenoble, France
[72] M.Ono,M.Saito, T.Yoshitomi, C.Fiegna, T.Ohguro, H.Iwai, “Sub-50 nm Gate Length
N-MOSFETs with 10nm phosphorus Source and Drain Junction,” in IEDM Tech.Dig., pp.119-122, December, 1993
[73] T.Ohguro, K.Yamada, N.Sugiyama, K.Usuda, Y.Akasaka, T.Yoshitomi, C.Fiegna, M.Ono,
M.Saito, H.Iwai, “Tenth Micron P-MOSFET’s with Ultra-Thin Epitaxial Channel Layer
Grown by Ultra-High Vacuum CVD”, in IEDM Tech.Dig.pp.433-436, December, 1993
[74] M.Ono, M.Saito, T.Yoshitomi, C.Fiegna, T.Ohguro, H.S.Momose, H.Iwai, “Influence of High
Substrate Doping Concentration on the Hot-Carrier and Other Characteristics of
Small-Geometry CMOS Transistors Down to the 0.1µm Generation”, Digest of Technical
Papers, Symposium on VLSI Technology, pp.147-148, June, 1994, Honolulu, Hawaii, USA
[75] Invited Talk: H.Iwai, Y.Katsumata, S.Matsuda, C.Yoshino, “Local Stress Analysis of
Semiconductor Devices”, Proceedings of 22 nd Symposium on ULSI Ultra Clean Technology, pp.252-264,August,1994
[76] K.Inou, S.Matsuda, N.Nakajima, N.Sugiyama, K.Usuda, S.Imai, Y.Kawaguchi, K.Yamada,
Y.Katsumata, H.Iwai, “52 GHz Epitaxial Base Bipolar Transistor with High Early Voltage of
26.5V with Box-like Base and Retrograded Collector Impurity Profiles”, IEEE
Bipolar/BiCMOS Circuits and Technology Meeting, pp.217-220,October,1994, Minneapolis,
USA
[77] N.Nakajima, N.Itoh, K.Inou, T.Iinuma, S.Matsuda, C.Yoshino, Y.Katsumata, H.Iwai, “0.5µm
Silicon Bipolar Transistor Technology for Analog Applications”, IEEE Bipolar/BiCMOS
Circuits and Technology Meeting, pp.213-216, October,1994, Minneapolis, USA
[78] N.Itoh, Y.Yoshida, S.Watanabe, Y.Katsumata, H.Iwai, “The Analysis of Silicon Bipolar
Transistor Scaling-Down Scheme for Low Noise and Low Power Analog Application”, IEEE
Bipolar/BiCMOS Circuits and Technology Meeting, pp.60-63, October, 1994, Minneapolis,
USA
[79] Invited Talk: H.Iwai, Y.Katsumata, M.Saito, “Solid-Phase Diffusion Technique”, Technical
Proceedings, SEMI Technology Symposium, pp.80-88, November, 1994
[80] C.Fiegna, H.Iwai, M.Saito, E.Sangiorgi, “Application of Semiclassical Device Simulation to
Trade-Off Studies Sub-0.1µm MOSFETs”, in IEDM Tech.Dig., pp.347-350, December, 1994
[81] S.Matsuda, C.Yoshino, H.Nakajima, K.Inou, T.Yoshitomi, Y.Katsumata, H.Iwai,
“Tree-Dimensional Mechanical Stress Analysis of Trench Isolation along{111}Gliding
Planes”, in IEDM Tech.Dig., pp.885-888, December, 1994
27
[82] H.S.Momose, M.Ono, T.Yoshitomi, T.Ohguro, S.Nakamura, M.Saito, H.Iwai, “Tunneling gate oxide approach to ultra-high current drive in small-geometry MOSFETs”, in IEDM Tech.Dig., pp.593-596, December, 1994
[83] M.Ono, M.Saito, T.Yoshitomi, C.Fiegna, T.Ohguro, H.Iwai, “Fabrication of Sub-50nm Gate
Length n-MOSFETs and their Electrical Characteristics”, Twenty-second Annual Conference on the Physics and Chemistry of Semiconductor Interfaces, p.SU1940, January, 1995
[84] T.Ohguro, M.Saito, K.Endo, M.Kakumoto, T.Yoshitomi, M.Ono, H.S.Momose, H.Iwai, “A
High Frequency 0.35 µm Gate Length Power Silicon NMOSFET Operating with Breakdown
Voltage of 13 V”, Proceeding of 1995 International Symposium on Power Semiconductor
Devices & Ics, pp.114-118, May, 1995, Yokohama, Japan
[85] Invited Talk: H.Iwai, H.S.Momose, Y.Katsumata, “Si-MOSFET Scaling Down to Deep-Sub
0.1-Micron Range and Future of Silicon LSI”, Proceeding of Technical Papers, International
Symposium on VLSI Technology, Systems, and Applications, pp.262-267, May, 1995, Taipei,
Taiwan, ROC
[86] C.Yoshino, K.Inou, S.Matsuda, H.Nakajima, Y.Tsuboi, H.Naruse, H.Sugaya, Y.Katsumata,
H.Iwai, “A 62.8 GHz fmax LP-CVD Epitaxially Grown Silicon Base Bipolar Transistor with
Extremely High Early Voltage of 85.7 V”, Digest of Technical Papers, Symposium on VLSI
Technology, pp.131-132, June, 1995, Kyoto, Japan
[87] M.Saito, M.Ono, R.Fujimoto, C.Takahashi, H.Tanimoto, N.Ito, T.Ohguro, T.Yoshitomi,
H.S.Momose, H.Iwai, “Advantage of Small Geometry MOSFETs for High-Frequency Analog
Applications under Low Power Supply Voltage of 0.5 V”, Digest of Technical Papers,
Symposium on VLSI Technology, pp.71-72, June, 1995, Kyoto, Japan
[88] T.Ohguro, N.Sugiyama, K.Imai, K.Usuda, M.Saito, T.Yoshitomi, M.Ono, H.S.Momose,
H.Iwai,”The influence of oxygen at epitaxial Si/Si substrate interface for 0.1 µm epitaxial Si channel N-MOSFETs grown by UHV-CVD”, Digest of Technical Papers, Symposium on
VLSI Technology, pp.21-22, June, 1995, Kyoto, Japan
[89] T.Yoshitomi, M.Saito, T.Ohguro, M.Ono, H.S.Momose, H.Iwai, “Silicided Silicon-Sidewall
Source and Drain (S 4 D) structure for high-performance 75-nm gate length pMOSFETs”,
Digest of Technical Papers, Symposium on VLSI Technology, pp.11-12, June, 1995, Kyoto,
Japan
[90] Invited Talk: H.Iwai, H.S.Momose, M.Saito, M.Ono, Y.Katsumata, “The future of ultra-small-geometry MOSFETs beyond 0.1 micron”, in 1995 INFOS, Villard-de-Lans, June,
1995, France : also Edited by S. Cristoloveanu and N.Gillemot, “Insulating Films on
Semiconductors 1995”, pp.147-154, 1995
[91] T.Yoshitomi, M.Saito, T.Ohguro, M.Ono, H.S.Momose, H.Iwai, “A High Performance 0.15
µm Single Gate CMOS Technology”, International Conference on Solid State Devices and
Materials, pp.222-224, August, 1995, Osaka, Japan
[92] K.Inou, Y.Katsumata, S.Matsuda, H.Naruse, H.Sugaya, H.Iwai, “Improvement of Narrow
Emitter Bipolar Transistor Performance by In-situ Highly Doped Arsenic Polysilicon
Technique”, IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp.93-96, September,
1995, Minneapolis, USA
[93] T.Ohguro, S.Nakamura, E.Morifuji, M.Ono, T.Yoshitomi, M.Saito, H.S.Momose, H.Iwai,
“Nitrogen-doped nickel monosilicide technique for deep submicron CMOS salicide”, IEDM
Tech. Dig., pp.453-546, December, 1995
[94] Invited Talk: H.Iwai, “Si-MOSFET downsizing into deep-sub-0.1 µm regime and images of future silicon LSIs towards 2010s”, FUET
96, International Symposium on the Basic of Future
Electronics technology, pp.57-64, February, 1996, Oiso, Japan
[95] Plenary Invited Talk: H.Iwai, W.Fichtner, R.W.Dutton, “TCAD for Sub-0.1 Micrometer Era –
Present Status & Future – “, 1996 Semiconductor Technology CAD Workshop & Exhibition, pp.1-42, May, 1996, Taiwan, ROC
[96] T.Ohguro, E.Morifuji, M.Saito, M.Ono, T.Yoshitomi, H.S.Momose, N.Ito, H.Iwai, “0.2 µm analog CMOS with very low noise figure at 2 GHz operation”, Digest of Technical Papers,
Symposium on VLSI Technology, pp.132-133, June, 1996, Honolulu, Hawaii, USA
[97] T.Yoshitomi, T.Ohguro, M.Saito, M.Ono, E.Morifuji, H.S.Momose, H.Iwai, “High
Performance 0.15 µm Single Gate Co Salicide CMOS”, Digest of Technical Papers,
Symposium on VLSI Technology, pp.34-35, June, 1996, Honolulu, Hawaii, USA
[98] Invited Talk: H.Iwai, “Ultra-small MOSFET Limits and Device Prospects for the Year 2010”,
28
IEEE Silicon Nanoelectronics Workshop, June, 1996, Honolulu, Hawaii,USA
[99] T.Yoshitomi, M.Saito, T.Ohguro, M.Ono, H.S.Momose, H.Iwai, “Hot-Carrier Reliability of
S 4 D n-MOSFETs”, ESSDERC ’96, pp.65-68, September, 1996, Bologna, Italy
[100] Plenary Invited Talk: H.Iwai, “Recent advances and future trends of ULSI technologies”,
ESSDERC’96, pp.46-52, September,1996, Bolonga, Italy
[101] H.S.Momose, S.Nakamura, Y.Katsumata, H.Iwai, “Thin Gate Dielectrics for future CMOS
Applications”, 27 th IEEE Semiconductor Interface Specialists Conference, 8.1, December,
1996, San Diego, California,USA
[102] H.S.Momose, E.Morifuji, T.Yoshitomi, T.Ohguro, M.Saito, T.Morimoto, Y.Katsumata, H.Iwai,
“High-frequency AC Characteristics of 1.5 nm Gate Oxide MOSFETs”, IEDM Tech. Dig., pp.105-108, December, 1996
[103] T.Ohguro,M.Saito, E.Morifuji, K.Murakami, K.Matsuzaki, T.Yoshitomi, T.Morimoto,
H.S.Momose, Y.Katsumata, H.Iwai, “High efficiency 2 GHz power Si-MOSFET design under low supply voltage down to 1V”, IEDM Tech. Dig., pp.83-86, December, 1996
[104] Invited Talk: H.Iwai, “Future High Performance Technologies for Sub-0.1 µm Devices”,
Semiconductor Technology Symposium, SEMICON Korea 97, pp.IV 30-39, February, 1997,
Korea
[105] T.Ohguro, S.Nakamura, E.Harakawa, E.Morifuji, T.Yoshitomi, T.Morimoto, H.S.Momose,
Y.Katsumata, H.Iwai, “Salicide Technology for Advanced CMOS Devices”, Semiconductor technology Symposium, SEMICON Korea 97, pp.
Ⅱ 57-66, February, 1997, Korea
[106] T.Ohguro, S.Nakamura, M.Saito, M.Ono, H.Harakawa, E.Morifuji, T.Yoshitomi, T.Morimoto,
H.S.Momose, Y.Katsumata, H.Iwai, “Ultra-shallow Junction and Salicide Techniques for
Advanced CMOS Devices”, Proceedings of the Sixth International Symposium on Ultralarge
Scale Integration Science and Technology, Electrochemical Society, pp.275-295, May, 1997
[107] H.S.Momose, S.Nakamura, Y.Katsumata, H.Iwai, “Ultra-thin Gate Oxide Technology for High
Performance CMOS”, Proceedings of the Sixth International Symposium on Ultralarge Scale
Integration Science and Technology, Electrochemical Society, pp.235-246, May, 1997
[108] Invited Talk: H.Iwai, “RF CMOS Technology”, Symposium on ULSI Technology & Systems,
May, 1997, Hsinchu, Taiwan, ROC
[109] H.S.Momose, S.Nakamura,T.Ohguro, Y.Katsumata, H.Iwai, “Uniformity and Reliability of
1.5nm direct tunneling gate oxide MOSFETs”, Symposium on VLSI Technology, pp.15-16,
June, 1997, Kyoto, Japan
[110] T.Ohguro, S.Nakamura, E.Morifuji, Y.Katsumata, H.Iwai, “0.25µm CoSi2 salicide technology thermally stable upto 1000C with high TDDB reliability”, Symposium on VLSI Technology, pp.102-103, June, 1997, Kyoto, Japan
[111] H.S.Momose, H.Iwai, “Low power, low voltage integrated circuit”, Internal Summer School on Advanced Microelectronics, June, 1997,Grenoble, France
[112] H.Iwai, “Silicon MOSFET scaling beyond 0.1µm”, International Microelectronics Conference, pp.11-18, Nis, September, 1997, Yugoslavia
[113] H.S.Momose, S.Nakamura, Y.Katsmata, H.Iwai, “Tunneking gate oxide MOSFET technology”, Europian Solid State Device Research Conference (ESSDERC), pp.133-143,
September, 1997, Ludwigberg, Germany
[114] H.Nii, C.Yoshino, H.Nakajima, Y.Katsumata, H.Iwai, “0.3µm BiCMOS technology for mixed analog/digital application systems”, IEEE bipolar/BiCMOS Circuit and Technology
Conference(BCTM), pp.68-71, September, 1997, Minneapolis, MN, USA
[115] H.Iwai, “CMOS downsizing and future concept of Si-LSI”, International Conference on
VCLSI and CAD, pp.162-167, November, 1997, Seoul, Korea
[116] H.S.Momose, S.Nakamura, T.Ohguro, Y.Katsumata, H.Iwai, “A study of hot-carrier degradation in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime”,
IEEE International Electron Devices Meeting (IEDM), pp.453-456, December, 1997,
Washington DC, USA
[117] T.Ohguro, H.Naruse, H.S.Momose, Y.Katsumata, H.Iwai, “0.18µm low voltage / low power
RF CMOS with zero Vtn analog MOSFEs made by undoped epitaxial channel technique”,
IEEE International Electron Devices Meeting (IEDM), pp.837-840, December, 1997,
Washington DC, USA
[118] Invited Talk: H. Iwai, “The downsizing of silicon devices and the impact on computers and communications”, International Conference on Computers and Devices for Communications
29
(CODEC’98), pp.4-13, January, 1998, Calcutta, India
[119] Invited Talk: H. Iwai, “Scaling CMOS below 0.1μm”, A Workshop Honoring of the Career of
Robert H. Dennard on the Occasion of the 320 th Anniversary of the 1-Transistor DRAM
Memory Cell, May, 1998, Yorktown Heights, NY, USA
[120] H. Iwai, “CMOS - year 2010 and beyond ; from technological side”, IEEE Custom Integrated
Circuit Conference (CICC’98), pp.141-148, May, 1998, Santa Clara, USA
[121] Invited Talk: Y. Unno, H. Iwai, “Future trends in semiconductor technologies, -- from industrial view point,” 1998 Advanced Research Workshop, Future Trends in Microelectronis:
Off the Beaten Path, May 31- June 5, 1998, Ile des Embiez, France
[122] H. S. Momose, S. Nakamura, Y. Katsumata, H. Iwai, “Study of direct-tunneling gate oxides fro
CMOS applications”, 3 rd International Symposium on Plasma-Induced Damage, pp.30-33,
June, 1998, Honolulu, Hawaii, USA
[123] T. Ohguro, H. Narus, H. Sugaya, S. Nakamura, E. Morifuji, H. Kimijima, T. Yoshitomi, T.
Morimoto, H. S. Momose, Y. Katsumata, H. Iwai, “High performance RF characteristics of raised gate/source/drain CMOS with Co salicide”, Dig. Tech., Symp on VLSI Tech., pp.136-137, June, 1998, Hololulu, Hawaii, USA
[124] T. Yoshitomi, H. Kimijima, S. Ishizuka, Y. Miyahara, T. Ohguro, E. Morifuji, T. Morimoto, H.
S. Momose, Y. Katsumata, H. Iwai, “A study of self-aligned doped channel structure for low power and low 1/f noise operation”, Dig. Tech., Symp on VLSI Tech., pp.98-99, June, 1998,
Hololulu, Hawaii, USA
[125] H. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Ohguro, T. Yoshitomi, H. Kimijima, S.
Nakamutra, T. Morimoto, Y, Katsumata, H. Tanimito, H. Iwai, “RF noise in 1.5 nm gate oxide
MOSFETs and the evaluation of NMOS LNA circuit integrated on a chip”, Dig. Tech., Symp on VLSI Tech., pp.96-97, June, 1998 , Honolulu, Hawaii,USA
[126] E. Morifujim C. E. Biber, W. Bachtold, T. Ohguro, T. Yoshitomi, H. Kimijima, T. Morimoto,
H. S. Momose, Y. Katsumata, H. Iwai, “RF noise study of small gate width Si-mOSFETs up to
8 GHz applications”, International Conference on Solid State Devices and Materiasl, pp.80-81,
September, 1998, Hiroshima, Japan
[127] Plenary Invited Talk: H. Iwai, “Current status and future of advanced CMOS technologies – digital and analog aspects --”, Int Conf. on Advanced Semiconductor Devices and
Microelectronics (ASDAM’98), pp.1-10, October, 1998, Smolenice, Slovakia
[128] Invited Talk: H. Iwai, “CMOS Scaling toward its limits”, Int. Conf. on Solid-State and
Integrated Circuit Technology (ICSICT’98), pp.31-34, October,1998, Beijing, China
[129] Invited Talk: H. Iwai, “Thin film technology for CMOS downsizing towards its limit”,
International Workshop on Development of Thin Film for Future ULSI's, p.17, 1998
[130] Invited Talk: H. Iwai, H. S. Momose, “Ultra-thin gate oxide – performance and reliability”,
Dig. Tech., pp.163-166, December, 1998, San Francisco, USA
[131] E. Morifujim T. Ohguro, T. Yoshitomi, H. Kimijima, T. Morimoto, H. S. Momose, Y.
Katsumata, H. Iwai, “Process induced damage on RFCMOS”, Tech. Dig. IEDM, Dig. Tech., pp.956-968, December, 1998, San Francisco, USA
[132] T. Ohguro, H. Naruse, H. Sugaya, H. Kimijima, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S.
Momose, Y. Katsumata, H. Iwai, “0.12µm Raised Gate/source/Drain Epitaxial Channel
NMOS Technology”, Tech. Dig. IEDM, Dig. Tech., pp.927-930, December, 1998, San
Francisco, USA
[133] H. S. Momose, H. Kimijima, S.Ishizuka, Y,. Miyahara, T. Ohguro, T. Yoshitomi, E. Morifuji,
S. Nakamura, T. Morimoto, Y. Katsumata, H. Iwai, “A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxides in the direct-tunneling regime”, Tech. Dig. IEDM, Dig.
Tech., pp.923-926, December, 1998, San Francisco, USA
[134] T. Yoshitomi, Y. Sugawara, E. Morifuji, T. Ohguro, H. Kimijima, T. Morimoto, H. S. Momose,
Y. Katsumata, H. Iwai, “On-chip spiral inductors with diffused shields using channel-stop implant”, Tech. Dig. IEDM, Dig. Tech., pp.540-543, December, 1998, San Francisco, USA
[135] Y. Katsumata, T. Ohguro, H. S. Momose, E. Morifuji, H. Iwai, “ RF CMOS technology,” 1998
Asa-Pacific Microwave Conference, Workshop, WS2. Leading Edge Silicon Devices and
Their Applications to Microwave/Millimeter-Wave Circuits, pp.3-20, December, 1998,
Yokohama, Japan
[136] Plenary Invited Talk: H. Iwai, “RF CMOS technology”, Int, Electron Devices and Material
Symposia (IEDMS’98), pp.1-01, December, 1998, Tainan, Taiwan, ROC
30
[137] H. Iwai, “Downsizing of CMOS Towards Deep Sub-0.1 Micro-Meter and its Limitation”, The
6th Korean Conference on Semiconductors, pp.1-4, February, 1999, Korea
[138] H. Kimijima, T. Ohguro, B. Evans 、 B. Acker, J. Bloom, H. Mabuchi, D.-L. Kwong, E.
Morifuji, T. Yoshitomi, H.S. Momose, M. Kinugawa, Y. Katsumata, H. Iwai, “Improvement of
1/f noise by using VHP(Vertical High Pressure) oxynitride gate insulator for deep-sub micron
RF and analog CMOS”, 1999 Symposium on VLSI Technology, pp. 119-120, June,1999,
Kyoto, Japan
[139] J.-S. Goo, C.-H. Choi, E. Morifuji, H.S. Momose, Z. Yu, H. Iwai, T.H. Lee, W. Dutton, “RF
Noise Simulation for Submicron MOSFET's Based on Hydrodynamic Model”, 1999
Symposium on VLSI Technology, pp.153-154, June ,1999, Kyoto, Japan
[140] E. Morifuji, H.S. Momose, T. Ohguro, T. Yoshitomi, H. Kimijima, F. Matsuoka, M. Kinugawa,
Y.Katsumata, H. Iwai, “Future perspective and scaling down roadmap for RF CMOS”, 1999
Symposium on VLSI Technology, pp.163-164, June,1999, Kyoto, Japan
[141] E. Morifuji, T. Ohguro, H. Kimijima, T. Yoshitomi, H. S. Momose, Y. Katsumata, K. Ishimaru,
F. Matsuoka, M. Kinugawa, H. Iwai, “RF modeling for 0.1µm gate length MOSFETS”, 29th
European Solid-State Device Research Conference, pp.656-659, September ,1999, Leuven,
Belgium
[142] Invited Talk: H. Iwai, “Scaling laws of CMOS - How this can be driven?”, Litho Workshop, A path towards sub-100nm lithography 、 IMEC, pp.1-14, September,1999, Leuven, Belgium
[143] Invited Talk: H. Iwai 、 Y. Katsumata, T. Ohguro, E. Morifuji, H.S. Momose, K. Inoh, H. Nii,
“Advanced Silicon BIPOLAR, BICMOS and CMOS technologies for RF Applications”,
EUMW (Europian Microwave)-Workshop 1999, Silicon and SiGe Technologies and Circuits, pp.4-7, October 1999, Munich, Germany
[144] T. Yoshitomi, Y. Ebuchi, H. Kimijima, T. Ohguro, E. Morifuji, H. S. Momose, K. Kasai, K.
Ishimaru, F. Matsuoka, Y. Katsumata, M. Kinugawa, H. Iwai, “High Performance MIM
Capacitor for RF BiCMOS/CMOS LSIs”, Proceedings of the 1999 BIPOLAR/BiCMOS
Circuits and Technology Meeting (BCTM), pp.133-136, September,1999, Minneapolis,
Minnesota, USA
[145] Invited Talk: H. Iwai, T. Ohguro, E. Morifuji, T. Yoshitomi, H. Kimijima, H. S. Momose, K.
Inoh, H. Nii, Y. Katsumata, “Advanced RF CMOS Technology”, Proceedings of SPIE (The
International Society for Optical Engineering)-Electronics and Structures for MEMS, pp.10-20,
October, 1999, Queensland,Australia
[146] T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, N. Sugiyama, E. Morifuji, H. Kimijima, T.
Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai, “Silicon Epitaxy and Its
Application to RFIC's”, The First Symposium on ULSI Process Integration, Electrochemical
Society Proceedings, Vol.99-18, pp.123-141 in the 196 th Meeting of the Electrochemical
Society, pp.123-141, October 1999, Honolulu 、 Hawaii, USA
[147] Invited Talk: H. Iwai, “Sub-100nm MOSFET technologies”, International Symposium on
Surface Science for Micro-and Nano-Device Fabrication, pp.5, November, 1999, Tokyo, Japan
[148] Plenary Invited Talk: H. Iwai, “Problems for downsizing of CMOS below 0.1 µm and attempts for solution by introduction of new materials, structures and planarization”,
International CMP Symposium '99, November, 1999 , Tokyo, Japan
[149] Invited Talk: H. Iwai, “Next-generation RF silicon device technology for mobile telecommunication”, 1999 The 20th Modern Engineering and Technology Symposium,
December, 1999 , Taipei, Taiwan, ROC
[150] H.S.Momose, E.Morifuji, H.Sugaya, S.Nakamura, T.Yoshitomi, H.Kimijima, T.Morimoto,
F.Matsuoka, Y.Katsumata, H.Ishiuchi, H.Iwai, “Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique”, International Electron Devices Meeting 1999, pp.819-822,
December, 1999, Washington DC, USA
[151] H. Iwai, “Source Drain and Wells”, Sub-100nm CMOS, 1999 IEDM Short Course, pp.1-95,
December,1999, Washington DC, USA
[152] Invited Talk: H. Iwai, “Sub-100nm MOSFET Technologies”, ISSS 2000, February, 2000,
India
[153] Invited Talk: H. Iwai, T. Ohguro 、 E. Morifuji, T. Yoshitomi, H. Kimijima, H. S. Momose, S.
Ohmi, K. Inoh, H. Nii, Y. Katsumata, “CMOS Technologies for High Frequencies”, GHz2000
Symposium, pp.41-45, March, 2000, Göteborg, Sweden
31
[154] Plenary Invited Talk: H. Iwai, H. S. Momose, S. Ohmi, “Ultra-thin gate SiO
²
technology”, proceedings of The Fourth International Symposium on The Physics and Chemistry of SiO
²
Interface, Electrochemical Society, pp.3-17, also in the Meeting Abstracts, the 197th Meeting of the Electrochemical Society, Vol.2000-1, p.443, May 14-18, 2000, Toronto, Canada
[155] Invited Talk: H. Iwai, “CMOS Technology for RF Application”, presented at the 22nd
International Conference On Microelectronics (MIEL 2000), pp.27-34, May, 2000, Niš,
Yugoslavia
[156] Invited Talk: H. Iwai, “High-speed low-power CMOS technology”, conference proceedings of the SEMICON Kansai 2000, Session 3, pp.42-51, June 1-2, 2000
[157] Invited Talk: H. Iwai, S. Ohmi, “Future CMOS Technology below 0.1µm”, SBMicro2000, pp.2-17, September 18-24, 2000, Manaus, Amazonas, Brazil
[158] Plenary Invited Talk: H. Iwai, S. Ohmi, “Problems and solutions for downsizing CMOS below 0.1µm”, Proceedings for 2000 IEEE International Conference on Semiconductor
Electronics (ICSE2000), pp.1-19, November 13-15, 2000, Malaysia
[159] Invited Talk: H. Iwai, “Gate Oxide Film and Small-Geometry MOS Devices”, Abstracts, Joint
Workshop of 29th IUVSTA International Workshop on Selective and Functional Film
Deposition Technologies as Applied to ULSI Technology, and 2nd International Workshop on
Development of Thin Films for Future ULSI's and Nano-Scale Process Integration, Ise-Shima, pp.108-122, November 19-24, 2000, Mie, Japan
[160] R. Fujimura, K.Sato, M. Takeda, S. Ohmi, H. Ishiwara, H. Iwai, “The relation between dielectric constant and short-channel effects for high-k gate insulator film's MOSFETs down to sub 50nm”, Abstracts, Joint Workshop of 29th IUVSTA International Workshop on Selective and Functional Film Deposition Technologies as Applied to ULSI Technology, and 2nd
International Workshop on Development of Thin Films for Future ULSI's and Nano-Scale
Process Integration, Ise-Shima, pp.165-169, November 19-24, 2000, Mie, Japan
[161] K. Osima, E. Tokumitsu, S. Ohmi, H. Iwai, H. Ishiwara, “Electrical Characteristics of High
Dielectric Constant ZrO2 Thin Films Prepared by Ultra High Vacuum-Electron Beam
Evaporation Method”, Abstracts, Joint Workshop of 29th IUVSTA International Workshop on
Selective and Functional Film Deposition Technologies as Applied to ULSI Technology, and
2nd International Workshop on Development of Thin Films for Future ULSI's and Nano-Scale
Process Integration, Ise-Shima, pp.323-326, November 19-24, 2000, Mie, Japan
[162] Invited Talk: H. Iwai, “Silicon Technology-Miniaturization from past to future”, Inauguration
Workshop of the Microtechnology Center at Chalmers, MC2, March 1, 2001 Gőteborg,
Sweden
[163] Invited Talk: H. Iwai, T. Ohguro, S. Ohmi, “NiSi Salicide Technology for Scaled CMOS”,
Abstract, European Workshop Materials for Advanced Metallization (MAM2001), p.07.5,
March 5-7, 2001 ,Sigtuna, Sweden
[164] Plenary Invited Talk: H. Iwai, S. Ohmi, “ULSI Process Integration for 2005 and beyond”,
ULSI Process Integration II, Electrochemical Society Proceedings Volume 2001-2, pp.3-33,
2001, also Abstract No.395, Meeting Abstracts, The 199th Meeting of The Electrochemical
Society, March 25-29, 2001
[165] R. Fujimura, M. Takeda, K. Sato, S. Ohmi, H. Ishiwara, H. Iwai, “Enhanced short-channel effects of sub-50nm gate length MOSFETs with high-k gate insulator films”, ULSI Process
Integration II, Electrochemical Society Proceedings Vol. 2001-2, pp.313-323, 2001, also
Abstract No.421, Meeting Abstracts, The 199th Meeting of The Electrochemical Society,
March 25-29, 2001
[166] H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, H. Iwai, “Study of wafer orientation dependence on performance and reliability of CMOS with direct-tunneling gate oxide”, 2001 Symposium on VLSI Technology, Kyoto, Digest of Technical Papers, pp.77-78,
June 12-14, 2001
[167] H. Iwai, S. Ohmi, “Gate dielectrics for deep sub-0.1 μm CMOS”, FTM 2001 Poster
Presentations, Scientific Program, 2001 Advanced Research Workshop, Future Trends in
Microelectronics: The Nano Millennium, p.45, June 25-29, 2001, Ile de Bendor, France
[168] Keynote Invited Talk: H. Iwai, “Direction of Silicon Technology from Past to Future”,
Keynote address, 8th International Symposium on the Physical & Failure Analysis of
Integrated Circuits, IPFA 2001, Proceedings, pp.1-35, July 9-13, 2001, Singapore
[169] Invited Talk: H. Iwai, S. Ohmi, “Problems and expected solutions for the gate oxide thinning
32
in miniaturized CMOS ULSI devices”, International Workshop on Device Technology,
Alternatives to SiO
2
as Gate Dielectric for Future Si-Based Microelectronics, p.16, September
3-5, 2001, Porto Alegre, Brazil, also 2001 MRS Workshop Series, pp.1-12, 2001
[170] S. Ohmi, C. Kobayashi, E. Tokumitsu, H. Ishiwara, H. Iwai, “Low Leakage La
2
O
3
Gate
Insulator Film with EOTs of 0.8-1.2 nm”, the 2001 International Conference on Solid State
Devices and Materials, pp.496-497, 2001
[171] S. Ohmi, S. Akama, A. Kikuchi, I. Kashiwagi, C. Ohshima, J. Taguchi, H. Yamamoto, C.
Kobayashi, K. Sato, M. Takeda, K. Oshima, H. Ishiwara, H. Iwai, “Rare Earth Metal Oxide
Gate Thin Films Prepared by E-beam Deposition”, International Workshop on Gate Insulator
2001, pp200-204, November 2001,Tokyo, Japan
[172] Invited Talk: H. Iwai, “Silicon technology trend from past to future”, IEEE Electron Devices and Solid-State Circuits Society Bangalore Chapter, March, 2002, India
[173] Invited Talk: H. Iwai, S. Ohmi, “CMOS Downsizing and High-k Gate Insulator Technology”,
Fourth IEEE International Caracas Conference on Devices, Circuits and Systems, pp.D049_1-8,
April 17-19, 2002, Aruba
[174] S. Ohmi, S. Akama, A. Kikuchi, I. Kashiwagi, C. Ohshima, J. Taguchi, H. Yamamoto, K. Sato,
M. Takeda, H. Ishiwara, H. Iwai, “Rare earth metal oxides for high-k gate insulator”, 201 st
ECS Meeting, abstracts vol.2002-1, pp.585, May 12-17 2002, Philadelphia U.S.A., also Proc. of the Ninth International Symposium on Silicon Material Science and Technology,
Semiconductor Silicon 2002, pp. 376-383
[175] H. Iwai: Advanced Device Technologies for sub-65nm Node FEOL; Varian semiconductor equipment vTech 2002, July, 2002
[176] S. Ohmi, M.Takeda, H.Ishiwara, H. Iwai: Characterization of Lu
2
O
3
High-k Thin Films on
Si(100) Fabricated by E-beam Deposition Method; Abstract of ISTC2002, September, 2002
[177] S.Ohmi, I.Kashiwagi, C.Ohshima, J.Taguchi, H.Yamamoto, J.Tonotanim H.Ishiwara, H.Iwai:
Electrical Characteristics of Rare Earth Gate Oxides Improved by Chemical Oxide and Long
Low Temperature Annealing; Abstracts of the 2002 International Conference on SSDM, pp.718-719, September, 2002
[178] T.Shiraishi, T.Nakamura, K.Takahashi, I.Kashiwagi, C.Ohshima, H.Nohira, S.Ohmi, H.Iwai,
T.Hattori: Depth Profiling of High-K Dielectric/Si Interfacial Transition Layer; abstracts of international conference of SSDM, pp.758-759, September, 2002
[179] C. Ohshima, I. Kashiwagi, S. Ohmi, H. Iwai, “Electrical Characteristics of Gd
2
O
3 thin film deposited on Si substrate”, Proceedings of ESSDERC2002, pp.415-418, September, 2002
[180] S. Akama, A. Kikuchi, J. Tonotani, S. Ohmi, H. Iwai:, “Stability of High-k Thin Films in
Moisture Ambience - The Effect of Dissolution Gas from Acryl Apparatus-”, Proceedings of
ESSDERC2002, pp.587-590, September, 2002
[181] J. Taguchi, H. Yamamoto, J. Tonotani, S. Ohmi, H. Iwai, “Annealing Condition Dependence of Electrical Characteristics for Dy
2
O
3
/Si(100) Structures”, Proceedings of ESSDERC2002, pp.591-594, September, 2002
[182] Invited Talk: H.Iwai, S.Ohmi, “Trend of CMOS downsizing and its reliability”, Proceedings of ESREF2002, pp.1251-1258, October, 2002
[183] H. Yamamoto, J. Taguchi, S. Ohmi, H. Iwai, “Electrical Characteristics Improvement of Dy
2
O
3
Thin Films by In-situ Vacuum Anneal”, abstracts of ECS 202nd Meeting, October,2002
[184] H. Iwai, S. Ohmi, S. Akama, C. Ohshima, I. Kashiwagi, A. Kikuchi, J. Taguchi, H. Yamamoto,
I. Ueda, A. Kuriyama, J. Tonotani, Y. Kim, Y. Yoshihara, H. Ishiwa, “High Dielectric
Constant Gate Insulator Technology using Rare Earth Oxides”, abstracts of ECS 202nd
Meeting, October, 2002
[185] A. Kikuchi, S. Akama, S. Ohmi, H. Iwai, “Stability of High-k Thin Films for Wet Process” , abstracts of ECS 202nd Meeting, October, 2002
[186] I. Kashiwagi, C. Ohshima, S. Ohmi, H. Iwai, “Characteristics of High-k Gd
2
O
3
Films
Deposited on Different Orientation of Si Substrate”, abstracts of ECS 202nd Meeting, October,
2002
[187] H. Yamamoto, J. Taguchi, S. Ohmi, H. Iwai, “The Effect of In-situ Vacuum Anneal for
High-Dielectric Dy
2
O
3
Thin Films”, abstracts of μE-ED 2002, pp.16-17, October, 2002
[188] I. Kashiwagi, C. Ohshima, Y. Kim, S. Ohmi, K. Tsutsui, H. Iwai, “Dependence of Gd
2
O
3
Thin
Film Properties on Si Substrate Orientation”, abstracts of μE-ED 2002, pp.14-15, October,
2002
[189] A.Kikuchi, S. Akama, S. Ohmi, K. Tsutsui, H. Iwai, “High-k Gate Insulator Endurance against
33
Moisture Ambience and Wet Process”, abstracts of IEEE μE-ED 2002, pp.12-13,
October ,2002
[190] H. Iwai, “CMOS Downscaling Towards Its Limit”, abstracts of IEEE μE-ED 2002, pp.4-5,
October, 2002
[191] H. Iwai, “CMOS Scaling and Requested New Technologies”, Proceedings of SISC2002,
December, 2002
[192] H. Nohira, T. Shiraishi, T. Nakamura, K. Takahashi, M. Takeda, S. Ohmi, H. Iwai, T. Hattori,
“Chemical and Electronic Structures of Lu
2
O
3
/Si Interfacial Transition Layer”, abstracts of 4th
ISCSI, October, 2002
[193] C. Ohshima, J. Taguchi, I. Kashiwagi, H. Yamamoto, S. Ohmi, H. Iwai, “Effect of Surface
Treatment of Si substrates and Annealing Condition on High-k Rare Earth Oxide Gate
Dielectrics”, abstracts of 4th ISCSI, October, 2002
[194] H. Iwai, “Advanced CMOS Technology for Sub-70 nm and further below”, 1 st WIMNACT, pp.3-98, November, 2002
[195] F.Lime, K.Oshima, M.Cassé, G.Ghibaudo, S.Cristoloveanu, B.Guillaumot, H.Iwai, “Ellectrical
Characterization of Advanced CMOS Devices with Metal Gate and HFO
2
Gate Dielectric”,
Proceedings WoDIM 2002, pp.81-84, November, 2002
[196] Plenary Invited Talk: H.Iwai, “CMOS Scaling and Requested New Technologies”, 33 rd IEEE
SISC 2002, December, 2002
[197] Invited Talk: H.Iwai, S.Ohmi, S.Akama, C.Ohshima, A.Kikuchi, I. Kashiwagi, J.Taguchi,
H.Yamamoto, J.Tonotani, Y.Kim, I.Ueda, A.Kuriyama, Y.Yoshihara,“Advanced Gate
Dielectric Materials for Sub-100nm CMOS”, IEDM 2002, pp.625-628, December, 2002
[198] H.Iwai, “CMOS Downsizing toward sub-10 nm”, ULIS 2003, pp7-10, March, 2003
[199] Invited Talk: H.Iwai, “Prospects and Challenges for Advanced Gate-Stack Materials in Sub-65 nm CMOS”, 2003 MRS Spring Meeting, Abstracts, p.90, April, 2003
[200] Keynote Invited Talk: H.Iwai, “CMOS down scaling and process induced damages”, 2003 8 th
International Symposium on Plasma- and Process- Induced Damage, pp1-11, April, 2003
[201] K.Oshima, S.Cristoloveanu, B.Guillaumot, G.le Carval, H.Iwai, C. Mazure, M.S.Kang,
Y.H.Bae, M.W.Kwon, J.H.Lee, S.Deleonibus, “Replacing the BOX with Buried Alumina:
Improved Thermal Dissipation in SOI MOSFETs”, 203 rd ECS Meeting, Vol.2003-01, Abstract
No.815, 2003
[202] J.O.Borland, H.Iwai, W.Masazara, H.Wang, “Extending the Life of Planar Single-Gate CMOS
& the Realization of Double-Gate/Multi-Gate CMOS Devices”, 203 rd ECS Meeting,
Vol.2003-01, Abstract No.976, 2003
[203] T.Hattori, T.Yoshida, T.Shiraishi, K.Takahashi, H.Nohira, S.Joumori, K.Nakajima, M.Suzuki,
K.Kimura, I.Kashiwagi, C.Ohshima, S.Ohmi, H.Iwai, “Composition, Chemical Structure and
Electronic Band Structure of Rare Earth Oxide/Si(100) Interfacial Transition Layer”, INFOS
2003-Barcelona, WS1-9, June, 2003
[204]
H.Iwai, “The Future of CMOS Downscaling”, FTM(Future Trends in Microelectronics)-2003,
Corsica, France, p46, June, 2003
[205] J.O.Borland, H.Iwai, W.Maszara, H.Wang, “Extending Planar Single-Gate CMOS &
Accelerating the Realization of Double-Gate/Multi-Gate CMOS Devices”, ULSI Process
Integration III, Vol.2003-06, pp.330-345, 2003
[206] Plenary Invited Talk: H.Iwai, Advanced High K Dielectrics”, ESSDERC 2003, p.15,
September, 2003, Estoril, Portugal
[207] R.Higaki, K.Tsutsui, Y.Sasaki, S.Akama, B.Mizuno, S.Ohmi, H.Iwai, “Effects of gas phase absorption into Si substrates on plasma doping process”, ESSDERC 2003, pp.231-234,
September 200 , Estoril, Portugal
[208] Y.Kim, A.Kuriyama, I.Ueda, S. Ohmi, K.Tsutsui, H.Iwai, “Analysis of Electrical
Characteristics of La
2
O
3
Thin Films Annealed in Vacuum and Others”, ESSDERC 2003, pp.569-572, September, 2003, Estoril, Portugal
[209] S.Ohmi, H.Yamamoto, J.Taguchi, K.Tsutsui, H.Iwai, “Effect of Vacuum Annealing on High-k
Dy
2
O
3
Thin Films Deposited on Si(100)”, SSDM 2003, pp.510-511, September, 2003 ,Tokyo,
Japan
[210] Plenary Invited Talk: H.Iwai, “CMOS Downscaling”, IUMRS-ICAM 2003, p.110, October
8-13,2003, Yokohama, Japan
[211] I.Ueda, S.Ohmi, H.Iwai, “Electrical Characteristics of High-K Stack Gate Dielectric Thin
Films with La
2
O
3
as Buffer Layer”, 204 th ECS Meeting Orlando, Abs.545, October12-16,
2003, Florida, U.S.A.
34
[212] H.Sauddin, Y.Yoshihara, S.Ohmi, K.Tsutsui, H.Iwai, “Low-Frequency Noise Characteristics of MISFET’s with La
2
O
3
Gate Dielectrics”, ECS 204 th Meeting Orlando, Abs.546,
October12-16, 2003, Florida, USA
[213] A.Kuriyama, S.Ohmi, K.Tsutusi, H.Iwai, “Effect of Post Metallization Annealing for La
2
O
3
Gate Thin Films on Electrical Characteristics”, ECS 204 th Meeting Orlando, Abs.564, October
12-16, 2003 , Florida, U.S.A.
[214] Y.Kim, S.Ohmi, K.Tsusui, H.Iwai, “Electrical Characteristics of High-k La
2
O
3
Thin Film
Deposited by E-Beam Evaporation Method”, ECS 204 th Meeting Orlando,Abs.582, October
12-16, 2003 , Florida, U.S.A.
[215] S.Ohmi, I.Ueda, Y.Kobayashi, K.Tsutsui, H.Iwai, “Electrical Characterstics of rare-earth oxides stacked-layer structures”, IWGI 2003 Tokyo, pp.28-31, November 6-7,2003, Tokyo.
Japan
[216] Invited Talk: H.Iwai, “CMOS Scaling toward sub-10nm regime”, EDMO2003,pp.30-34,
November, 17-18,2003, Orlando, Florida, USA
[217] Plenary Invited Talk: H.Iwai, “Scaling of Advanced CMOS”, IWPSD2003, pp.13-18,
December, 2003, Chennai, India
[218] Plenary Invited Talk: H.Iwai, “CMOS Scaling Challenge to sub-10 nm”, CODEC-04, January
1-3,2004, Kolkata, India
[219] Plenary Invited Talk: H.Iwai, “CMOS Scaling for sub-90 nm to sub-10 nm”, VLSI2004, pp.30-35, January 5-9, 2004, Mumbai, India
[220] K.Tsusui, R.Higaki, Y.Sasaki, T.Sato, H.Tamura, B.Mizuno, H.Iwai, “Contribution and
Control of Neutral Gas Absorption Effects in the Plasma Doping of Boron into Si”,
IWJT-2004 pp.46-49, March 15-16, 2004, Shanghai, China
[221] C.G.Jin, Y.Sasaki, K.Tsutsui, H.Tamra, B.Mizuno, R.Higaki, T.Satoh, K.Majima, H.Sauddin,
K.Takagi, S.Ohmi, H.Iwai, “Estimation of Ultra-Shallow Plasma Doping (PD) Layer’s Optical
Absorption Properties by Spectroscopic Ellispsometry (SE)”, IWJT-2004, pp.102-103, March
15-16, 2004, Shanghai, China
[222] K.Tsutsui, Y.Sasaki, C.G.Jin, H.Tamura, B.Mizuno, R.Higaki, T.Sato, K.Majima, S.Ohmi,
H.Iwai, “Ultra Shallow p + /n Junctions Fabricated by Plasma Doping and All Solid State
Laser Annealing”, Proceedings of the International Symposium, 205 th Meeting of The
ElectrochemicalSociety,ProceedingVol.2004-01, pp.106-111, May, 2004, SanAntonio,USA
[223] Plenary Talk: H.Iwai, “FUTURE CMOS SCALING”, Proceeding of the 11 th International
Conference, Mixed Design of integrated circuits and systems, pp.19-23, MIXEDS 2004, June
24-26, 2004, Szczecin, Poland
[224] Y.Sasaki, C.G.Jin, H.Tamura, B.Mizuno, R.Higaki, T.Satoh, K.Majima, H.Sauddin, K.Takagi,
S.Ohmi, K.Tsutsui, H.Iwai, “B2H6Plasma Dopong with “In-situ He Pre-amorphization”, 2004
Symposium on VLSI Technology Digest of Technical Papers, pp.180-181, June 15-17, 2004,
Honolulu, USA
[225] Invited Talk: H.Iwai, “RF CMOS Technology”, 2004 Asia-Pacific Radio Science Conference
Proceedings, pp.296-298, August 24-27, 2004, Qingdao,China
[226] Invited Talk: H. Iwai, “Future of CMOS Technology”, 2004 Semiconductor Manufacturing
Technology workshop Proceedings, pp.5-8, Sep.9-10, 2004, Taiwan, ROC
[227] Y.Kim, S. Ohmi, K.Tsutsui, H.Iwai, “Space-Charge-Limited Current Conductions in La2O3
Thin Films Deposited by E-Beam Evaporation after Low Temperature Dry-Nitrogen
Annealing”, ESSDERC 2004, Proceeding of the 34 th European Solid-State Device Research
Conference, September 21-23, 2004, pp.81-84, 2004, Leuven, Belgium
[228] T. Sato, R. Higaki, H. Tamura, Y. Sasaki, B. Mizuno, K. Tsutsui, H. Iwai, “Effects of Wet
Cleaning Treatment on Dose of Impurity after Plasma Doping”, ESSDERC 2004, Proceeding of the 34 th European Solid-State Device Research Conference, September 21-23, 2004, pp.149-152, 2004
[229] J.Ng, S.Ohmi, K.Tsutsui, H.Iwai, “A Study of Aluminum Gate La2O3 nMISFET with Post
Metallization Anneal”, Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufactruing, 206 th Meeting of The Electrochemical Society, Proceedings Vol. 2004-04, pp.369-380, October, 2004, Hawaii, USA
[230] Y.Kim, S.Ohmi, K.Tsutsui, H.Iwai, “Electrical Conduction Processes in Lanthana Thin Films prepared by E-Beam Evaporation”, Dielectrics for Nanosystems: Materials Science, Processing,
Reliability, and Manufactruing, 206 th Meeting of The Electrochemical Society, Proceedings
Vol. 2004-04, pp.452-463, October, 2004, Hawaii, USA
[231] B. Mizuno, Y. Sasaki, C. Jin, H. Tamura, K. Okashita, H. Ito, K.Tsutsui, H.Iwai, “Plasama
Doping”, 7 th International Conference on Solid-State and Integrated Circuits Technology,
35
Proceedings, October 18-21, 2004, ICSICT 2004, Vol. I pp.423-427, Beijing, China
[232] K. Tsutsui, R. Higaki, T. Sato, Y. Sasaki, H.Tamura, B. Mizuno, H. Iwai, “Effects of Surface
Conditions on Dose Controllability of Plasma Doping Process”, 7 th International Conference on Solid-State and Integrated Circuits Technology, Proceedings October 18-21, 2004, ICSICT
2004, Vol. I pp.439-444, Beijing, China
[233] Invited Talk: H. Iwai, “CMOS Technology Future”, ICCDCS, pp.179-182, November 3-5,
2004, Punta Cana, Dominican Republic
[234] C.G. Jin, Y. Sasaki, K. Okashita, H. Tamura, H. Ito, B. Mizuno, K. Tsutsui, S. Ohmi, H. Iwai,
“Ultra Shallow p+/n Junction Formation by Plasma Doping (PD) and All Solid-State Laster
Annealing (ASLA) with Selective Absorption Modulation”, the 15 th International Conference on Ion Implantation Technology, IIT2004, October 25-29, 2004, Taipei, Taiwan, ROC
[235] Y. Sasaki, C.G. Jin, K. Okashita, H. Tamura, H. Ito, B. Mizuno, R. Higaki, T. Satoh, K.
Majima, H.Sauddin, K. Takagi, S. Ohmi, K. Tsutsui, H. Iwai, “New Method of Plasma Doping with In-Situ Helium Pre-Amorphization”, the 15 th International Conference on Ion
Implantation Technology, IIT2004, October 25-29, 2004, Taipei, Taiwan, ROC
[236] Plenary Talk: H. Iwai, “Future Semiconductor Manufacturing - Challenges and Opportunities”,
2004 IEEE International Electron Devices Meeting, December 13-15, 2004, pp.11-16, San
Francisco Hilton and Towers, San Francisco, USA
[237] H. Iwai, “Future of Si integrated devices and its manufacturing”, WOFE 2004 Advanced
Workshop on Frontiers Electronics, J. E. Irausquin Blvd 77 Palm Beach, December 18-22, p.72, 2004, Aruba
[238] K. Miyauchi, K. Nakagawa, K. Tsutsui, H. Iwai, “La2O3/Y2O3 Stack High-K Gate Insulator
Technique”, WOFE 2004 Advanced Workshop on Frontiers Electronics, J. E. Irausquin Blvd
77 Palm Beach, December 18-22, 2004, p.14, Aruba
[239] H. Iwai, “New Technology Study for Future Downscaling CMOS: High-k and Plasma
Doping” 6 th Workshop and IEEE EDS Mini-colloquia on Nanometer CMOS Technology,
National Chiao Tung University, January 21-22, 2005, pp.1-1 , Taiwan, ROC
[240] Invited Talk: H. Iwai, “Challenges for the CMOS roadmap and nanotechnology beyond
CMOS”, Workshop on Semiconductors and Micro & Nano-Technology SEMANTEC 2005, pp.1-4, March 4, 2005,Campinas, Brazil
[241] Y.Kobayashi, R.Xiang, K.Tsutsumi, H.Iwai, “Formation of heat resistant Ni silicide by additional Hf layers.”, Materials for Advanced Metallization (MAM2005), March 6-9, 2005,
Dresden, Germany
[242] I. Aiba, Y. Sasaki, K. Okashita, H. Tamura, Y. Fukagawa, K. Tsutsui, H. Ito, K. Kakushima, B.
Mizuno, H. Iwai, “Feasibility Study of Plasma Doping on Si Substrates with Photo-Resist
Patterns”, International Workshop on Junction Technology(IWJT), pp.71-72, June 7-8, 2005,
Osaka, Japan
[243] K. Tsutsui, K. Majima, Y. Fukagawa, Y. Sasaki, K. Okashita, H. Tamura, K. Kakushima, H.
Ito, B. Mizuno, H. Iwai, “Analysis of Conductivity in Ultra-shallow p+ Layers Formed by
Plasma Doping”, International Workshop on Junction Technology(IWJT), pp.73-74, June
7-8,2005, Osaka, Japan
[244] H. Sauddin, H. Tamura, K. Okashita, Y. Sasaki, H. Ito, B. Mizuno, K. Kakushima, K. Tsutsui,
H. Iwai, “Reverse Current of Plasma Doped p+/n Ultra-Shallow Junction”, International
Workshop on Junction Technology(IWJT), pp.75-76, June 7-8,2005, Osaka, Japan
[245] Tutrial:
H. Iwai, “High-K Gate Stack Technology”, ESSDERC 2005, September 12-16, 2005,
Grenoble, France
[246] K. Nakagawa, K. Miyauchi, K. Kakushima, T. Hattori, K. Tsutsui, H. Iwai, “The Effect of
Y
2
O
3
Buffer Layer for La
2
O
3
Gate Dielectric Film”, ESSDERC 2005, pp.387-389, September
12-16, 2005, Grenoble, France
[247] S. Yoshizaki, Woei Yuan Chong, M. Nakagawa, Y. Nara, M. Yasuhira, F. Ohtsuka, T.
Arikado, K. Nakamura, K. Kakushima, K. Tsutsui , H. Aoki, H. Iwai, “RF Modeling of Sub ‐
100 nm CMOS”, ESSDERC 2005, September 12-16, 2005, Grenoble, France
[248] Keynote Address:
H. Iwai, “Silicon Integrated Circuit Technology and MANUFACTURING
Innovations for the Past and the Next 30 Years”, 22nd International VLSI Multilevel
[249]
Interconnection Conference, pp.25-27, October 4-6, 2005, Fremont, USA
E.Miranda J.Molina, Y.Kim, H.Iwai,
“
Degradation of High-K La
2
O
3
gate Dielectrics using
Progressive Electrical Stress
”, the 16 th European Symposium on Reliability of Electron
Devices, October 12, 2005, Bordeaux, France
[250] H. Nohira, T. Yoshida, H. Okamoto, W. Sakai, K. Nakajima, M. Suzuki, K. Kimura, Ng Jin
Aun, Y. Kobayashi, S. Ohmi, H. Iwai, E. Ikenaga, “THERMAL STABILITY OF
36
LANTHANUM OXIDE/Si(100) INTERFACIAL TRANSITION LAYER”, ECS 208 th
Meeting, ECS Transaction, Vol.1, No.1, pp.87-95, October 16-20, Los Angeles, USA
[251] H. Iwai, “CMOS Scaling and its Future towards Downsizing Limit”, IEEE EDS WIMNACT-9,
2005, October 25, 2005, Yokohama, Japan
[252] Y. Kuroki, Jin-Aun Ng, K. Kakushima, N. Sugii, K. Tsutsui, H. Iwai, “Al/La
2
O
3
Analysis of
Post Metallization Annealed MISFETs by XPS”, ECS 208 th Meeting, Vol. 1, No.5, pp.239-247,
October 17-20, 2005, Los Angeles, USA
[253] J. Molina, K.Kakushima, P. Ahmet, S. Nobuyuki, K. Tsutsui, H. Iwai, “BREAKDOWN AND
RELIABILITY OF METAL GATE-La
ANNEALING IN N
2
2
O
3
THIN FILMS AFTER POST-DEPOSITION
”, ECS 208 th Meeting, Vol. 1, No. 5, pp.757-765, October 17-20, 2005,
Los Angeles, USA
[254] Invited Talk: H. Iwai, “Future of CMOS Scaling and Its Manufacturing”, IWPSD-2005, pp.55-66, December 13-17, 2005, New Delhi, India
[255] Invited Talk: H. Iwai, “Future CMOS Technology and Manufacturing”, EPMDS-2006,
Vol.1-1, January 4-6, 2006, Kolkata, India
[256] H. Iwai, “Recent Status an Nano CMOS and Future Direction”, IWNC2006, pp.1-5, January
30-31, 2006, Mishima, Japan
[257] K. Tsutsui, Y. Sasaki, K. Majima, Y. Futagawa, I. Aiba, R. Higaki, C. Jin, H. Ito, B. Mizuno,
J.A.Ng, K. Tachi, J. Song, Y. Shiino, K. Kakushima, P. Ahmet, H. Iwai, “Ultra-shallow
Junction and High-k dieletric for Nano CMOS”, IWNC2006, pp.56-68, January 30-31, 2006,
Mishima, Japan
[258] H. Wong, K. Kakushima, H. Iwai, “Material and Interface Instabilities of High-k MOS Gate
Dielectric Films”, IWNC2006, pp.169-174, January 30-31, 2006, Mishima, Japan
[259] Manoj C. R., A. Mangal, V. R. Rao, K. Tsutsui, H. Iwai, “Parasitics Effects in Multi Gate
MOSFETs”, IWNC2006, pp.255-260, January 30-31, 2006, Mishima, Japan
[260] I. Aiba, Cheng-Guo Jinm, Y. Sasaki, K. Tsutsui, H. Tamura, K. Okashita, H. Kakushima, H.
Iwai, “Photo Resist Removal Process Using Wet Treatment After Plasma Doping” ,
ISTC-2006, Vol.1, pp.295-296, March 21-22, 2006, Shanghai, China
[261] K. Tsutsui, Y. Sasaki 、 Cheng-Guo Jin, H. Tamura, K. Okashita, H. Ito, B. Mizuno, H.
Sauddin, K. Majima, T. Satoh, Y. Fukagawa, K. Kakushima, H. Iwai, “Formation of
Ultra-shallow Junctions by Plasma Doping”, ISTC-2006, Vol. 1, pp.232-241, March 21-22,
2006, Shanghai, China
[262] A. Fukuyama, K. Kakuashima, P. Ahmet, A.N.Chandorkar,K. Tsutsui, N. Sugii, T. Hattori, H.
Iwai, “Analysis of Voltage Coefficient and Leakage Current of La
2
O
3
Mim Capacitor”,
ISTC-2006, Vol.1 pp.225-231, March 21-22, 2006, Shanghai, China
[263] R. Xiang, K. Nagahiro, T. Shiozawa, P. Ahmet, K. Tsusui, Y. Okuno, M. Matsumoto, M.
Kubota, K. Kakushima, H. Iwai,
“Irregular Increase in Sheet Resistance of Ni Silicides at
Transition Temperature Range from NiSi to NiSi2 Depending on Annealing Time”,
ISTC-2006, March 21-22, 2006, Shanghai, China
[264] P. Ahmet, T. Nagata, D. A. Kukuruznyak, K. Ohmori, K. Kakushima, K. Tsutsui, T.Chikyou,
H.Iwai, “Combinatorial Fabrication and Phase Diagramming of Ternary Composition Spreads”,
ISTC-2006, Vol.1 pp.215-224, March 21-22, 2006, Shanghai, China
[265] Invited Talk: H.Iwai, “CMOS Scaling and Future Manufacturing”, 2006-IWNE, pp.3-47,
April 21, 2006, Tainan, Taiwan
[266] Keynote Speech:
H.Iwai, “Semiconductor Manufacturing Technology in the 21st Century”,
2006 VLSI-TSA, pp.1-17, April 24-26, 2006, Hsinchu, Taiwan
[267] K.Shiraishi, T.Nakayama, Y.Akasaka, S.Miyazaki, T.Nakaoka, K.Ohmori, P.Ahmet, K.Torii,
H.Watanabe, T.Chikyow, Y.Nara, H.Iwai, K.Yamada, “New Theory of Effective Work
Functions at Metal/High-k Dielectric Interfaces-Application to Metal/High-k HfO
2
And La
2
O
3
Dielectric Interfaces-” , ECS 209 th Meeting, ECS Transactions, Vol. 2, No.1, pp.25-40, May
7-12, 2006, Denver, USA
[268] P.Ahmet, T.Nagata, D.A.Kukuruznyak, K.Ohmori, K.Kakushima, K.Tsutsui, T.Chikyow,
H.Iwai, “Combinatorial Fabrication and Characterization of Oxide and Metal Thin Film
Composition Spreads”, ECS 209 th Meeting, ECS Transactions, Vol. 2, No.1, pp.79-90, May
7-12, 2006, Denver, USA
[269] K.Kakushima, P.Ahmet, N.Sugii, K.Tsutsui, T.Hattori, H.Iwai, “Lanthanum Oxides for Gate
Insulator Application”, ECS 209 th Meeting, ECS Transactions, Vol. 2, No.1, pp.115-127, May
7-12, 2006, Denver, USA
[270] T.Hattori, K.Kakushima, K.Nakajima, H.Nohira, K.Kimura, H.Iwai, “Angle-Resolved
Photoelectron Spectroscopy Study on Gate Insulators”, ECS 209 th Meeting, ECS Transactions,
37
Vol. 2, No.1, pp.275-286, May 7-12, 2006, Denver, USA
[271] J.A.Ng, N.Sugii, K.Kakushima, P.Ahmet, T.Hattori, K.Tsutsui, H.Iwai, “Mobility Degradation
Analysis for La
2
O
3
nMOSFET”, ECS 209 th Meeting, ECS Transactions, Vol. 2, No.1, pp.329-338, May 7-12, 2006, Denver, USA
[272] K.Tsutusi, R.Xiang, K.Nagahiro, T.Shiozawa, P.Ahmet, Y.Okuno, M.Matsumoto, M.Kubota,
K.Kakushima, H.Iwai, “Irregular Increase in sheet Resistance of Ni Sikicides at Temperature
Range of Transition from NiSi to NiSi
2
”, IWJT-2006, pp.188-191, May 15-16, 2006, Shanghai,
China
[273] Invited Talk: H. Iwai, “La
2
O
3
Gate Oxide Technology for MOSFETs”, The-E-MRS 2006
Spring Meeting,May 29, 2006, Nice, France
[274] J.Song, A.Fukuyama, K.Kakushima, P.Ahmet, K.Tsutsui, T.Hattori, H.Iwai, “Characteristics of La
2
O
3
/Ge MIS Capacitors on Annealing Condition”, The-E-MRS 2006 Spring Meeting, Vol.
1-1, May 29, 2006, Nice, France
[275] Invited Talk, Distinguished Lecture: H.Iwai, “Future CMOS Scaling and Its Manufacturing”,
AdCom &ExCom Meeting Mini-Colloquia, June 1, 2006, Napoli, Italy
[276] K.Kakushima, P.Ahmet, J.A.Ng J.Molina,H.Sauddin,Y.Kuroki, K.Nakagawa,A.Fukuyama,
K.Tachi, Y.Shiino, J.Song, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai, “Study of La
2
O
3
Gate
Dielectric Suitability for Future MIM and MOSFETs”, 2006 IEEE Si Nanoelectronics
Workshop, p.113, June 12, 2006, Honolulu, Hawaii, USA
[277] H.Iwai, “Future of nano CMOS and its manufacturing”, FTM, p.47, June 27, 2006, Heraklion,
Crete
[278] Invited Talk, Distinguished Lecture: H.Iwai, “High Dielectric Constant Gate Insulator
Technology”, WIMNACT Mini-Colloquium, July 4, 2006, Singapore
[279] Keynote Speech: H.Iwai, “Future of Nano-CMOS Technology and Its Production”, IPFA2006, pp.1-17, July 5, 2006, Singapore
[280] E.Miranda, H.Iwai, “ Modeling of the Leakage Current in Ultrathin La
2
O
3
Films Using a
Eneralized Power Law Equation ”, IPFA2006, pp.306-310 ,July 7, 2006, Singapore
[281] Invited Talk, Distinguished Lecture: H.Iwai, “ Nano-CMOS and Its Manufacturing”, EDS
Tsinghua Student Chapter Opening Ceremony, July 10, 2006, Beijing, China
[282] Invited Talk: H. Iwai, “Histrical Trends and Future Perspectives of Silicon Technology
Scaling”, SINANO Summer School 2006, Bologna, Italy
[283] A.Kuriyama, O. Faynot, L. Brevard, A. Tozzo, L.Clerc, J.Mitard, V. Vidal, S. Deleonibus,
S.Cristoloveanu, H. Iwai, “ Precise Extraction of Metal Gate Work Function from Bevel
Structures”, Solid State Devices and Materials Yokohama 2006, pp.210-211, September 13-15,
2006, Japan
[284] K. Ohmori, P.Ahmet, K. Shiraishi, K. Yamabe, H. Watanabe, Y. Akasaka, N. Umezawa, K.
Nakjima, M.Yoshitake, T. Nakayama, K.-S. Chang, K. Kakushima, Y. Nara, M.L. Green,
H.Iwai, K. Yamada, T. Chikyow,
“
Wide Controllability of Flatband Voltage in La
2
O
3
Gate
Structures-Remarkable Advantages of La
2
O
3 over HfO
2
-”, Solid State Devices and Materials
Yokohama 2006, pp.432-433, September 13-15, 2006, Japan
[285] Keynote Talk:
H. Iwai, “Academia-Industry collaborations in Japan in the field of
Nanoelectronics”, ENIAC-MEDEA+ Workshop, ESSDERC/ESSCIRC 2006, September 22,
2006, Montreux, Switzerland
[286] Invited Talk: H. Iwai, “CMOS for next 15 years as the mainstream of nano device technology: problems, solutions and beyond that”, SINANO Workshop, ESSDERC/ESSCIRC 2006,
September 22, 2006, Montreux, Switzerland
[287] M. Nakagawa, J. Song, Y. Nara, M. Yasuhira, F. Ohtsuka, T. Akikado, K. Nakamura,
K.Kakushima, P.Ahmet, K.Tsutsui, H. Iwai, “High Frequency Model of Sub-100nm High-k
RF CMOS”, Satellite workshop to ESSDERC/ESSCIRC 2006, September 22,2006, Montreux,
Switzerland
[288] A.Kuriyama, O. Faynot, L. Brevard, A. Tozzo, L.Clerc, S. Deleonibus, J. Mitard, V. Vidal, S.
Cristoloveanu, H.Iwai,
“
Work Function Investigation in Advanced Metal Gate-HfO
2
-SiO
2
Systems with Bevel Structures
”,
ESSDERC 2006, pp.109-112,September 19, 2006, Montreux,
Switzerland
[289] K. Tsutsui, Y. Sasaki, C-G. Jin, H. Sauddin, K. Majima. Y. Fukagawa, I. Aiba, H. Ito, B.
Mizuno, K. Kakushima, P. Ahmet, H. Iwai, “Ultra-Shallow Junction Formation By Plasma
Doping And Flash Lamp Annealing”, RTP-2006, October 11, 2006, Kyoto, Japan
[290] A.N.Chandorkar,Ch.Ragunandan, P. Agashe, D. Sharma, H. Iwai, “Impact of Process variations on Leakage Power in CMOS Circuits in Nano Era”, ICSICT-2006, Vol.2 pp.1248-1251, October 23-26, 2006, Shanghai, China
38
[291] K.Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H.
Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, K. Toii, T. Chikyow, Y. Nara, T-J. King Liu,
H. Iwai, K. Yamada, “Physics of Interfaces between gate electrodes and high-k dielectrics”,
ICSICT-2006, pp.384-387, October 23-26, 2006, Shanghai, China
[292] P. Ahmet, K. Kakushima, K. Tsutsui, N. Sugii, T.Hattori, H. Iwai, “La-based oxides for High-k
Gate Dielectric Application”, ICSICT-2006, pp.408-411, October 23-26, Shanghai, China
[293] K. Nagahiro, K. Tsutsui, T. Shiozawa, R. Xiang, P. Ahmet, K. Kakushima,Y. Okuno, M.
Matsumoto, M. Kubota, H. Iwai, “Thermal Stability of NiSi Controlled by Post Silicidation
Metal Doping Method”, ICSICT-2006, pp.466-469, October 23-26, 2006, Shanghai, China
[294] H.Sauddin, Y.Sasaki, H. Ito, B. Mizuno, P. Ahmet, K. Kakushima, N. Sugii, K. Tsutsui, H.
Iwai, “Leakage Current Characteristics of Ultra-Shallow Junctions Formed by B2H6 Plasma
Doping”, ECS 210th Meeting, ECS Transactions, Vol.3 No.2, pp.57-65, October
29-November 3, 2006, Cancun, Mexico
[295] H. Nohira, T. Matsuda, K.Tachi, Y.Shiino, J.Song, Y.Kuroki, Ng Jin Aun, P.Ahmet,
K.Kakushima, K.Tsutsui, E.Ikenaga, K.Kobayashi, H.Iwai, T.Hattori, “ Effect of Deposition
Temperature on Chemical Structure of Lanthanum Oxide/Si Interface Structure”, ECS 210th
Meeting, ECS Transactions,Vol.3 No.2, pp.169-173, October 29-November 3, 2006, Cancun,
Mexico
[296] T. Nakayama, K. Shiraishi, S. Miyazaki, Y. Akasaka, T. Nakaoka, K. Torii, A. Ohta, P.
Ahmet, K. Ohmori, N.Umezawa, H.Watanabe, T.Chikyow, Y.Nara, H.Iwai, K.Yamada,
“Physics of Metal/High-k Interfaces”, ECS 210th Meeting, ECS Transactions, Vol.3 No.3, pp.129-140, October 29- November 3, 2006, Cancun, Mexico
[297] K.Ohmori, P.Ahmet, K.Shiraishi, K.Yamabe, H.Watanabe, Y.Akasaka, N.Umezawa,
K.Nakajima, M.Yoshitake, T.Nakayama, K.-S. Chang, K.Kakushima, Y.Nara, M.L.Green.
H.Iwai, K.Yamada, T.chikyow, “Wide Controllability of Flatband Voltage in La2O3 Gate
Stack Structures - Remarkable Advantages of La2O3 over HfO2-”, ECS 210th Meeting, ECS
Transactions, Vol.3 No.3, pp.351-363, October 29-November 3, 2006, Cancun, Mexico
[298] K.Tachi, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai, “Effect of Oxygen for
Ultra-Thin La2O3 Film Deposition”, ECS 210th Meeting, ECS Transactions, Vol.3 No.3, pp.425-434, October 29- November 3, 2006, Cancun, Mexico
[299] Y.Shiino, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai, “La
2
O
3
Gate
Dielectric Thin Film with Sc2O3 Buffer Layer for High Temperature Annealing”, ECS 210th
Meeting, ECS Transactions , Vol.3 No.3, pp.511-519, October 29-November 3 2006, Cancun,
Mexico
[300] Y. Kuroki, Jin-Aun Ng, K. Kakushima, N. Sugii, K. Tsutsui, H. Iwai, “Al/ La
2
O
3
Analysis of
Post Metallization Annealed MISFETs by XPS”, ECS 210th Meeting, ECS Transactions ,
Vol.1 No.5, pp.239-247, October 29-November 3 2006, Cancun, Mexico
[301] J. Molina, K. Kakushima, P. Ahmet, S. Nobuyuki, K. Tsutsui, H. Iwai, “BREAKDOWN AND
RELIABILITY OF METAL GATE - La
2
O
3
THIN FILMS AFTER POST-DEPOSITION
ANNEALING IN N
2
”, ECS 210th Meeting, ECS Transactions , Vol.1 No.5, pp.757-765, Oct ober 29-November 3 2006, Cancun, Mexico
[302] Invited Talk:
H. Iwai , H. Wong, “Nano-CMOS Technology for Next Fifteeen Years”, The
IEEE TENCON Nanoscale CMOS Technology, p.9,November 14-17, 2006, Hong Kong
[303] Invited Plenary Talk: H. Iwai, “Nano CMOS Manufacturing”, The Conference on
Optoelectronic and Microelectronic Materials and Devices, December 6-8, 2006, Perth,
Western Australia
[304] Invited Plenary Talk : H. Iwai, “ Nano CMOS Manufacturing”, The International Conference on Computers and Devices for Communication (CODEC)2006, p.5, December, 18-20 2006,
Kolkata, India
[305] Keynote Speech: H. Iwai, “Nano CMOS Technology and Manufacturing”, The 4th
International Conference on Electrical & Computer Engineering, p.20, December 19-21, 2006,
Dhaka, Bangladesh
[306] Invited Talk, Distinguished Lecture:
H. Iwai, “Electron Devices for Human Society”,
Inaugural Ceremony of IEEE Electron Devices Society Bangladesh Chapter, December 19,
2006, Dhaka, Bangladesh
[307] Invited Talk, Distinguished Lecture:
H. Iwai, “Miniaturization of Semiconductor Devices for
Integrated Circuits”, IEEE EDS Mini-Colloquium on Microelectronics & VLSI, pp.5-8,
January 3, 2007, Bhubaneswar, India
[308] Invited Talk,Invited Talk :
H. Iwai, “Future of Silicon Integrated Circuit Technology”, The
2007 Nano and Giga Challenges Conference, p.97, March 14 2007, Phoesnix, USA
39
[309] T. Shiozawa, K. Nagahiro, K. Tsutsui, P. Ahmet, K. Kakushima, and H. Iwai, “Improvement of Thermal Stability of Ni Silicide by Al Interlayer Deposition”, The ECS ISTC 2007, March
20, 2007, pp.43-47, Shnghai, China
[310] Y. Kobayashi, K.Tsutsui, K.Kakushima, V. Hariharan, V. R. Rao, P.Ahmet, H.Iwai, “Parasitic
Effects Depending on Shape of Spacer Region on FinFETs”, ECS 211th Meeting, ECS
Transactions,Vol.6 No.4 pp.83-87, May 8, 2007, Chicago, USA
[311] Invited Talk, Distinguished Lecture: H. Iwai, “Future of Nano CMOS Technology”,
WIMNACT/MQ 1 & IEDST, June 4, 2007, Tsinghua University, Beijing, China
[312] J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Improvement of interfacial properties with interfacial layer in La
2
O
3
/Ge Structure”, INFOS2007,
Microelectronic Engineering, pp.2336-2339,June20-23 2007, Glyfada, Athens, Greece
[313] S. Sato, K. Tachi , K. Kakushima , P. Ahmet , K. Tsutsui , N. Sugii , T. Hattori, H. Iwai,
“Thermal-Stability Improvement of LaON Thin Film Formed Using Nitrogen Radicals”,
INFOS2007, Microelectronic Engineering, pp.1894-1897, June20-23 2007, Glyfada, Athens,
Greece
[314] T. Kawanago, K. Tachi , J. Song , K. Kakushima, P. Ahmet, K. Tsutsui , N. Sugii , T. Hattori
H. Iwai, “Electrical Characterization of Directly Deposited La-Sc Oxides Complex for Gate
Insulator Application", INFOS2007, Microelectronic Engineering, pp.2235-2238, June20-23
2007, Glyfada, Athens, Greece
[315] Invited Talk : H. Iwai, “Future of Silicon Integrated Circuit Technology”, Second International
Conference on Industrial and Information systems, August 8-11, 2007, University of
Paradeniya, Sri Lanka
[316] H. Iwai, “Past and Future of Silicon Integrated Circuit Technology”, School of Physics,
September 7, 2007, Xinjiang University, Xinjiang, China
[317] K. Okamoto, M. Adachi, K. Kakushima, P. Ahmet, N. Sugii, K. Tsutsui, T. Hattori, H. Iwai,
“Effective Control of Flat-band Voltage in HfO
2
Gate Dielectric with La
2
O
3
Incorporation” ,
ESSDERC 2007, September 11-13, 2007, Munich, Germany
[318] Y.C.Ong,D.S.Ang,S.J.O’Shea,K.L.Pey,T.Kawanago,K.Kakushima,H.Iwai,“Characterization of the Sc
2
O
3
/ La
2
O
3
High-k Gate Stack by STM”, SSDM TSUKUBA2007, September 19-21,
2007, Tsukuba, Japan
[319] Keynote Speech: H. Iwai, “Gate stack technology for next 25 years”, 4th International
Symposium on Advanced Gate Stack Technology, September 26, 2007, Dallas, Texas, USA
[320] K.Tsutsui, K.Nagahiro, T.Shiozawa, P.Ahmet, K.Kakushima, H. Iwai, “Improvement of
Thermal Stability of Ni Silcide by Additive Metals with Specific Introduction Processes”, ECS
212th Meeting, ECS Transactions, Vol.11, No.6, pp.207-213, October 7-12, 2007, Washington,
USA
[321] K.Tachi, K.Kakushima, P.Ahmet, K.Tsutsui, N. Sugii, T. Hattori, H.Iwai, “Improvement of
Interface of W/La
2
O
3/
Si MOS Structure Using Al Capping Layer”, ECS 212th Meeting, ECS
Transactions, Vol.11, No.4, pp.191-198, October 7-12, 2007, Washington, USA.
[322] M.Adachi, K.Okamoto, K.Kakushima, P.Ahmet, K.Tsutsui, N. Sugii, T. Hattori, H.Iwai,
“Control of Flat Band Voltage by Partial Incorporation of La
2
O
3 or Sc
2
O
3
into MfO
2 in
Metal/MfO
2/
SiO
2/
Si MOS Capacitors”, ECS 212th Meeting, ECS Transactions, Vol.11 No.4, pp.157-167, October 7-12, 2007, Washington, USA
[323] Invited Talk, Distinguished Lecture: H.Iwai,
“Future Gate Stack Technology”,
Mini-Colloquium at IBM East Fishkill, December 7, 2007, New York, USA
[324] Golden Jubilee Distinguished Lecture:
H.Iwai, “Past and Future Half-Centuries for
Semiconductor Device Development”, Indian Institute of Technology
, Bombay, January 11 ,
2008, Bombay, India
[325]
H.Iwai, “Advanced Logic Technologies with New Materials and Strucures”, Inadian Institute of Science, January 18 , 2008, Bangalore, India
[326]
H.Iwai, “Past and future for micro-and nano-electronics, focusing on Si integrated circuits technology
”,
Workshop and IEEE EDS Mini-colloqiia on Nanometer COMOS Technology
(WIMNACT) , March 6-7, 2008, Sikkim, India
[327] K. Tsutsui, T. Shiozawa, K. Nagahiro, Y. Ohishi, K. Kakushima, P. Ahmet, N. Urushihara, M.
Suzuki, H. Iwai, “Improvement of Thermal Stability of Ni Silicide on N+-Si by Direct
Deposition of Group III Element (Al, B) Thin Film at Ni/Si Interface”, MAM2008, pp.63-64,
March 2-5, Dresden, Germany
[328] Y. Ohishi , K. Noguchi , K. Kakushima , P. Ahmet, K. Tsutsui , N. Sugii , T. Hattori , H. Iwai,
“Schottky Barrier Height Modulation of Ni Silicide/Si Contacts by Insertion of Thin Er or Pt
Layers
”,
The ECS ISTC 2008, pp.459-462, March 16, 2008, Shnghai, China
40
[329] Y. Morozumi, K. Kakushima, P. Ahmet, K. Tsutsui,N. Sugii, T. Hattori, K. Natori , H.Iwai,
“Properties of Ballistic current in MOSFETs studied by RT model ”, The ECS ISTC 2008, pp.129-132, March 16,2008, Shnghai, China
[330] Keynote Speech: H.Iwai, “CMOS Technology after Reaching the Scale Limit”, IWJT-2008, pp.1-2, May 15-16, 2008, Shanghai, China
[331] K. Tsutsui, M. Watanabe, Y. Nakagawa, K. Sasaki, T. Kai, Cheng-Guo Jin, Y. Sasaki, K.
Kakushima, P. Ahmet, B. Mizuno, T. Hattori, H.Iwai, “Profiling of Carrier Properties for
Shallow Junctions Using a New Sub-nanometer Step-by-step Etching Technique”, IWJT-2008, pp.58-61, May 15-16, 2008, Shanghai, China
[332] K. Kakushima, K. Okamoto, K. Tachi, S. Sato, T. Kawanago, J. Song, P. Ahmet, N. Sugii, K.
Tsutsui , T. Hattori , H. Iwai, “Impact of Thin La
2
O
3
Insertion for MfO
2
MOSFET”, ECS 213th
Meeting, ECS Transactions, Vol.13, No.2, pp.29-37, May 19, 2008, Phoenix, USA
[333] K. Tsutsui , T. Shinozawa, K. Nagahiro, Y. Ohishi, K. Kakushima, P. Ahmet, N. Urushihara, N.
Suzuki , H. Iwai, “Effects of B Al Interface Layers on Thermal Stability of Ni Silicide on Si”,
ECS 213th Meeting, Vol.13, No.1, pp.413-419, May 21, 2008, Phoenix, USA
[334] N. Umezawa, K, Shiraishi, K. Kakushima, H. Iwai, K. Ohmori, K. Yamada, T. Chikyow,
“Relation between solubility of silicon in high-k oxides and the effect of Fermi level pinning”,
ECS 213th Meeting, ECS Transactions,Vol.13, No.2, pp.15-20, May, 2008, Phoenix, USA
[335] Invited Talk, Distinguished Lecture: H. Iwai, “Past and future for micro-and nano-electronics, focusing on Si integrated circuits technolog”, IEEE EDS Committee, AdCom &ExCom
Meeting Mini-Colloquium, June 2, 2008, National Technical University at Athenes, Greece
[336] Invited Talk, Distinguished Lecture: H.Iwai, “Past and future for micro- and nano-electronics, focusing on Si integrated circuits technology”, Mini-Colloquia, Sabanci University, Jun. 4,
2008, Istanbul , Republic of Turkey
[337] Invited Talk, Distinguished Lecture: H.Iwai, “Future of Nano-CMOS after Scaling Limit”,
Mini-Colloquia, Pontificia Universidad Javeriana, Mini-Colloquium, September 8, 2008,
Bogota , Colombia
[338] Y. Kobayashi, K. Tsutsui, K. Kakushima, P. Ahmet, V. R. Rao, H. Iwai, “Analysis of
Threshold Voltage Variations of FinFETs : Separation of Short Channel Effects and Space
Charge Effects”, Int. Conf. on Solid State Devices and Materials (SSDM2008), September,
2008, Tsukuba, Japan
[339] K. Kakushima, K. Okamoto, K. Tachi, S. Sato, J. Song, T. Kawanago, P. Ahmet, N. Sugii, K.
Tsutsui, T. Hattori, H. Iwai, “Interfacial Dipole Measurement of Dielectric/Silicon Interface by
X-ray Photoelectron Spectroscopy”, PRIME 2008: Joint International Meeting, ECS
Transactions, October 14, 2008, Honolulu, Hawaii, USA
[340] H. Nohira,Y. Takenaga,K.Kakushima, P. Ahmet, K. Tsutsui, H. Iwai, “Annealing-temperature
Dependence of Compositional Depth Profile and Chemical Structures of LaOx/ScOx/Si and
ScOx/LaOx/Si Interfacial Transition Layer”, PRIME 2008: Joint International Meeting, ECS
Transactions, ECS Transactions, Vol.16, No.5, pp.171-176, October 14, 2008, Honolulu,
Hawaii, USA
[341] K. Okamoto, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, A.N.Chandorkar,
“0.5 nm EOT MOS structure with TaSi
T. Hattori,H.Iwai, x
/W stacked gate electrode”, PRIME 2008: Joint
International Meeting, ECS Transactions, Vol.16, No.5, pp.203-212, October 14, 2008,
Honolulu, Hawaii, USA
[342] K.Noguchi , W.Hosoda , K.Matano , K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, A. N.
Chandorkar, T.Hattori , H.Iwai, “Schottky Barrier Height Modulation by Er Insertion and Its
Application to SB-MOSFETs”, PRIME 2008: Joint International Meeting, ECS Transactions,
October 14, 2008, Honolulu, Hawaii, USA
[343] Y. Lee, T. Nagata, K. Kakushima, K. Shiraishi, H. Iwai, “Electronic Structure Analysis of
Silicon Nanowires for High Conductivity in n- and p-channel Nanowire-FET”, PRIME 2008:
Joint International Meeting, ECS Transactions, October 14, 2008, Honolulu, Hawaii, USA
[344] Y. Kobayashi , A. Sachid, K. Tsutsui, K. Kakushima, P. Ahmet ,V. Rao, H. Iwai, “Analysis of
Threshold Voltage Variations of FinFETs Relating to Short Channel Effects”, PRIME 2008:
Joint International Meeting, ECS Transactions, October 14, 2008, Honolulu, Hawaii, USA
[345] M. Kouda, K. Tachi, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, A. Chandorkar , T.
Hattori, H. Iwai, “Electric Properties of CeOX /La2O3 Stack as Gate Dielectric in Advanced
MOSFET Technology”, PRIME 2008: Joint International Meeting, ECS Transactions, Vol.16
No.5, pp.153-160, October 14, 2008, Honolulu, Hawaii, USA
[346] J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Effect of
41
Ultrathin Si Passivation Layer for Ge MOS Structure with La2O3 Gate Dielectric”, PRIME
2008: Joint International Meeting, ECS Transactions, Vol.16, No.5, pp.285-293, October 14,
2008, Honolulu, Hawaii, USA
[347] M. Hino, K. Nagata, T. Yoshida, D. Kosemura, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii,
A. Ogura, T. Hattori, H. Iwai, “Study on Stress Memorization by Argon Implantation and
Annealing”, PRIME 2008: Joint International Meeting, ECS Transactions, Vol.16 No.10, pp.117-124, October 14, 2008, Honolulu, Hawaii, USA
[348] K. Kakushima, K. Tachi, M. Adachi, K. Okamoto, S. Sato, T. Kawanago, P.Ahmet, K.Tsutsui,
N. Sugii, T. Hattori, H. Iwai, “Advantage of La
2
O
3
Gate Dielectric over HfO
2 for Direct
Contact and Mobility Improvment”, ESSDERC 2008, pp. 126-129, October 15-19, 2008,
Scotland, UK
[349] K.Tsutsui, M. Watanabe, Y. Nakagawa, T. Matsuda, T.Yoshida, E. Ikenaga, K. Kakushima,
P.Ahmet, H. Nohira, T. Maruzumi, A. Ogura, T. Hattori, H. Iwai, “New Analysis of Heavily
Doped Boron and Arsenic in Shallow Junctions by X-ray Photoelectron Spectroscopy”,
ESSDERC 2008, pp. 142-145, October 15-19 ,2008, Scotland, UK
[350] P.Ahmet, T. Shiozawa, K.Nagahiro, K.Kakushima, K.Tsutsui, T. Chikyow, H.Iwai, “Ni silicidation on Heavily Doped Si Substrates”, ICSICT2008, Vol.2 pp.1304-1307, October
20-23, 2008, Beijing, China
[351] H.Iwai, “Past and future for micro-and nano-electronics, focusing on Si integrated circuits technology”, Changchun University of Science and Technology, Mini-Colloquium, October 24,
2008, Changchun, China
[352] H.Iwai, “Technology Scaling and Roadmap for 22nm CMOS logic and beyond”, Dalian
University of Technology, Mini-Colloquium,October 27, 2008, Dalian, China
[353] H.Iwai, “Future of Nano-CMOS after Scaling Limit”, Shenyang University of Technology,
Mini-Colloquium,October 28, 2008, Shenyang, China
[354] Invited Talk: H. Iwai, “Introduction of new materials into Si-integrated Circuits”, C-MRS,
November 23, 2008, South China University of Technology, Guangzhou, China
[355] H. Iwai, “Past and Future of Si integrated Circuit Technology”, Xiangtan University,
November 24, 2008, Xiangtan, China
[356] H. Iwai, “Introduction of new materials into Si integrated circuits”, Hunan University,
November 27, 2008, Changsha, China
[357] H. Iwai, “Past and future of Si integrated circuit technologies”, Nanjing University, November
28, 2008, Nanjing, China
[358] H. Iwai, “Technology Scaling and Roadmap” 2008 IEDM Short Course : 22nm CMOS
Technology, Decemver 14, 2008, San Francisco, USA
[359]
H.Iwai, “Downsizing of transistors towards its Limit”, NIT Calicut, January 5, 2009, Calicut,
India
[360] Invited Talk, Distinguished Lecture: H.Iwai, “Technology Scaling and Roadmap for 22nm and beyond”, Kyungpook National University, Mini-Colloquium, March 13, 2009, Daegu,
Korea
[361] H. Fujisawa , A. Srivastava, K. Kakushima , P. Ahmet, K. Tsutsui , N. Sugii , T. Hattori
Sarkar , H.
Iwai
, “
Electrical Characterization of W/HfO
2
1 , C. K.
MOSFETs with La
2
O
3
Incorporation”,
ISTC /CSTIC2009, p.53, March 19,2009, Shanghai, China
[362] H. Kamimura , H. Arai , , K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H.
Iwai, “Evaluation of Lateral Ni Diffusion in Si Nanowire Schottky Contact”, ISTC
/CSTIC2009, p.58, March 19,2009, Shanghai, China
[363] Invited Talk, Distinguished Lecture: H. Iwai, “Technology Scaling and Roadmap for 22nm
CMOS and beyond”, University College of Dublin, EDS Mini-Colloquium on Advanced
Electron Devices modeling and Technology, May 1, 2009, Dublin, Ireland
[364] Invited Talk:
H. Iwai, “Technology Roadmap for 22nm CMOS and Beyond”, IEEE/2 nd IEEE
International Workshop On Electron Devices And Semiconductor Technology, June 1, 2009,
Indian Institute of Technology Bombay, Mumbai, India
[365]
H.Iwai, “Past and Future of Integrated Circuits Technology”, International Conference on
Frontiers of Physics(ICFP 2009), p.60, June 2-5,2009, Kathmandu, Nepal
[366] K.Tachi, T. Ernst, C. Dupre, A. Hubert, S. Becu, H. Iwai, S. Cristoloveanu, O. Faynot,
“Transport Optimization with Width Dependence of 3D-stacked GAA Silicon Nanowire FET with High-k/Metal Gate Stack”, 2009 Silicon Nanoelectronics Workshop, June 13, 2009,
Kyoto, Japan
[367]
H. Iwai, “Nono-CMOS Technology after Reaching Its Scaling Limit”, Future Trends in
Microelectronics(FTM-2009) Workshop, June 16, Sardinia, Italy
42
[368] P.Ahmet, T. Nagata, K.Kakushima, K.Tsutsui, T. Chikyow, H. Iwai, “On the thermal stability of nicket silicides”, Future Trends in Microelectronics(FTM-2009) Workshop, June 16,
Sardinia, Italy
[369] M.Kouda, N.Umezawa, K.Kakushima, P.Ahmet, K.Shiraishi, T.Chikyow, K.Yamada, H.Iwai,
“Charged defects reduction in gate insulator with multivalent materials”, 2009 Symposium on
VLSI Technology Digest of Technical Papers, pp.200-201, June 17, 2009, Kyoto, Japan
[370] Plenary Invited Talk: H.Iwai, “Roadmap for 22nm and beyond”, INFOS2009, June 29, 2009,
Clare College, Cambridge, UK
[371] J. Song, K. Kakushima, P.Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Post metallization annealing study in La
2
O
3
/Ge MOS structure”, INFOS2009, Microelectronic Engineering, Vol.
86, pp.1638-1641, June 28-July 1, 2009, Cambridege University, UK
[372] T. Kawanago, J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H.
Iwai ,“Experimental Study for High Efffective Mobility with directly deposited HfO
2
/La
2
O
3
MOSFET”, INFOS2009, Microelectronic Engineering, Vol. 86, pp.1629-1631, June 28-July 1,
2009, Cambridege University, UK
[373] H.Iwai, “Si Nanowire experiment”, G-COE Workshop on Nanoelectronics, July 3, 2009,
University of Cambridege, UK
[374] K.Kakushima, H.Iwai, “High-k Experiment below 0.5-nm EOT”, G-COE Workshop on
Nanoelectronics, July 3, 2009, Cambridege University, UK
[375] Keynote Speech: H.Iwai, “Logic LSI Technology Roadmap for 22nm and Beyond”, IPFA2009,
July 8, Suzhou, China
[376] H.Iwai, “Future nanoelectronic device technologies - high-k, nanowire and alternative channel-”, NSC-JST Nano Device Workshop, July 23, 2009, National Nano Device
Laboratories, Hsinchu, Taiwan
[377] S. Sato, H. Kamimura, H. Arai, K. Kakushima, P. Ahmet, K. Ohmori, K. Yamada, H. Iwai,
“High-Performance Si Nanowire FET with a Semi Gate-Around Structure Suitable for
Integration”, ESSDERC 2009, 39 th European Solid-State Device Research Conference, pp.249-252, September 14-18, 2009, Athens, Greece
[378] K. Kakushima, K. Okamoto, T. Koyanagi, K. Tachi, M. Kouda, T. Kawanago, J. Song, P.
Ahmet, K. Tsutsui, N. Sugii, T. Hattori, H. Iwai, “Selection of Rare Earth Silicate with SrO
Capping for EOT Scaling below 0.5 nm”, ESSDERC 2009, 39 th European Solid-State Device
Research Conference, pp.403-406, September 14-18, 2009, Athens, Greece
[379] H.Iwai, “Roadmap for Nano-CMOS”, ECS 216th Meeting, ECS Transactions, Vol.25, No.7, pp.67-76, October 7, 2009, Vienna, Austria
[380] K.Kakushima, P.Ahmet, H. Iwai, “Overwhelming the 0.5 nm EOT Level for CMOS Gate
Dielectric”, ECS 216th Meeting, ECS Transactions, Vol.25, No.7, pp.171-75, October 4-9,
2009, Vienna, Austria
[381] M.Mamatrishat, M.Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Analysis of Remote Coulomb Scattering Limited Mobility in MOSFETs with CeO
2
/La
2
O
3
Gate Stacks”, ECS 216th Meeting, ECS Transactions,Vol.25, No.7, pp.253-257, October4-9, 2009, Vienna, Austria
[382] H.Arai, H.Kamimura, S.Sato, K.Kakushima, P. Ahmet, K.Tsutsui, N.Sugii, K.Natori, T.Hattori,
H.Iwai, “Annealing Reaction for Ni Silicidation of Si Nanowire”, ECS 216th Meeting, ECS
Transactions, Vol.25, No.7, pp.447-454, October 4-9, 2009, Vienna, Austria
[383] T.Koyanagi, K.Okamoto, K.Kakushima, P.Ahmet, K.Tsutsui, A. Nishiyama, N.Sugii, K.Natori,
T.Hattori, H.Iwai, “Impact of Alkali Earth Elements Incorporation on Electrical Characteristics of La
2
O
3
Gated MOS Device”, ECS 216th Meeting, ECS Transactions, Vol.25, No.6, pp.17-22,
October 4-9, 2009, Vienna, Austria
[384] M.K.Bera, J.Song, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai, “Electrical
Properties of Lanthanum-scandate Gate Dielectric Directly Deposited on Ge”, ECS 216th
Meeting, ECS Transactions,Vol.25, No.6, pp.67-77, October 4-9, 2009, Vienna, Austria
[385] K.Funamizu, Y.C.Lin, K.Kakushima, P.Ahmet, K.Tsutsui, N.Sugii, E.Y.Chang, T.Hattori,
H.Iwai, “Electrical Characteristics of HfO
2 and La
2
O
3
Gate Dielectrics for In
0.53
Ga
0.47
A s
MOS
Structure”, ECS 216th Meeting, ECS Transactions, Vol.25, No.6, pp.265-270, October 4-9,
2009, Vienna, Austria
[386] H.Nohira, Y.Kon, K.Kitamura, M.Kouda, K.Kakushima, H.Iwai, “Annealing-temperature
Dependence of Compositional Depth Profiles and Chemical Bonding States of CeO x
/ LaO x
/Si and LaO x
/CeO x
/Si Structure”, ECS 216th Meeting, ECS Transactions,Vol.25, No.6, pp.321-326, October 4-9, 2009, Vienna, Austria
[387] H.Nakayama, K.Kakushima, P.Ahmet, E.Ikenaga, K.Tsutsui, N.Sugii, T.Hattori, H.Iwai,
43
“Crystallographic Orientation Dependent Electrical Characteristics of La
2
O
3
MOS Capacitors”,
ECS 216th Meeting, Vol.25, No.6, pp.339-345, October 4-9, 2009, Vienna, Austria
[388] Y. Lee, K. Kakushima, K. Shiraishi, K. Natori, H. Iwai, “Systematic Study on Size
Dependences of Transport Parameters for Ballistic Nanowire-FET with Effective Mass
Approximation”, 2009 International Conference on Solid Sate Devices and Materials, E-7-5,
October 2009, Sendai Kokusai hotel, Miyagi, Japan
[389] H. Iwai, “Miniaturization and future prospects of Si devices”, G-COE PICE International
Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology,
Japan
[390] M. K. Bera, J. Song, P. Ahmet, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, T. Hattori,
H. Iwai, “Rare-earth based mixed oxide as high-k gate dielectrics for Ge MOSFET”, G-COE
PICE International Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology, Japan
[391] J. Song, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hattori and H. Iwai, “Effect of
Ultrathin Si Passivation Layer for La
2
O
3
/Ge MOS structure”, G-COE PICE International
Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology,
Japan
[392] T. Kawanago, K. Kakushima, P.Ahmet, K.Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Experimental Investigation of V
FB
shift and Effective Mobility in La
2
O
3
MOS Devices”, G-COE PICE International Symposium on Silicon Nano Devices, October
13-14, 2009, Tokyo Institute of Technology, Japan
[393] S. Sato, H. Arai, K. Kakushima, P. Ahmet, H. Iwai, “Evaluation of Channel Potential Profile of Si Nanowire Field Effect Transistor”, G-COE PICE International Symposium on Silicon
Nano Devices, October 13-14, 2009, Tokyo Institute of Technology, Japan
[394] M. Mamatrishat, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Study on Remote Coulomb Scattering Limited Mobility in MOSFETs with
CeO
2
/ La
2
O
3
Gate Stacks”, G-COE PICE International Symposium on Silicon Nano Devices,
October 13-14, 2009, Tokyo Institute of Technology, Japan
[395] A. Abudukelimu, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Current-Voltage Characteristics of Ballistic Nanowire MOSFET by
Numerical Analysis”, G-COE PICE International Symposium on Silicon Nano Devices,
October 13-14, 2009, Tokyo Institute of Technology, Japan
[396] M. Kouda, N. Umezawa, K. Kakushima, H. Nohira, P. Ahmet, K. Shiraishi, T. Chikyow, K.
Yamada, H. Iwai, “Charged defects reduction in gate insulator with multivalent materials”,
G-COE PICE International Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo
Institute of Technology, Japan
[397] Y. Lee, K. Kakushima, K. Shiraishi, K. Natori, H. Iwai, “Size-Dependent Transport
Characteristics of Ballistic Silicon Nanowire FETs”, G-COE PICE International Symposium on
Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology, Japan
[398] H. Nakayama, K. Kakushima, P. Ahmet, E. Ikenaga,K. Tsutsui, N. Sugii, T. Hattori, H. Iwai,
“Crystallographic Orientation Dependent
Electrical Characteristics of La
2
O
3
MOS Capacitors”,
G-COE PICE International Symposium on Silicon Nano Devices, October 13-14, 2009,
Tokyo Institute of Technology, Japan
[399] H. Arai, H. Kamimura, S. Sato, K. Kakushima, P. Ahmet, A. Nishiyama,K. Tsutsui, N. Sugii,
K. Natori, T. Hattori H. Iwai, “Annealing Reaction for Ni Silicidation of Si Nanowire”,
G-COE PICE International Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo
Institute of Technology, Japan
[400] K. Funamizu, T. Kanda, Y.C. Lin, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, E.Y. Chang, K. Natori, T. Hattori, H. Iwai, “Electrical Characteristics of HfO
2
and
La
2
O
3
Gate Dielectrics for In
0.53
Ga
0.47
As MOS Structure”, G-COE PICE International
Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology,
[401]
Japan
W.Hosoda, K.Ozawa, K.Kakushima, P.Ahmet, K.Tsutsui, A.Nishiyama, N.Sugii, K.Natori,
T.Hattori, H.Iwai, “A Study of Schottky Barrier Height Modulation of NiSi by Interlayer
Insertion and Its Application to SOI SB-MOSFETs”, G-COE PICE International Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology, Japan
[402] K. Matano, K. Kakushima, P. Ahmet, N. Sugii, K. Tsutsui, T. Hattori, H. Iwai, “Threshold
Voltage Control in p-MOSFET with High-k Gate dielectric”, G-COE PICE International
Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of Technology,
Japan
44
[403] T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui,A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Influence of Alkali Earth Elements Capping on Electrical Characteristics of
La
2
O
3
Gated MOS Device”, G-COE PICE International Symposium on Silicon Nano Devices,
October 13-14, 2009, Tokyo Institute of Technology, Japan
[404] Y. Kobayashi, K. Kakushima, P. Ahmet, V. Ramgopal Rao, K. Tsutsui, H. Iwai,
“Short-channel effects on FinFETs induced by inappropriate fin widths”, G-COE PICE
International Symposium on Silicon Nano Devices, October 13-14, 2009, Tokyo Institute of
Technology, Japan
[405] Keynote Speech: H. Iwai, “Past and future of Micro/Nano-electronics”, IEEE EDS & SKP
Workshop 2009, Novemver 4, 2009, SKP Engineering College,Tiruvannamalai, India
[406] Invited Talk, Distinguished Lecture: H. Iwai, “Past and future of Micro/Nano-electronics”,
IEEE EDS Mini Colloquia, November 9, 2009, Government Engineering College, Port Blair,
India
[407] K. Tachi, M. Casse, D. Jang, C. Dupre, A. Hubert, N. Vulliet, C. Maffini-Alvaro, C. Vizioz, C.
Carabasse, V. Delaye, J.M.Hartmann, G. Ghibaudo, H. Iwai, S. Cristoloveanu, O. Faynot,
Ernst, “Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires”, IEDM 2009, December 8, 2009, Baltimore, USA
[408] Plenary Invited Talk: H. Iwai, “Si MOSFET Roadmap for 22nm and beyond”, CODEC 2009,
December 14, 2009, Hyatt Regency, Kolkata, India
[409] H. Iwai, “Past and Future of Silicon Electronic Devices”, December 15, 2009, National
Symposium on “Science and Technology and the Young (Career, Creativity and Excitement)”
Organized by National Academy of Science, Calcutta University, Kolkata, India
[410] Invited Talk, Distinguished Lecture: H Iwai, “Future nanoelectronic device technologies - high-k, nanowire and alternative channel”, IEEE AP & ED Joint MQ, January 13, 2010,
IIT Bombay, Bombay, India
[411] K.Matano, K. Funamizu, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Electrical Characteristics of Rare Earth (La, Ce, Pr and
Tm) Oxides/Silicates Gate Dielectric”, China Semiconductor Technology International
Conference,Vol.27, No.1, pp.1129-1134, March 18-19, 2010, Shanghai, China
[412] W. Hosoda, K. Ozawa, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Fabrication of SB-MOSFETs on SOI Substrate Using Ni Silicide
Containing Er Interlayer” China Semiconductor Technology International Conference, Vol.27,
No.1, pp.1105-1110, March 18-19, 2010, Shanghai, China
[413] A. Abudukelimu, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Performance of Silicon Ballistic Nanowire MOSFET with Diverse
Orientations and Diameters”, China Semiconductor Technology International Conference,
Vol.27, No.1, pp.1111-1116, March 18-19, 2010, Shanghai, China
[414] H Iwai, “Si Nanoelectronic Device Technology”, March 10, 2010, University of Science and
Technology of China, Hefei, China
[415] H Iwai, “Past and Future of Integrated Circuits Technology”, March 15, 2010, Jiangxi
University of Finance and Economics, Nanchang, China
[416] H Iwai, “Past and Future of Integrated Circuits Technolog”, March 16, 2010, East China
Jiaotong University, Nanchang, China
[417] Invited Talk, Distinguished Lecture: H. Iwai, “Si Nanoelectronic Device Technolohy” , IEEE
EDS DL, Beyond the definition of classical devices & communication technology, Siliguri
Institute of Technology, March 29, 2010, Siliguri Institute of Technology, Siliguri, India
[418] Invited Talk, Distinguished Lecture: H. Iwai, “Si Nanoelectronic Device Technology", IEEE
EDS WIMNACT 23, April 2, 2010, IIT Guwahati, Guwahati, India
[419] Invited Talk, Distinguished Lecture: H. Iwai, “Si Nanoelectronic Device Technology", IEEE
EDS WIMNACT 23, April 5, 2010, North-Eastern Hill University, Shillong, India
[420] Invited Talk, Distinguished Lecture: H. Iwai, “Si Nanoelectronic Device Technology", IEEE
EDS WIMNACT 23, April 8, 2010, NIT Silchar, Silchar, India
[421] Invited Talk, Distinguished Lecture: H. Iwai, “Nanoelectronic Device Technology", IEEE
EDS WIMNACT 23, April 9, 2010, Heritage Institute of Technology, Kolkata, India
[422] P. Ahmet, K. Kakushima, H Iwai, “Towards the Ultimate Scaling of MOSFET Gate
Dielectrics - Direct Contact of High-k and Silicon-", ECS 217 th Meeting, Vol.28, No.2, pp.69-73, April 26, 2010, Vancouver, Canada
[423] P. Ahmet, W. Hosoda, K. Noguchi, Y. Ohishi, K. Kakushima, K. Tsutsui, H. Iwai, “Er Inserted
Ni Silicide Metal Source/Drain for Schottky MOSFETs”, IEEE IWJT 2010 Extended
45
Abstracts 2010 International Workshop on Junction Technology, pp.62-64, May 11, 2010,
Shanghai, China
[424] A. Uedono, K. Tsutsui, S. Ishibashi, H. Watanabe, S. Kubota, K. Tenjinbayashi, Y. Nakagawa,
B. Mizuno, T. Hattori, H. Iwai, “Vacancy-Type Defects in Ultra-Shallow Junctions Fabricated
Using Plasma Doping Studied by Positron Annihilation”, IEEE IWJT 2010 Extended
Abstracts 2010 International Workshop on Junction Technology, pp.149-154, May 11, 2010,
Shanghai, China
[425] K. Tsutsui, N. Hoshino, Y. Nakagawa, M. Tanaka, H. Nohira, K. Kakushima, P. Ahmet, Y.
Sasaki, B. Mizuno, T. Hattori, H. Iwai, “Depth Profiling of Chemical Bonding States of
Impurity Atoms and Their Correlation with Electrical Activity in Si Shallow Junctions”, IEEE
IWJT 2010 Extended Abstracts 2010 International Workshop on Junction Technology, pp.174-177, May 11, 2010, Shanghai, China
[426] K. Tsutsui, Y. Kobayashi, K. Kakushima, P. Ahmet, V. R. Rao, H. Iwai, “Analysis of
Threshold Voltage Variation in Double-gate MOSFETs(FinFETs), International Symposium on technology Evolution for Silicon Nano-Electronics(ISTESNE), p.53, June 4, 2010, Tokyo
Institute of Technology, Tokyo, Japan
[427] Invited Talk, Distinguished Lecture: H. Iwai, “Past and future of Si integrated circuit device technologies” , IEEE EDS Mini Colloquium, June 7, 2010, Institute for Microelectronics
Stuttgart(IMS-CHIPS), Stuttgart, Germany
[428] K. Kakushima, T. Koyanagi, D. Kitayama, M. Kouda, J. Song, T. Kawanago, M. Mamatrishat,
K. Tachi, M. K. Bera,P. Ahmet, H. Nohira, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, K. Yamada, H. Iwai, “Direct Contact of High-k/Si Gate Stack for EOT below 0.7 nm using LaCe-silicate Layer with V fb controllability”, 2010 Symposium on VLSI Technology, pp.69-70, June 15, 2010, Honolulu, Hawaii, USA
[429] Keynote Speech: H. Iwai, “Future perspective for the mainstream CMOS technology and their contribution to green technologies”, 2010 Asia-Pacific Workshop on Fundamentals and
Applications of Advanced Semiconductor Devices, July 1, 2010, Tokyo Institute of
Technology, Japan
[430] H. Iwai, “Nanoelectronic Device Technology - Future perspective for the mainstream CMOS technology-”, July 15, 2010, Xinjiang University, Xinjiang, China
[431] Invited Talk:
H. Iwai,“Si Nanowire Device and its Modeling”, International Conference on
Simulation of Semiconductor Processes and Devices(SISPAD), September 6, 2010, , Bologna,
Italy
[432] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Optimized Oxygen Annealing Process for V th Tuning of p-MOSFET with
High-k/Metal Gate Stacks”, ESSDERC 2010, 40 th European Solid-State Device Research
Conference, September 15, 2010, Seville, Spain
[433] S. Sato,Y. Lee, K. Kakushima, P. Ahmet, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Gate
Semi-Around Si Nanowire FET Fabricated by Conventional CMOS Process with Very High
Drivability”, ESSDERC 2010, 40 th European Solid-State Device Research Conference,
September 16, 2010, Seville, Spain
[434] K. Tachi, N. Vulliet, S. Barraud, B. Guillaumot, V. Maffini-Alvaro, C. Vizioz, C. Arvet, Y.
Campidelli, P. Gautier, J.M. Hartmann, T. Skotnicki, S. Cristoloveanu, H. Iwai, O. Faynot, T.
Ernst, “3D Source/Drain Doping Optimization in Multi-Channel MOSFET, ESSDERC 2010,
40 th European Solid-State Device Research Conference, September 16, 2010, Seville, Spain
[435] H. Iwai, “Future Silicon Nanoelectronic Technology”, Shandong University, September 21,
2010, Jinan, China
[436] Invited Talk: H. Iwai, “High-k Gate Stack Technology Beyond 0.5 nm EOT”, 11 th IUMRS
International Conference in Asia, September 28, 2010, Qingdao, China
[437] T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Impact of Alkali-Earth-Elements Incorporation on V fb
R0ll-Off
Characteristics of La
2
O
3
Gated MOS Device”, ECS 218th Meeting, ECS Transactions,Vol.33,
No.3, pp.67-74, October 11, 2010, Las Vegas, USA
[438] M. Bera, P. Ahmet, K. Kakushima, K. Tsutsui, N. Sugii, A. Nishiyama, T. Hattori, H. Iwai,
“Electrical Properties of Yttrium-Titanium Oxide High-k Gate Dielectric on Ge”, ECS 218th
Meeting, ECS Transactions ,October 11, 2010, Las Vegas, USA
[439] M. Mamatrishat, M. Kouda, T. Kawanago, K. Kakushima, P. Ahmet, A. Aierken, K. Tsutsui,
46
A. Nishiyama, N. Sugii, K. Natori, H. Iwai, “Effect of Remote-Surface –Roughness Scattering on Electron Mobility in MOSFETs with High-k Dielectrics”, ECS 218th Meeting, ECS
Transactions, Vol.33, No.3, pp.249-255, October 11, 2010, Las Vegas, USA
[440] N. Shigemori, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Suppression of Lateral Encroachment of Ni Silicide into Si Nanowires using Nitrogen Incorporation”, ECS 218th Meeting, ECS Transactions, October 11, 2010, Las
Vegas, USA
[441] D. Kitayama, T. Koyamagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “TiN Capping Effect on High Temperature Annealed RE-Oxide
MOS Capacitors for Scaled EOT”, ECS 218th Meeting, ECS Transactions, Vo.33, No.3, pp.527-535, October 11, 2010, Las Vegas, USA
[442] Y. Wu, N. Shigemori, S. Sato, K. Kakushima, P. Ahmet, K. Tsuitsui, N. Sugii, A. Nishiyama,
K. Natori, T. Hattori, H. Iwai, “Observation of Tunneling FET operation in MOSFET with
NiSi/Si Schottky source/channel interface”, ECS 218th Meeting, ECS Transactions, October
11, 2010, Las Vegas, USA
[443] Chia-Hua Chang, Tin-En Shie, Yueh-Chin Lin, K. Kakushima, H. Iwai, Po-Ching Lu,
Ting-Chun Lin, Guan Ning Juang, Edward Yi Chang, “Effect of Thermal Treatments on
HfO
2
/In
0.7
Ga
0.3
As Metal-Oxide-Semiconductor Capacitor Characteristics”, ECS 218th Meeting,
ECS Transactions, Vol.33, No.3, pp.473-478, October 11, 2010, Las Vegas, USA
[444]
H. Iwai, “Past and Future of Micro/Nano CMOS Devices”, ICSICT(International Conference on Solid-State and Integrated Circuit Technology)2010 EDS-Mini Colloquia & Tutorials,
November 1, 2010, Shanghai China
[445] K. Tsutsui, M. Tanaka, N. Hoshino, H. Nohira, K. Kakushima, P. Ahmet, Y. Sasaki, B.
Mizuno, T. Muro, T. Kinoshita, T. Hattori, H. Iwai, “Soft X-ray Photoelectron Spectroscopy
Study of Activation and Deactivation of Impurities in Shallow Junctions”,
ICSICT(International Conference on Solid-State and Integrated Circuit Technology)2010,
November 3, 2010, Shanghai, China
[446] A. Abudukelimu, K. Kakushima, P. Ahmet, M. Geni, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “The Effect of Isotropic and Anisotropic Scattering in Drain
Region of Ballistic Channel Diode”, ICSICT(International Conference on Solid-State and
Integrated Circuit Technology)2010, November 3, 2010, Shanghai, China
[447] P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T.
Kawanago, K. Kakushima, H. Iwai, “Scaling of EOT Beyond 0.5nm”, ICSICT(International
Conference on Solid-State and Integrated Circuit Technology)2010, November 4, 2010,
Shanghai, China
[448] K. Ozawa, M. Kouda, Y. Urabe, T. Yasuda, K. Kakushima, P. Ahmet, H. Iwai, “La
2
O
3 insulators prepared by ALD using La(iPrCp)3 source: self-limiting growth conditions and electrical properties”, ICSICT(International Conference on Solid-State and Integrated Circuit
Technology)2010, November 4, 2010, Shanghai, China
[449] H. Iwai, “Si Nanowire FET Modeling and Technology”, Institute of Microelectronics Chinese
Academy of Sciencee, November 8, 2010, Beijing, China
[450] K. Tachi, M. Casse, S. Barraud, C. Dupre, A. Hubert, N. Vulliet, M.E. Faivre, C. Vizioz, C.
Carabasse, V. Delaye, J.M. Hartmann, H. Iwai, S. Cristoloveanu, O. Faynot, T. Ernst,
“Experimental study on carrier transport limiting phenomena in 10 nm width nanowire CMOS transistors”, 2010 IEDM, December 8, 2010, San Francisco, USA
[451] T. Nakayama, K. Kakushima, O. Nakatsuka, Y. Machida, S. Sotome, T. Matsuki, K. Ohmori,
H. Iwai, S. Zaima, T. Chikyow, K. Shiraishi, K. Yamada, “Theory of Workfunction Control of
Silicides by Doping for Future Si-Nano-Devices based on Fundamental Physics of Why
Silicides Exist in Nature”, 2010 IEDM, December 8, 2010, San Francisco, USA
[452] H. Iwai, “Past and Future of Micro/Nano-Electronics”, IEEE EDS MINI-COLLOQUIUM on
“Nanoelectronics”, Gandhi Institute of Technology and Management, December 28, 2010,
Bhubaneshwar, Orissa, India
[453]
H. Iwai, “Si Nanowire FET Modeling and Technology”, IEEE EDS MINI-COLLOQUIUM on
“Nanoelectronics”, National Institute of Science and Technology, December 30, 2010,
Berhampur, Orissa, India
[454]
H. Iwai, “Past and Future of Micro/Nano-Electronics”, Muthayammal Engineering, January 7,
2011, Rasipuram, Tamilnadu, India
47
[455] M. Kouda, K. Kakushima, P. Ahmet , K. Tsutsui , A, Nishiyama, N. Sugii, K. Natori, T. Hattori ,
H. Iwai, “Rare earth oxide capping effect on La2O3 gate dielectrics toward EOT of 0.5nm” ,
2011 International Workshop on Dielectric Thin Films for Future ULSI Devices: Science and
Technology(IWDTF-11) , January 20, 2011, Tokyo, Japan
[456] M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A, Nishiyama , N. Sugii, K. Natori, T.
Hattori, H. Iwai , “Preparation and electrical characterization of CeO2 films for gate dielectrics application: comparative study of CVD and ALD processes”, 2011 International Workshop on
Dielectric Thin Films for Future ULSI Devices: Science and Technology(IWDTF-11) , January
20, 2011, Tokyo, Japan
[457] Y. Lee, K. Kakushima, K. Natori , H. Iwai , “Cross-sectional distribution of phonon-limited electron mobility in rectangular silicon nanowire field effect transistors”, 2011 International
Workshop on Dielectric Thin Films for Future ULSI Devices: Science and
Technology(IWDTF-11) , January 20, 2011, Tokyo, Japan
[458] D. Hassanzadeh , T. Takashi , K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Effects of In
0.53
Ga
0.47
As Surface Preparation on MOS Device
Electrical Characterization”, 2011 International Workshop on Dielectric Thin Films for Future
ULSI Devices: Science and Technology(IWDTF-11) , January 20, 2011, Tokyo, Japan
[459] Introductory Talk: H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS
Mini-colloquium on Nanometer CMOS Technology (WIMNACT 26), February 9, 2011,
Tokyo, Japan
[460] E. Y. Chang, H. Iwai, “III-V MOSFETs for Next Generation-Fabrication of III-V MOS
Capacitor”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[461] H. Iwai, “High-K Gate Dielectronics for Future III-V FET”, Taiwan-Japan Workshop on
“Nano Devices”,p.52, March 3, 2011, Tokyo, Japan
[462] K. Tachi, K. Kakushima, H. Iwai, S. Cristoloveanu, T. Ernst, “Characterization of carrier transport in vertically-stacked Si nanowire FETs”, Taiwan-Japan Workshop on “Nano
Devices”,March 3, 2011, Tokyo, Japan
[463] S. Sato, K. Kakushima, P. Ahmet, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Influence of the cross-sectional shape for Si nanowire FETs”, Taiwan-Japan Workshop on “Nano
Devices”,March 3, 2011, Tokyo, Japan
[464] Y. Lee, K. Kakushima, K. Natori, H. Iwai, “Corner Effects on Phonon-Limited Mobility in
Rectangular Si Nanowire MOSFETs”, Taiwan-Japan Workshop on “Nano Devices”,March 3,
2011, Tokyo, Japan
[465] A. Abudukelimu, K. Kakushima, P. Ahmet, K. Natori, H. Iwai, “Influence of Phonon
Generation of Hot Electrons in Drain Region on Ballistic Transport”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[466] N. Shigemori, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “An effective suppression process for Ni silicide enchroachment into Si nanowire”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[467] M. Koyama, N. Shigemori, H. Arai, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Lateral encroachment of Ni silicide into silicon nanowire”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[468] K. Nakajima, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Interface State Density Measurement of Three Dimensional Silicon
Structures by Charge Pumping Method”, Taiwan-Japan Workshop on “Nano Devices”,March
3, 2011, Tokyo, Japan
[469] T. Kawanago, T. Suzuki, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “An effective process for oxygen defect suppression for La-based oxide gate dielectric”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo,
Japan
[470] T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Flatband Voltage Shift of La-based Gate Oxides with Alkali-earth-elements
Incorporation”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[471] T. Kaneda, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Effect of rare earth oxide capping for La-based gate oxides”,
Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo, Japan
[472] M. Mamatrishat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, H.
Iwai, “Remote-surface-roughness scattering-limited electron, mobility in ultrathin high-k gate stacked MOSFETs”, Taiwan-Japan Workshop on “Nano Devices”,March 3, 2011, Tokyo,
Japan
48
[473] D. Kitayama, T. Kubota, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Precise Control of Silicate Reaction with La
“Nano Devices”, March 3, 2011, Tokyo, Japan
2
O
3
Gate
Dielectrics towards Equivalent Oxide Thickness of 0.5 nm”, Taiwan-Japan Workshop on
[474] T. Kanda, D. Zade, Y. -C. Lin, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
E. Y. Chang, K. Natori, T. Hattori, H. Iwai, “Annealing Effect on the Electrical Properties of
La
2
O
3
/InGaAs MOS Capacitors”, CSTIC2011,March 13, 2011, Shanghai, China
[475] T. Kawanago, K. Kakushima, P. Ahmet, K. Tsutsui,
Hattori, H. Iwai and V
, “
A. Nishiyama, N. Sugii, K. Natori,
Metal Inserted Poly-Si Stacks with La
T.
2
O
3
Gate Dielectrics for Scaled EOT
FB
Control by Oxygen Incorporation ”, CSTIC2011, March 13, 2011, Shanghai, China
[476] S. Sato, K. Kakushima, P. Ahmet, K. Ohmori, K. Natori, K. Yamada, H. Iwai, “Structural
Effects of Channel Cross-section on a Gate Capacitance of Silicon Nanowire Field-Effect
Transistors”, CSTIC2011, March 14, 2011, Shanghai, China
[477] P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat T.
Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai,
“TiN/W/La
2
O
3
/Si High-k Gate Stack for EOT below o.5nm”, CSTIC2011,March 14, 2011,
Shanghai, China
[478] Invited Talk, Distinguished Lecture: H. Iwai, “Past and Future of Micro/Nano-Electronic
Devices”, One day National Workshop on Electronic Devices, April 7, 2011, Mizoram
University Aizawl, Mizoram, India
[479] Invited Talk: H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”,ISDMISC 2011,
April 12, 2011, Sikkim Manipal Institute of Technology, Sikkim, India
[480] H. Iwai, “Si nanowire FET technology”, ECS 219th Meeting, ECS Transactions,Vol.35, No.3, pp.33-53, May 2, 2011, Montreal, Canada
[481] P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T.
Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai,
“Effects of Metal Layer Insertion on EOT scaling in TiN/Metal/ La
2
O
3
Si High –k Gate
Stacks”, ECS 219th Meeting, ECS Transactions, Vol.35, No.2, pp.305-308, May 3, 2011,
Montreal, Canada
[482] C. Dou, K. Mukai, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Resistive switching behaviors of ReRAM having W/CeO
2
/Si/TiN structure” ,
ECS 219th Meeting, ECS Transactions,May 4, 2011, Montreal, Canada
[483] Yueh-Chin Lin, Chia-Hua Chang, K. Kakushima, H. Iwai, Tin-En Shie, Guan-Ning Huang,
Po-Ching Lu, Ting-Chun Lin and Edward Yi Chang, “Study of La
2
O
3
/HfO
2
Gate Dielectric for n-InAs Metal-Oxide-Semiconductor Capacitor”, ECS 219th Meeting, ECS Transactions, pp.397-401, May, 2011, Montreal, Canada
[484] Invited Talk, Distinguished Lecture: H. Iwai, “Future of Si Nano-CMOS Technology”,2011
IEEE EDS WIMNACT 29- Taiwan, IEEE EDS Mini-colloquium on Nanometer CMOS
Technology, May 27, 2011, National Chiao Tung University, Taiwang
[485] K. Ohmori, W. Feng, S. Sato, R. Hettiarachchi, M. Sato, T. Matsuki, K. Kakushima, H. Iwai, K.
Yamada, “Direct Real-Time Observation of Channel Potential Fluctuation, Correlated to
Random Telegraph Noise of Drain Current Using Nanowire MOSFETs with Four-Probe
Terminals”, 2011 Symposium on VLSI Technology, June 14-16, 2011, Kyoto, Japan
[486] D. Zade, K. Kakushima, T. Kanda, Y.C.Lin, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii,
E.Y. Chang, K. Natori, T. Hattori, H. Iwai, “Improving electrical characteristics of
W/HfO
2
/In o.53
Ga o.47
As gate stacks by altering deposition techniques”, Insulating Films on
Semiconductors(INFOS 2011), June 21-24, 2011, Grenoble, France
[487] D. Kitayama, T. Koyanagi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Effect of thin Si insertion at metal gate/highk interface on electrical characteristics of MOS device with La
2
O
3
”, Insulating Films on
Semiconductors(INFOS 2011), June 21-24, 2011, Grenoble, France
[488] H. Iwai, “Future of Si Nano-CMOS Technology”, ICMAT 2011 (International Conference on
Materials for Advanced Technologies), July 1, 2011, Singapore
[489] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Metal Inserted Poly-Si wirh High Temperature Annealing for Achieving
EOT of 0.62nm in La-silicate MOSFET”, 41 st European Solid-State Device Research
Conference, September 12-16, 2011, Helsinki, Finland
[490] M. Koyama, N. Shigemori, K. Ozawa, K. Tachi, K. Kakushima, O. Nakatsuka, K. Ohmori, K.
Tsutsui, A. Nshiyama, N. Sugii, K. Yamada, H. Iwai, “Si/Ni-Silicide Schottky Junctions with
49
Atomically Flat Interfaces Using NiSi
2
Source”, 41 st European Solid-State Device Research
Conference, September 12-16, 2011, Helsinki, Finland
[491] Keynote Speech: H. Iwai, “Future of Nano CMOS Technology”, 2011 IEEE Regional
Symposium on Micro and Nanoelectronics(IEEE-RSM 2011), September 29, 2011, Le
Meredien Hotel, Kota Kinabalu, Malaysia
[492] H. Iwai, “Miniaturization and future prospects of Si devices”, G-COE PICE International
Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by
World’s Leading Scientists, G-COE PICE International Symposium and IEEE EDS
Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists,
October 4, 2011, Tokyo Institute of Technology, Japan
[493] K. Kakushima, J. Kanehara, T. Hattori, K. Tsutsui, H. Iwai, “Boron depth profile of a plasma immersed substrate by XPS analysis”, G-COE PICE International Symposium and IEEE EDS
Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists,
October 4-5, 2011, Tokyo Institute of Technology, Japan
[494] T. Kawanago, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Nitrogen incorporated La-silicate gate dielectric with high scalability”,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists,October 4-5, 2011, Tokyo Institute of
Technology, Japan
[495] M. Mamat, T. Seki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai , “Evaluation of oxide traps in La based oxides for direct high-k/Si capacitor” ,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[496] A. Abudukelimu, A. Ablimit*, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui,
K. Natori, T. Hattori, H. Iwai, “Electron transport in ballistic diodes: influence of phonon generation in drain region” , G-COE PICE International Symposium and IEEE EDS
Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists,
October 4-5, 2011, Tokyo Institute of Technology, Japan
[497] M. Kouda, K. Ozawa, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Comparative study of
CeO
2
gate dielectrics using chemical vapor deposition and atomic layer deposition” , G-COE
PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano
Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[498] D. H. Zadeh, Y. Suzuki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai,“Characterization of metal Schottky junction for InGaAs substrate” ,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[499] C. Dou, S. Sato, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Si nanowire FET with asymmetric channel”, G-COE PICE International
Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by
World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan
[500] Y. Wu, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H.
Iwai, “An analytical model of a tunnel FET with Schottky junction” , G-COE PICE
International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices:
Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology,
Japan
[501] K. Tuokedaerhan, T. Kaneda, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Impact of annealing ambient for La
2
O
3
/Si capacitor” , G-COE
PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano
Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[502] D. Kitayama, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Effect of Silicate Formation at Metal Gate/High-k Interface on Electrical
Characteristics of La
2
O
3
gated MOS Devices” , G-COE PICE International Symposium and
IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s
Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan
[503] T. Suzuki, M. Kouda, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Formation and electrical
50
characterization of MgO - incorporated La
2
O
3
gate insulators by ALD” , G-COE PICE
International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices:
Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology,
Japan
[504] K. Nakajima, W. Li, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori,
T. Hattori, H. Iwai, “Interface state density measurements of 3D silicon channel by charge pumping method” , G-COE PICE International Symposium and IEEE EDS Minicolloquium on
Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011,
Tokyo Institute of Technology, Japan
[505] R. Hosoi, Y. Suzuki, D. H. Zadeh, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “A novel interpretation of frequency dispersed capacitances in InGaAs capacitor by conductance method” , G-COE PICE International
Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by
World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan
[506] W. Li, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H.
Iwai, “Interface state density measurements of 3D silicon channel by charge pumping method” ,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[507] S. Kano, C. Dou, M. Hadi, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Impact of metal electrode material on resistive switching properties of Ce oxides” , G-COE PICE International Symposium and IEEE EDS
Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists,
October 4-5, 2011, Tokyo Institute of Technology, Japan
[508] Y. Tanaka, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori,
H. Iwai, “Impact of annealing on structural change in amorphous carbon: effect of Fe catalyst” ,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists, G-COE PICE International
Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by
World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan
[509] Y. Tamura, R. Yoshihara, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai ,“A novel Ni silicidation technology for Schottky diode formation” ,
G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid
Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[510] K. Tsuneishi, M. Kouda, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai,“Electrical properties of Tm
2
O
3
gate dielectric and its scaling issues” , G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced
Hybrid Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo
Institute of Technology, Japan
[511] M. Hosoda, Y. Lee, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Size dependent phonon limited electron mobility of Si nanowire” , G-COE
PICE International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano
Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of
Technology, Japan
[512] K. Matsumoto, M. Koyama, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Ni silicidation for Si fin and nanowire structures” , G-COE PICE
International Symposium and IEEE EDS Minicolloquium on Advanced Hybrid Nano Devices:
Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo Institute of Technology,
Japan
[513] R. Yoshihara, Y. Tamura, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Electrical characterization of atomically flat NiSi
2
Schottky diode” , G-COE PICE International Symposium and IEEE EDS Minicolloquium on Advanced
Hybrid Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011, Tokyo
Institute of Technology, Japan
[514] J. Kanehara, Y. Takei, Y. Miyata, H. Nohira, Y. Izumi, T. Muro, T. Kinoshita, P. Ahmet, K.
Kakushima, K. Tsutsui, T. Hattori, H. Iwai, “Depth Profiling of As with Various Chemical
Bonding States Doped in Si Shallow Junction by Using Soft X-ray Photoelectron
Spectroscopy” , G-COE PICE International Symposium and IEEE EDS Minicolloquium on
Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists, October 4-5, 2011,
51
Tokyo Institute of Technology, Japan
[515] Y. Miyata, K. Akita, J. Kanehara, H. Nohira, Y. Izumi, T. Muro, T. Kinoshita, P. Ahmet, K.
Kakushima, K. Tsutsui, T. Hattori, H. Iwai, “Analysis of Boron Doped in Si Fin Structure by
Soft X-ray Photoelectron Spectroscopy” , G-COE PICE International Symposium and IEEE
EDS Minicolloquium on Advanced Hybrid Nano Devices: Prospects by World’s Leading
Scientists, October 4-5, 2011, Tokyo Institute of Technology, Japan
[516] M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori,
H. Iwai, “Electrical Properties of Rare-Earth oxides and La
2
O
3
Stacked Gate Dielectrics”, ECS
220 th Meeting,ECS Transactions, Vol.41, No.7, pp.119-124, October 9-14,2011, Boston, USA
[517] T. Kaneda, M. Kouda, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hatorri, H. Iwai, “Influence of Flash Lamp Annealing on Electrical Characteristics of MOS
Device with Si/ La
2
O
3
/n-Si Structure”, ECS 220 th Meeting, ECS Transactions, Vol.41, No.7, pp.157-164,October 9-14,2011, Boston, USA
[518] K. Nakajima, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Dependence of Interface-State Density on Three Dimensional Silicon
Structure Measured by Charge-Pumping Method”, ECS 220 th Meeting, ECS
Transactions,Vol.41, No.7, pp.293-298, October 9-14,2011, Boston, USA
[519] H. Nohira, A. Komatsu, K. Yamashita, K. Kakushima, H. Iwai, Y. Hoshi, K. Sawano, Y.
Shiraki, “XPS Study on Chemical Bonding States of highk /high-
μ
Gate Stacks for Advanced
CMOS”, ECS 220 th Meeting, ECS Transactions, Vol.41, No.7, pp.137-146, October 9-14,2011,
Boston, USA
[520] Y. Sakurai, K. Ohmori, K. Yamada, K. Shiraishi, K. Kakushima, H. Iwai, S. Nomura,
“Photoluminescence Characterization of the Interface Properties of Si Nanolayers and
Nanowires”, ECS 220 th Meeting, October 9-14,2011, Boston, USA
[521] Invited Talk: H. Iwai, “Materials and Structures for Future nano CMOS”, IEEE
Nanotechnology Materials and Devices Conference(NMDC) 2011, October 21, 2011, Jeju,
Korea
[522] Y. Tamura, R. Yoshihara, K. Kakushima, O. Nakatsuka, P. Ahmet, H. Nohira, K. Tsutsui, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Electrical Properties of
Ultrathin-Nickel-Silicide Schottky Diodes on Si(100)”, 15 th International Conference on Thin
Films, 2011, November 8, 2011, Kyoto, Japan
[523] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
T. Hattori, H. Iwai, “Characterization of Effective Electron Mobility in n/MOSFETs with
Direct Contact La-silicate/Si Structure”, 15 th International Conference on Thin Films, 2011,
November 8, 2011, Kyoto, Japan
[524] Y. Suzuki, D. Zade, R. Hosoi, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Electrical characteristics of La
2
O
3
/In
0.53
Ga
0.47A
As capacitors with surface nitridation”, 15 th International Conference on Thin Films, 2011, November 8, 2011,
Kyoto, Japan
[525] W. Feng, R. Hettiarachchi, Y. Lee, S. Sato, K. Kakushima, M. Sato, K. Fukuda, M. Niwa, K.
Yamabe, K. Shiraishi, H. Iwai, K. Ohmori, “Fundamental origin of excellent low-noise property in 3D Si-MOSFETs ~Impact of charge-centroid in the channel due to quantum effect on 1/ f noise ~, 2011 IEDM, December 5-7, 2010, Washington, USA
[526] H. Iwai, “Si Nano Electronics”, 2011 Tsukuba Nanotechnology Symposium(TNS’11),
December 15, 2011, University of Tsukuba, Japan
[527] Y. Wu, K. Kakushima, K. Ohmori, A. Nishiyama, H. Iwai, K. Yamada, “A Study on
Fabrication and Analytic Modeling of novel Schottky contact tunneling Transistors”, Tsukuba
Nanotechnology Symposium(TNS’11), December 15, 2011, University of Tsukuba, Japan
[528] C. Dou, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Si nanowire FET with asymmetric channel”, Tsukuba Nanotechnology
Symposium(TNS’11), December 15, 2011, University of Tsukuba, Japan
[529] Invited Talk, Distinguished Lecture: H. Iwai, “Future of Nano CMOS Technology”,
International Workshop on The Future of Nano Electronics Research and Challenges Ahead,
December 26, 2011, SKP Engineering College, Tiruvannamalai, Tamilunadu, India
[530] Invited Talk, Distinguished Lecture: H. Iwai, “Future of Nano CMOS
Technology”,WINMACT 30, December 30, 2011, Sri Rama Krishna Institute, India
[531] Keynote Lecture: H. Iwai, “FUTURE OF NANO CMOS TECHNOLOGY”, International
Conference on Nanoscience and Technology(ICONSAT 2012), January 21, 2012, Hyderabad,
India
52
[532] Invited Talk, Distinguished Lecture: H. Iwai, “Future of Nano-CMOS Technology”,
WIMNACT Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology 31,
January 30, 2012, Tokyo Institute of Technology, Japan
[533] Invited Talk, Distinguished Lecture: H. Iwai, “Nano CMOS and High-k Technology”, IEEE
EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012,
Tokyo Institute of Technology, Japan
[534] H. Iwai, “High-k Gate Dielectrics for Future III-V FET”, IEEE EDS MQ WIMNACT 32
C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of
Technology, Japan
[535] K. Kakushima, J. Kanehara, T, Hattori, K. Tsutsui, H. Iwai, “Boron depth profile of a plasma immersed substrate by XPS analysis”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS
Japan Chapter and TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[536] T. Kawanago, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Nitrogen incorporated La-silicate gate dielectric with high scalability”, IEEE
EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012,
Tokyo Institute of Technology, Japan
[537] M. Mamat, T. Seki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Evaluation of oxide traps in La based oxides for direct high-k/Si capacitor”,
IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10,
2012, Tokyo Institute of Technology, Japan
[538] A. Abudukelimu, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Influence of Heat Generation within Drain Region on Transport of Hot
Electrons”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT,
February 10, 2012, Tokyo Institute of Technology, Japan
[539] M. Kouda, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Comparative study of CeO
2 gate dielectrics using chemical vapor deposition and atomic layer deposition”, IEEE EDS MQ
WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo
Institute of Technology, Japan
[540] M. Kouda, T. Suzuki, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Stack structures of ALD-
La
2
O
3
and CVD-CeO
2
: fabrication and mobility improvement effects”, IEEE EDS MQ
WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo
Institute of Technology, Japan
[541] Y. Lee, K. Kakushima, K. Natori, H. Iwai, “Corner Effects on Phonon-Limited Mobility in
Rectangular Si Nanowire MOSFETs”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS
Japan Chapter and TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[542] D. H. Zadeh, R. Hosoi, Y. Suzuki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii,K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Electrical Characterization and improvement of high-k/InGaAs devices”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[543] C. Dou, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T.
Hattori, H. Iwai, “Si nanowire FET with asymmetric channel”, IEEE EDS MQ WIMNACT 32
C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of
Technology, Japan
[544] Y. Wu, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii,K. Tsutsui, K. Natori, T. Hattori, H.
Iwai, “An analytical model of a tunnel FET with Schottky junction”, IEEE EDS MQ
WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo
Institute of Technology, Japan
[545] W. Li, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H.
Iwai, “Interface state density measurements of 3D silicon channel by conductance method” ,IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT,
February 10, 2012, Tokyo Institute of Technology, Japan
[546] K. Tuokedaerhan, T. Kaneda, M. Mamat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama,
N. Sugii, K. Natori, T. Hattori, H. Iwai, “Impact of Annealing Ambient for La
2
O
3
/Si
Capacitor”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT,
February 10, 2012, Tokyo Institute of Technology, Japan
[547] D. Kitayama, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T.
Hattori, H. Iwai, “Effect of Silicate Formation at Metal Gate/High-k Interface on Electrical
Characteristics of La
2
O
3
gated MOS Devices”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[548] K. Nakajima, W. Li, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
53
T. Hattori, H. Iwai, “Interface state density measurements of 3D silicon channel by charge pumping method”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and
TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[549] R. Hosoi, Y. Suzuki, D. H. Zadeh, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “A novel interpretation of frequency dispersed capacitances in InGaAs capacitor by conductance method”, IEEE EDS MQ WIMNACT 32
C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of
Technology, Japan
[550] T. Suzuki, M. Kouda, K. Kakushima, P. Ahmet, H. Iwai, T. Yasuda, “Formation and electrical characterization of MgO - incorporated La
2
O
3
gate insulators by ALD” , IEEE EDS MQ
WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo
Institute of Technology, Japan
[551] S. Kano, C. Dou, M. Hadi, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Impact of metal electrode material on resistive swirching properties of Ce oxides”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of Technology, Japan
[552] Y. Tamura, R. Yoshihara, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “A novel Ni silicidation technology for Schottky diode formation”,
IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10,
2012, Tokyo Institute of Technology, Japan
[553] Y. Tanaka, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori,
H. Iwai, “Impact of annealing on structural change in amorphous carbon: effect of Fe catalyst”,
IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10,
2012, Tokyo Institute of Technology, Japan
[554] K. Matsumoto, M. Koyama, Y. Wu, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Ni silicidation for Si Fin and nanowire strucures” IEEE
EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012,
Tokyo Institute of Technology, Japan
[555] M. Hosoda, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori,
H. Iwai, “Size-dependent phonon-limited electron mobility in Si Nanowire MOSFETs”, IEEE
EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012,
Tokyo Institute of Technology, Japan
[556] K. Tsuneishi, M. Kouda, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Electrical properties of Tm2O3 gate dielectric and its scaling issues”, IEEE EDS MQ WIMNACT 32 C0-sponsored by EDS Japan Chapter and TIT,
February 10, 2012, Tokyo Institute of Technology, Japan
[557] R, Yoshihara, Y. Tamura, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “Electrical characterization of atomically flat NiSi2 Schottky diode”, Ni silicidation for Si Fin and nanowire strucures” IEEE EDS MQ WIMNACT 32
C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of
Technology, Japan
[558]
H. Iwai, “High-k, Metal Gate, Channel Materials New material integration in CMOS technologies”, ULIS 2012, Tutorial, March 5, 2012, Grenoble, France
[559] K. Kakushima, Y. Suzuki, D. Zade, T. Kawanago, H. Iwai, “High-k Gate Dielectrics for
InGaAs Substrates”, International Symposium on “Development of Core Technologies for
Green Nanoelectronics”, March 14, 2012, Miraican Hall, National Museum of Emerging
Science and Innovation, Japan
[560] R. Hosoi, Y. Suzuki, D. Zadeh, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii,
K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Characterization of matal Schottky junction for
In
0.53
Ga
0.47A
As substrates”, CSTIC 2012, March 18-19, 2012, Shanghai, China
[561] S. Kano, C. Dou, M. Hadi, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, L. Tsutsui, Y.
Kataoka, K. Natori, E. Miranda, T. Hattori, H. Iwai, “Influence electrode materials on CeO x based resistive switching”, CSTIC 2012, March 18-19, 2012, Shanghai, China
[562] W. Li, K. Nakajima, C. Dou, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, Y.
Kataoka, K. Natori, T. Hattori, H. Iwai, “Evaluation of Interfacial State Density of MOS
Capacitor with Three-Dimensional Channel by Conductance Method”, CSTIC 2012, March
18-19, 2012, Shanghai, China
[563] Invited Talk, Distinguished Lecture:
H. Iwai, “Past and Future of Micro/Nano-Electronic
Devices”, IEEE EDS, April 28, 2012, Institute of Engineering & Management, Kolkata, India
[564] Invited Talk, Distinguished Lecture:
H. Iwai, “Past and Future of Micro/Nano-Electronic
54
Devices”, IEEE EDS, April 30, 2012, NIT Manipur, Imphal, India
[565] K. Ohmori, W. Feng, R. Hettiarachchi, Y. Lee, S. Sato, K. Kakushima, M. Sato, K. Fukunda,
M. Niwa, K. Yamabe, K. Shiraishi, H. Iwai, K. Yamada, “Low-frequency noise reduction in Si
Nanowire MOSFETs”, ECS 221 st Meeting, ECS Transactions,Vol.45, No.3, pp.437-442, May
9, 2012, Seattle, WA, USA
[566] E. Miranda, S. Kano, C. Dou, J. Sune, K. Kakushima, H. Iwai, “New experimental evidences of conductance quantization in electroformed oxide stacks”, E-MRS 2012 Spring Meeting,
May, 2012, Strasbourg, France
[567] Y. Miyata, J. Kanehara, H. Nohira, Y. Izumi, T. Muro, T. Kinoshita, P. Ahmet, K. Kakushima,
K. Tsutsui, T. Hattori, H. Iwai, “Soft X-ray Photoelectron Spectroscopy Study of Boron Doped on Top Surfaces and Sidewalls of Si Fin Structures”, 2012 12 th International Workshop on
Junction Technology(IWJT2012), May 14-15, 2012, Shanghai, China
[568] H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm Generation”, Electron Devices
Colloquium, June 4, 2012, Imec, Leuven, Belgium
[569] H. Iwai, “Future of Si devices”, 2012 Advanced Resesaerch Workshop Future Trends In
Microelectronics: Into the Cross Currents, June 27, 2012, Corsica, France
[570] Y. Sakurai, K. Ohmori, K. Yamada, K. Kakushima, T. Tayagaki, H. Iwai, Y. Kanemitsu, K.
Asakawa, K. Shiraishi, S. Nomura, “Photoluminescence Properties of Si Nanolayers and Si
Nanowires”, Tsukuba Nanotechnology Symposium 2012(TNS’12), July 26-27,2012, Japan
[571] T. Kawanago, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, H. Iwai, “(100)-and (110)-oriented nMOSFETs with highly Scaled EOT in
La-silicate/Si Interface for Multi-gate Architecture”, ESSDERC 2012, September 18, 2012,
Bordeaux, France
[572] M. Koyama, M. Casse, R. Coquand, S. Barraud, H. Iwai, G. Ghibaudo, G. Reimbold, “Study of Carrier Transport in Strained and Unstrained SOI Tri-gate and Omega-gate Si Nanowire
MOSFETs”, ESSDERC 2012, September 18, 2012, Bordeaux, France
[573] D. H. Zadeh, H. Ohmine, Y. Suzuki, K. Kakuhisma, P. Ahmet, Y. Kataoka, A. Nisiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “La
2
O
3
/ In o.53
Ga
0.47
A
S metal-oxide-semiconductor capacitor with low interface state density using TiN/W gate electrode”, SSDM 2012, September, 2012, Kyoto, Japan
[574] H. Iwai, “Future of Nanoelectronics and Devices”, 2012 International Semiconductor
Conference Dresden – Grenoble(ISCDG), September 25, 2012, Grenoble, France
[575] H. Iwai, B. de Salvo, “Scaling and Beyond for Logic and Memories. Which perspectives?”,
2012 International Semiconductor Conference Dresden – Grenoble(ISCDG), Short Course,
September 26, 2012, Grenoble, France
[576] K. Kakushima, Y. Tamura, R. Yoshihara, K. Tsutsui, H. Iwai, “Interface Controlled Stacked
Ni Silicidation Process with Schottky Barrier Height Controllability”, IUMRS-ICEM 2012,
September 28, 2012, Yokohama, Japan
[577]
H. Iwai, “Introduction of New Materials into CMOS Devices”, ECS 222 nd Meeting, ECS
Transactions, Vol.50, No.5, pp.13-20, October 10, 2012, Honolulu, Hawaii
[578]
H. Iwai, “Si Nanowire Technology”, ECS 222 nd Meeting, ECS Transactions, Vol.50, No.4, pp.251-260, October 10, 2012, Honolulu, Hawaii
[579] Y. Tamura, R. Yoshihara, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “A Proposal of Schottky Barrire Height Tuning
Method with Interface Controlled Ni/Si Stacked Silicidation Process”, ECS 222 nd Meeting,
ECS Transactions, Vol. , No. , pp. , October 8, 2012, Honolulu, Hawaii
[580] Y. Tanaka, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K. Tsutsui, K.
Natori, T. Hattori, S. Yamasaki, H. Iwai, “TiC Electrode Formed by Multi-Stacking Process for Diamond Contact Metal”, ECS 222 nd Meeting, ECS Transactions, Vol. , No. , pp. ,
October 9, 2012, Honolulu, Hawaii
[581] Y. Suzuki, D. H. Zadeh, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Effect of In
0.53
Ga
0.47A
As surface nitridation on electrical characteristics of high-k/capacitors”, ECS 222 nd Meeting, ECS Transactions, Vol.50,
No.4, pp.145-150, October 9, 2012, Honolulu, Hawaii
[582] R. Yoshihara, Y. Tamura, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Thermally stable NiSi
2
for Ge contact with Schottky barrirer height modulation capability”, ECS 222 nd Meeting, ECS Transactions, Vol.50, No.9, pp.217-221, October 9, 2012, Honolulu, Hawaii
[583] K. Tuokedaerhan, R. Tan, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, ”Interface Properties of La-silicate MOS Capacitors
55
with Tungsten Carbide Gate Electrode for Scaled EOT”, ECS 222 nd Meeting, ECS
Transactions, Vol.50, No.4, pp.281-284, October 10, 2012, Honolulu, Hawaii
[584] J. Chen, K. Tsuneishi, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Thickness dependent electrical characteristics of
AlGaN/GaN MOSHEMT with La
2
O
3 gate dielectrics”, ECS 222 nd Meeting, ECS Transactions,
Vol.50, No.3, pp.353-357, October 10, 2012, Honolulu, Hawaii
[585] K. Tsuneishi, J. Chen, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Ti silicide electrodes low contact resistance for undoped AlGaN/GaN structure”, ECS 222 nd Meeting, ECS Transactions, Vol.50, No.3, pp.447-450, October 11, 2012, Honolulu, Hawaii
[586] E. Miranda, T. Kawanago, K. Kakushima, J. Sune, H. Iwai, “Analysis and modeling of the gate leakage current in advanced nMOSFET devices with severe gate–to-drain dielectric breakdown”, ESREF2012, October, 2012, Cagliari, Italy
[587] Distinguished Lecture: H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm
Generation”, Workshop and IEEE EDS Mini-colloquim on Nanometer CMOS
Technology(WIMNACT 35), November 29, 2012, Nanyang Technological University,
Singapore
[588] Distinguished Lecture: H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm
Generation”, Workshop and IEEE EDS Mini-colloquim on Nanometer CMOS
Technology(WIMNACT 36), November 30, 2012, Penang Skills and Development Center,
Penang, Malaysia
[589] H. Iwai, “Future of nano CMOS technology”, EDSSC2012, December 4, 2012, Thailand
[590] H. Iwai, “Past and Future of Micro/Nano Electronic Devices”, IEEE Mini Colloquium on The
Future of Nano Electronics, December 27, 2012, Dhanalakshmi Srinivasan Engineering
College, Tiruvannamalai, Tamil Nadu, India
[591] H. Iwai, “Future of nano CMOS Technology”, ICEVENT2013, January 8, 2013,
Tiruvannamalai, India
[592] Poster: T. Kawanago, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Interface properties of La-silicate gate dielectrics on
Si(110)surface”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[593] Poster: D.H.Zade, H. Oomine, Y. Suzuki, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama,
N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “La
2
O
3
/In
0.53
Ga
0.47A
As metal-oxide-semiconductor capacitor with low interface state density using TiN/W gate electrode”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[594] Poster: M. Hadi, S. Kano, C. Dou, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Resistive Switching Device using Ce-oxide with
Ni-silicide Electrodes”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[595] Poster: K. Tuokedaerhan, S. Hosoda, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Work Function Extraction of W,Ta and Ti
Carbides Formed by Multi Stacked Process”, Workshop and IEEE EDS Mini-colloquium on
Nanometer CMOS Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and
Kuramae Hall, Tokyo Institute of Technology, Japan
[596] Poster: W. Li, K. Nakajima, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K.
Natori, T. Hattori, H. Iwai, “Extraction of Interface State Density of 3-dimensional Si channel”,
Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT
37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of Technology,
Japan
[597] Poster: J. Chen, G. Lu, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Electrical characteristics of AlGaN/GaN HEMT with
La-oxide gate dielectrics”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[598] Poster: S. Kano, C. Dou, M. Hadi, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Transient Switching Characteristics of Ce-oxide
56
Resistive Switching Devices”, Workshop and IEEE EDS Mini-colloquium on Nanometer
CMOS Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall,
Tokyo Institute of Technology, Japan
[599] Poster: Y. Suzuki, D.H.Zadeh, H. Oomine, K. Kakushima, P. Ahmet, Y. Kataoka, A.
Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Interface Engineering of
La
2
O
3
/InGaAs Capacitors with High Temperature Stability”, Workshop and IEEE EDS
Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37), February 18, 2013,
Royal Blue Hall and Kuramae Hall, Tokyo Institute of Technology, Japan
[600] Poster: Y. Tanaka, K. Kakushima, P. Ahmet, Y. Kataoka, K. Tsutsui, A. Nishiyama, N. Sugii,
K. Natori, T. Hattori, H. Iwai, “Interface controlled metal contact for n -type diamonds”,
Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT
37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of Technology,
Japan
[601] Poster: Y. Tamura, R. Yoshihara, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Stacked Ni-Silicidation Process for Schottky
Barrier FET”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[602] Poster: K. Tsuneishi, J. Chen, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii,
K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “A Robust Ohmic Contact Process for AlGaN/GaN using Ti-silicide electrodes” , Workshop and IEEE EDS Mini-colloquium on Nanometer
CMOS Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall,
Tokyo Institute of Technology, Japan
[603] Poster: M. Hosoda, K. Kakushima, K. Natori, S. Yamasaki, H. Ohashi, H. Iwai, “Carrier transport modeling in diamonds”, Workshop and IEEE EDS Mini-colloquium on Nanometer
CMOS Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall,
Tokyo Institute of Technology, Japan
[604] Poster: K. Matsumoto, M. Koyama, Y. Wu, K. Kakushima, P. Ahmet, Y. Kataoka, A.
Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Size dependent resistivity change of Ni-silicides in nano-region”, Workshop and IEEE EDS Mini-colloquium on
Nanometer CMOS Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and
Kuramae Hall, Tokyo Institute of Technology, Japan
[605] Poster: Y. Xhao, M. Maimaitrishat, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Separation of bulk and interface traps of La-silicate on
Si(100) surface”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[606] Poster: T. Inamura, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K. Tsutsui,
K. Natori, T. Hattori, H. Iwai, “Formation of Fe-silicides using Multi-Stacking Sputtering
Process”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[607] Poster: H. Oomine, D.H.Zadeh, Y. Suzuki, K. Kakushima, P. Ahmet, Y. Kataoka, A.
Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “La-Oxide Gate Dielectrics for
InGaAs Substrates formed by Chemical Vapor Deposition”, Workshop and IEEE EDS
Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37), February 18, 2013,
Royal Blue Hall and Kuramae Hall, Tokyo Institute of Technology, Japan
[608] Poster: T. Seki, T. Kawanago, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii,
K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Infrared absorption study of La-silicate gate dielectrics”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[609] Poster: A. Takemasa,K. Kakushima, P. Ahmet, Y. Kataoka, K. Tsutsui, A. Nishiyama, N.
Sugii, K. Natori, T. Hattori, H. Iwai, “Impact of Surface Treatments for Metal Contact on p-type Diamonds”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[610] Poster: S. Hosoda, K. Tuokedaerhan, K. Kakushima, P. Ahmet, K. Tsuitsui, Y. Kataoka, A.
Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, “Improvenents in interface, states with
W-carbide metal gate for La
2
O
3
/si MOS Capacitor”, Workshop and IEEE EDS
57
Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37), February 18, 2013,
Royal Blue Hall and Kuramae Hall, Tokyo Institute of Technology, Japan
[611] Poster: R. Yoshihara, Y. Tamura, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “A Novel Ohmic Contact Process for n-Ge
Substrates”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[612] Poster: J. Song, M. Koyama, K. Matsumoto, K. Kakushima, O. Nakatsuka, K. Ohmori, K.
Tsutsui, A. Nishiyama, N. Sugii, K. Yamada, H. Iwai, “Atomically flat Ni-silicide/Si interface using NiSi
2
sputtering”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS
Technology (WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo
Institute of Technology, Japan
[613] Poster: P. Liu, K. Kakushima, H. Iwai, “Transport characteristics of 2-dimensional hole gas in
AlGaN/GaN”, Workshop and IEEE EDS Mini-colloquium on Nanometer CMOS Technology
(WIMNACT 37), February 18, 2013, Royal Blue Hall and Kuramae Hall, Tokyo Institute of
Technology, Japan
[614] Poster: M. Okamoto, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Extraction of Energy Band Diagram of AlGaN/GaN with SiO
2
Capped Annealing using X-ray Photoelectron Spectroscopy”, Workshop and IEEE
EDS Mini-colloquium on Nanometer CMOS Technology (WIMNACT 37), February 18, 2013,
Tokyo Institute of Technology, Japan
[615] T. Seki, T. Kawanago, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, K.
Tsutsui, K. Natori, T. Hattori, H. Iwai, “Electrical and Infrared Absorption Studies on
La-silicate/Si Interface”, International Symposium on Next-Generation Electronics(ISNE
2013), February 25, 2013, I-Shou University, Kaoh siung, Taiwan
[616] M. Hosoda, K. Kakushima, K. Natori, S. Yamasaki, H. Ohashi, H. Iwai, “On the electron conduction in n -diamond”, International Symposium on Next-Generation Electronics(ISNE
2013),February 25, 2013, I-Shou University, Kaoh siung, Taiwan
[617] K. Matsumoto, M. Koyama, Y. Wu, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, K. Tsutsui, K. Natori, T. Hattori, H. Iwai, “Electrical Analyses of Nickel Silicide
Formed on Si Nanowires with 10-nm-width”, International Symposium on Next-Generation
Electronics(ISNE 2013),February 25, 2013, I-Shou University, Kaoh siung, Taiwan
[618] H. Iwai, “III-V MOSFET for Next Generation”, Taiwan-Japan Workshop on Nano Devices
2013, March 5, 2013, National Chiao Tung University, Taiwan
[619] Invited Talk:
H. Iwai, “Future of Nano CMOS Technology”, China Semiconductor
Technology International Conference (CSTIC) 2013, March 17, 2013, Shanghai, China
[620] E. Y. Chang, H. D. Trinh, Y. C. Lin, H. Iwai, “Development of High k/III-V (InGaAs, InAs,
InSb) Structures for Future Low Power, High Speed Device Applications”, 2013 MRS Spring
Meeting, April 2, 2013, San Francisco, California, USA
[621] M. Casse, S. Barraud, R. Coquand, M. Koyama, D. Cooper, C. Vizioz, C. Comboroure, P.
Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, S. Barnola, V. Delaye, F. Aussenac, G.
Ghibaudo, H. Iwai, G. Reimbold, “Strain-Enhanced Performance of Si-Nanowire FETs”, ECS
223 nd Meeting, ECS Transactions, Vol.53, No.3, pp.125-136, May 14, 2013, Toronto, Canada
[622] K. Kakushima, R. Yoshihara, K. Tsutsui, H. Iwai, “A Low Temperature Ohmic Contact
Process for n -type Ge Substrates”, 2013 13 th International Workshop on Junction
Technology(IWJT2013), June 6, 2013, Kyoto, Japan
[623] Poster: K. Kakushima, H. Wakabayashi, K. Tsutsui, H. Iwai, “Interface State Density of
Passivation/Nanowire Interface”, The 1 st International Symposium on Nano-Wire Si Solar
Cells/ MEXT “FUTURE-PV Innovation” Project, June 10, 2013, Tokyo Tech Front, Tokyo
Institute of Technology, Tokyo, Japan
[624] M. Koyama, M, Casse, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold, “Study of Low-frequency Noise in SOI Tri-gate Silicon Nanowire MOSFETs”, 22 nd ICNF, June 26,
2013, Montpellier, France
[625] E. Miranda, T. Kawanago, K. Kakushima, J. Sune, H. Iwai, “Modeling of the Output
Characteristics of Advanced N-MOSFETs After a Severe Gate-to-Channel Dielectric
Breakdown”, Insulating Films on Semiconductors(INFOS 2013), June 26, 2013, Cracow,
Poland
[626] B.L.Yang, H. Wong, S. Dong, K. Kakushima, H. Iwai, “Charge Trapping and Detrapping
Characteristics CeO
2/
La
2
O
3
Stack Gate Dielectrics”, 7 th International Conference on Materials, for Advanced Technologies(ICMAT2013), July 3, 2013, Singapore
58
[627] Invited Talk: H. Iwai, “Ultimate CMOS scaling”, Korean International Summer School on
Nanoelectronics(nano-KISS 2013), July 3, 2013, Daejeon, Korea
[628] Keynote Speech: H. Iwai, “Future of Nano CMOS Technology”, SBMicro 2013, September 4,
2013, Curitiba, Brazil
[629] Invited Talk: H. Iwai, “Future of Nano CMOS Technology”, EDS Mini Colloquim, September
9, 2013, UNICAMP, Campinas, Brazil
[630] T. Kawanago, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Advantage of TiN Schottky Gate over Conventional Ni for
Improved Electrical Characteristics in AlGaN/GaN HEMT”, ESSDERC 2013, September 17,
2013, Bucharest, Romania
[631] M. Koyama, M. Casse, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold,
“Influence of Device Scaling on Low-frequency Noise in SOI Tri-gate Si Nanowire N-and
PMOS FETs”, ESSDERC 2013, September 19, 2013, Bucharest, Romania
[632] D. H. Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Scalable La-silicate Gate Dielectric on InGaAs
Substrate with High Thermal Stability and Low Interface State Density”, 2013 International
Conference on Solid State Devices and Materials(SSDM),September 26, 2013, Fukuoka, Japan
[633] Poster: M. S. Hadi, S. Kano, C. Dou, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N.
Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “A Proposal of a Forming-Free
Resistive Switching Memory based on Breakdown and Anodic Reoxidation of thin SiO
2 on
NiSi
2
Electrode using CeO x
Buffer Layer”, 2013 International Conference on Solid State
Devices and Materials(SSDM),September 26, 2013, Fukuoka, Japan
[634] K. Nayak, M. Bajaj, A. Konar, P. J. Oldiges, H. Iwai, K.V.R.M. Murali, V.R. Rao, “Negative
Differential Conductivity and Carrier Heating in Gate-All-Around Si Nanowire FETs and its
Impact on CMOS logic Circuits”, 2013 International Conference on Solid State Devices and
Materials(SSDM),September 26, 2013, Fukuoka, Japan
[635] Poster: P. Liu, K. Kakushima, H. Iwai, “Characterization of Two-Dimensional Hole Gas at
GaN/AlGaN Heterointerface”, The 1st IEEE Workshop on Wide Bandgap Power
Devices and Applications, October 27-29, 2013, Columbus, Ohio,USA
[636] Poster: M. Okamoto, K. Kakushima, Y. Kataoka, A, Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, H. Iwai, “An Ohmic Contact Process for AlGaN/GaN Structures using TiSi
Applications, October 27-29, 2013, Columbus, Ohio,USA
2
Electrodes”,
The 1st IEEE Workshop on Wide Bandgap Power Devices and
[637] S. Hosoda, K. Tuokedaerhan, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Reliability of La-silicate MOS capacitors with tungsten carbide gate electrode for scaled EOT”, ECS 224 nd Meeting, ECS Transactions,
Vol.58, No.7, pp.61-64, October 28, 2013, San Francisco, CA, USA
[638] J. Song, K. Matsumoto, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi,
K. Tsutsui, K. Natori, H. Iwai, “Resistivity of Ni silicide nanowires and its dependence on Ni film thickness used for the formation”, ECS 224 nd Meeting, ECS Transactions, Vol.58, No.7, pp.87-91, October 28, 2013, San Francisco, CA, USA
[639] H. Oomine, D.H.Zadeh, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi,
K. Tsutsui, K. Natori, H. Iwai, “Electrical characterization of atomic layer deposited La
2
O
3 films on In
0.53
Ga
0.47A
As substrates”, ECS 224 nd Meeting, ECS Transactions, Vol.58, No.7, pp.385-389, October 30, 2013, San Francisco, CA, USA
[640] T. Inamura, A. Sasaki, K. Aoki, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “A stacked sputtered process for β -FeSi
2 formation”, ECS 224 nd Meeting, ECS Transactions, Vol. , No. , pp. , October 30, 2013,
San Francisco, CA, USA
[641] Poster: K. Tuokedaerhan, S. Hosoda, Y. Nakamura, K. Kakushima, Y. Kataoka, A. Nishiyama,
N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Influence of Carbon Incorporation in W Gate Electrode for La-silicate Gate Dielectrics”, 2013 International Workshop on
DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES-SCINCE AND
TECHNOLOGY-, November 7, 2013, University of Tsukuba, Ibaraki, Japan
[642] Poster: Y. Wu, H. Hasegawa, K. Kakushima, K. Ohmori, T. Watanabe, H. Wakabayashi, K.
Tsutsui, A. Nishiyama, N. Sugii, Y. Kataoka, K. Natori, K. Yamada, H. Iwai, “Influence of
Band Discontinuities at Source-Channel contact in Tunnel FET Performance”, 2013
International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON
DEVICES-SCINCE AND TECHNOLOGY-, November 7, 2013, University of Tsukuba,
Ibaraki, Japan
59
[643] D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Low D it
High-k/In
0.53
Ga
0.47
As Gate Stack with
CET down to 0.73 nm and Thermally Stable Silicide Contact by Suppression of Interfacial
Reaction”, IEDM 2013,December 9, 2013, Washington, DC
[644] Distinguished Lecture: H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS,
WIMNACT 38, December 27, 2013, Thiagarajar College of Engineering, Tamilnadu Madurai,
India
[645] Plenary Talk: H. Iwai, “Future of Nano CMOS Technology”, International Conference on
VLSI Design 2014, January 7, 2014, Convocation Hall, IIT Bombay, Mumbai, India
[646] H. Iwai, “Future of Multi-Gate CMOS Technology”, Euro SOI 2014, January 29,2014,
Tatrragona Spain
[647] H. Iwai, “Future of Nano-CMOS Technology”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[648] Poster: T. Kawanago, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Advantage of TiN Schottky Gate over Conventional Ni for
Improved Electrical Characteristics in AlGaN/GaN HEMT”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[649] Poster: D. Hassan Zadeh, H. Oomine, K. Kakushima, H. Iwai, “Highly Scalable La
2
O
3
/InGaAs Gate Stack with Low Interface State Density”,The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[650] Poster: M.S. Hadi, C. Dou, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
A study on Resistive Memory based on
Breakdown and Anodic Reoxidation of thin SiO2 on NiSi2 Electrode with CeOx
Buffer Layer”,
The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February
7, 2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[651] Poster: C. Dou, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Determination of oxide traps distribution high-k/InGaAs MOS capacitor by capacitance-voltage measurement”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[652] Poster: Y. Wu, H. Hasegawa, K. Kakushima, H. Wakabayashi, K. Tsutsui, A. Nishiyama, N.
Sugii, Y. Kataoka, K. Natori, H. Iwai, “Influence of structure parameter on Mg2Si-Si
Hetero-junction Tunneling FET”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[653] Poster: K. Tuokedaerhan, S. Hosoda, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Mobility Improvement of La-silicate MOSFET by W2C Gate Electrode”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39,
February 7, 2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[654] Poster: W. Li, A. Sasaki, H. Oozu, K. Aoki, K. Kakushima, Y. Kataoka, A. Nishiyama, N.
Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
Resistivity Measurement of
Monoclinic Thin Tungsten Oxide Film Due to Annealing Processes”,
The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[655] Poster: J. Chen, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H, Iwai, W. Saito, “
Electrical characteristics of AlGaN/GaN HEMT with La2O3 gate dielectrics”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[656] Poster: T. Inamura, T. Kato, A. Sasaki, K. Aoki, K. Kakushima,Y. Kataoka, A. Nishiyama, N.
Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
A study on silicide semiconductors for high efficiency thin film photovoltaic devices”,
The Workshop on
Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[657] Poster: H. Oomine, D.H.Zadeh, K. Kakushima, A. Nishiyama, N. Sugii, Y. Kataoka, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
Effect of pretreatment for high-/k//InGaAs interface property”,
The Workshop on Future Trend of
60
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[658] Poster: T. Seki, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “
Physical understanding of La-silicate gate dielectrics thermally formed by interface reaction on Si(110) and (111)”,
The Workshop on
Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[659] Poster: A. Takemasa, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Electrical characteristics of Ti, Ni, NiSi2 and Ni3P/n-diamond contacts”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[660] Poster: S. Hosoda, K. Tuokedaerhan, K. Kakushima, K. Tsutsui, Y. Kataoka, A. Nishiyama, N.
Sugii, H. Wakabayashi, K. Natori, T. Hattori, H. Iwai, “
Atomically flat interface of
La-silicate/Si with W2C gate electrodes”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[661] Poster: R. Yoshihara, M. Motoki, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
Interface control process toward un-pinned metal/germanium Schottky contact”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[662] Poster: J. Song, K. Matsumoto, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
Reduction of the resistivities of Ni
Silicide formed by the reaction of Si nanowire and Ni thin films”,
The Workshop on
Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[663] Poster: H. Imamura, T. Inamura, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “
Characterization of Thin NiSi2 Films by
Stacked Silicidation Sputtering Process with Kr Gas”,
The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[664] Poster: M. Okamoto, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, H. Iwai, W. Saito, “An Ohmic Contact Process for AlGaN/GaN Structures using
TiSi2 Electrode”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39,
February 7, 2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[665] Poster: T. Shoji, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Silicon Nanowire Solar Cells: Surface Passivation and Interface
Analysis”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[666] Poster: Y. Nakamura, K. Kakushima, Y. Kataoka, A. Nishiyama, H. Wakabayashi, N. Sugii, K.
Tsutsui, K. Natori, H. Iwai, “
Measurement of flat-band voltage shift using multi-stacked dielectric film”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[667] Poster: H. Hasegawa, Y. Wu, J. Song, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Improvement of tunnel FET performance using narrow bandgap semiconductor silicide /Si hetero-structure source electrode”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[668] Poster: M. Motoki, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Dependence between Sheet Resistance and Annealing
Temperature of Ni Germanide Formed by Multi-Layered Ni and Ge Films”, The Workshop on
Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[669] Poster: P. Liu, A. Nakajima, K. Kakushima, T. Makino, M. Ogura, S. Nishizawa, H. Iwai, H.
Ohashi, “ A study on mobility of 2D hole gas in AlGaN/GaN heterostructure with piezo- and spontaneous polarization”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[670] I Poster: Y.M. Lei, S. Munekiyo, K. Kakushima, T. Kawanago, Y. Kataoka, A. Nishiyama, N.
61
Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, M. Furuhashi, N. Miura, S. Yamakawa,
“ Interface reaction analysis of La2O3/SiC upon annealing by ATR-FTIR”, The Workshop on
Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall,
Suzukakedai Campus, Tokyo Institute of Technology, Japan
[671] Poster: M. Yoon, K. Terayama, A. Nakajima, S. Nishizawa, H. Ohashi, K. Kakushima, H.
Wakabayashi, K. Tsutsui, H. Iwai, “
Investigation into scaling law in AlGaN/GaN Fin field effect transistors by device simulation”,
The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[672] Poster: T. Kato, T. Inamura, A. Sasaki, K. Aoki, K. Kakushima, Y. Kataoka, A. Nishiyama, N.
Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, “Electrical characteristic of b-FeSi2”,
The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7, 2014,
Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[673] Poster: Y. Matsukawa,M. Okamoto, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H.
Wakabayashi, K. Tsutsui, K. Natori, H. Iwai, W. Saito, “An Ohmic Contact Process for
AlGaN/GaN Structures using TiCElectrode”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[674] Poster: Y. Takei, M. Okamoto, S. Man, R. Kayanuma, M. Kamiya, W. Saito, K. Tsutsui, K.
Kakushima, H. Wakabayashi, Y. Kataoka, H. Iwai, “Contact resistances depending on AlGaN layer thickness for AlGaN/GaN HEMT structures”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[675] Poster: M. Kamiya, Y. Takei, W. Saito, K. Kakushima, H. Wakabayashi, Y. Kataoka, K.
Tsutsui, H. Iwai, “
Evaluation of 2DEG distribution on AlGaN/GaN HEMTs introducing uneven AlGaN layers and its possibility for low-resistive contacts formation”,
The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[676] Poster: Y. Ito, H. Hori, K. Tsutsui, K. Kakushima, H. Wakabayashi, Y. Kataoka, A. Nishiyama,
N. Sugii, K. Natori, H. Iwai, “Schottky barrier height reduction process for silicide/Si interfaces”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[677] Poster: H. Yonezawa, R. Kayanuma, A. Nakajima, S. Nishizawa, H. Ohashi, K. Tsutsui, K.
Kakushima, H. Wakabayashi, H. Iwai, “AlGaN/GaN-based p-channel HFETs with wide-operating temperature”, The Workshop on Future Trend of Nanoelectronics:WIMNACT
39, February 7, 2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology,
Japan
[678] Poster: K. Terayama, A. Nakajima, S. Nishizawa, H. Ohashi, K. Kakushima, H. Wakabayashi,
K. Tsutsui, H. Iwai, “Caluculation of ultimate on-resistance in GaN lateral HFETs using device simulation”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39,
February 7, 2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[679] Poster: S. Man, R. Kayanuma, Y. Takei, T. Takahashi, M. Shimizu, K. Tsutsui, K. Kakushima,
H. Wakabayashi, Y. Kataoka, H. Iwai, “A Study on the Fabrication of GaN-FinFET Using
Selective Area Growth Method”, The Workshop on Future Trend of
Nanoelectronics:WIMNACT 39, February 7, 2014, Suzukake Hall, Suzukakedai Campus,
Tokyo Institute of Technology, Japan
[680] Poster: H. Hori, Y. Ito, K. Tsutsui, K. Kakushima, H. Wakabayashi, Y. Kataoka, A. Nishiyama,
N. Sugii, K. Natori, H. Iwai, “Effects of substrate back bias on solar cells formed on thin SOI structures”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[681] Poster: T. Ohashi, H. Wakabayashi, K. Kakushima, N. Sugii, A. Nishiyama, Y. Kataoka, K.
Natori, K. Tsutsui, H. Iwai, “Performance Prediction on n-MOSFET using Single-Layer MoS2
Channel”, The Workshop on Future Trend of Nanoelectronics:WIMNACT 39, February 7,
2014, Suzukake Hall, Suzukakedai Campus, Tokyo Institute of Technology, Japan
[682] Poster: A. Takemasa, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K.
Tsutsui, K. Natori, H. Iwai, “Electrical characteristics of n-type diamond contacts with Ti, Ni,
NiSi
2
and Ni
3
P electrodes”, China Semiconductor Technology International Conference
(CSTIC) 2014, March 16-17, 2014, Shanghai, China
[683] Keynote Speech: H. Iwai, “Future of Nano CMOS Technology”, ICCDCS, April 2, 2014,
Playa del Carmen, Mexico
62
[684] M. Koyama, M. Casse, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold, “Assessment of
Technological Device Parameters by Low-frequency Noise Investigation in SOI Omega-gate
Nanowire NMOS FETs”, 15 th ULIS Conference, April 9, 2014, Stockholm, Sweden
[685] M. Koyama, M. Casse, R. Coquand, S. Barraud, G. Ghibaudo, H. Iwai, G. Reimbold,
“Influence of Technological and Geometrical Parameters on Low-frequency Noise in SOI
Omega-gate Nanowire MOSFETs”, 2014 International Symposium on VLSI Technology,
Systems and Applications(2014 VLSI-TSA), April 28, 2014, Hsinchu, Taiwan
[686] Y. Takei, M. Okamoto, W. Saito, K. Tsutsui, K. Kakushima, H. Wakabayashi, Y. Kataoka, H.
Iwai, “Ohmic Contact Properties Depending on AlGaN Layer Thickness for AlGaN/GaN High
Electron Mobility Transistor Structures”, ECS 225 th Meeting, ECS Transactions, Vol.61, No.4, pp.265-270, May 14, 2014, Orlando,FL, USA
[687] Poster: A.Nakajima, H. Yonezawa, K. Tsutsui, K. Kakushima, S. Nishizawa, H. Ohashi, H.
Wakabayashi, H. Iwai, “One-chip operation of GaN-based P-channel and N-channel
Heterojunction Field Effect Transistors”, The 26 th International Symposium on Power
Semiconductor Devices and ICs(ISPSD 2014), June 15-19, 2014, Waikoloa, Hawaii, USA
Distinguished Lecture
[1] H.Iwai, “CMOS Scaling beyond 0.1µm”, IEEE EDS Distinguished Lecture Univ. of Florida ,
September, 1997, Gainsville, FL, USA
[2]
H.Iwai, “CMOS scaling below 0.1µm ” IEEE Distinguished Lecture”, IEEE Distinguished
Lecture, January, 1998, Singapore
[3] “CMOS Scaling and its Future towards Downsizing Limit,” IEEE EDS WIMNACT-9, 2005,
Yokohama , Japan, Oct. 2005. pp. 55-66.
[4] “Recent Status an Nano CMOS and Future Direction,” IWNC, Mishima , Japan, Jan. 2006, pp.
2-3.
[5] “Future of CMOS and Its Manufacturing” IEEE LEOS Chapter& EDS Chapter, Jan.3, 2006,
Kolkata, India
[6] “Future CMOS Scaling and Its Manufacturing”, IEEE Mini-Colloquia, Jun. 1, 2006, Naples,
Italy
[7]
“ High Dielectric Constant Gate Insulator Technology”, WIMNACT IEEE Mini-Colloquia
Singapore, Jul. 4 2006, Singapore
[8]
“
Nano-CMOS and Its Manufacturing”, EDS Tsinghua Student Chapter Opening Ceremony,
Jul. 10 2006, Beijing, China
[9] “Miniaturization of Semiconductor Devices for Integrated Circuits” University of Chile,
UTFSM., University of Bio Bio, Nov. 20-24 , Chile
[10] “Electron Devices for Human Society” Inaugural Ceremony of IEEE Electron Devices Society
Bangladesh Chapter, Dec 19, 2006, Dhaka, Bangladesh
[11] "Miniaturization of Semiconductor Devices for Integrated Circuit ” Jan. 3 2007,Bhubaneswar,
India
[12]
“ Past and future of Si integrated circuit technology” Jan. 9, 11 2007,Kashgar Pedagogiical
Institute, Hotan, China
[13]
“ Past and future of Si integrated circuit technology” Jan.11 2007, Hotan Pedagogical College,
Hotan, China
[14]
“
Past and future of Si integrated circuit technology” Jan.16 2007,
Xinjian University,
Urumuqi
, China
63
[15] "Nano-CMOS Technology and Its Beyond" Feb. 5 , 2007 , National Chiao Tung University,
Taiwang
[16] "Nano-CMOS and High-k/metal Gate Technology" Feb.6, 2007, UMC, Taiwang
[17] "Future of Nano CMOS Technology” 、 WIMNACT/MQ 1 & IEDST, June 4, 2007, Tsinghua
University, Beijing, China
[18] “Future Gate Stack Technology” Mini-Colloquium at IBM East Fishkill, Dec. 7, 2007, New
York, USA
[19] “High-k/Metal Gate Technology” Indian Institute of Technology, Bombay , Jan. 9 , 2008,
Bombay, India
[20] Past and Future for Micro-and Nano-Electronics Focusing on Si Integrated Circuits
Technology ” Narula Institute of Technology , Feb. 29, 2008, Kolkata, India
[21] “Roadmap for 22nm Logic CMOS and Beyond” IIT Bombay, Jan. 21, 2009, Bombay, India
[22] “Roadmap for 22nm Logic CMOS and Beyond” Bengal Engineering Science University, Mar.
5 , 2009, Bengal, India
[23] “Downsizing of transistors towards its Limit” Bengal Institute of Technology&Management,
Mar. 6 , 2009, Bengal, India
[24] “Roadmap for 22nm Logic CMOS and Beyond” Heritage Institute of Technology, Mar. 9 ,
2009, Heritage, India
[25] “Technology Scaling and Roadmap for 22nm CMOS and beyond” University College of
Dublin, EDS Mini-Colloquium on Advanced Electron Devices modeling and Technology,
May 1, 2009, Dublin, Ireland
[26] “Past and Future of Integrated Circuits Technology” University of Manchester, May 5, 2009,
Manchester, UK
[27] “Recent Our Activities in Si FET Research” IIT Madras, November 3, 2009, Chennai, India
[28] “Past and future of Micro/Nano-electronics” IEEE EDS Mini Colloquia, November 9, 2009,
Government Engineering College, Port Blair, India
[29] “Si MOSFET Roadmap for 22nm and beyond", December 16, 2009, Jadavpur University,
Kolkata, India
[30] “Future nanoelectronic device technologies - high-k, nanowire and alternative channel”,
January 13, 2010, IEEE AP & ED Joint MQ, IIT Bombay, Bombay, India
[31] H. Iwai, "Beyond the definition of classical devices & communication technology", March 29,
2010, IEEE EDS DL Siliguri Institute of Technology, Siliguri Institute of Technology, Siliguri,
India
[32] H. Iwai, "Si Nanoelectronic Device Technology", April 2, 2010, IEEE EDS WIMNACT 23,
IIT Guwahati, Guwahati, India
[33] H. Iwai, "Si Nanoelectronic Device Technology", April 5, 2010, IEEE EDS WIMNACT 23,
North-Eastern Hill University, Shillong, India
[34] H. Iwai, "Si Nanoelectronic Device Technology", April 8, 2010, IEEE EDS WIMNACT 23,
NIT Silchar, Silchar, India
[35] H. Iwai, "Nanoelectronic Device Technology", April 9, 2010, IEEE EDS WIMNACT 23,
Heritage Institute of Technology, Kolkata, India
[36] H. Iwai, "Past and future of Si integrated circuit device technologies", June 7, 2010,IEEE EDS
Mini Colloquium, Institute for Microelectronics Stuttgart(IMS-CHIPS), Stuttgart, Germany
[37] H. Iwai, “Past and future trends of integrated Circuit Technology”, October 25, 2010, Nano
Devices and Material Technology, Tribhuvan University, Pokhara, Nepal
[38] H. Iwai, “Si Nanowire FET Modeling and Technology”, November 8, 2010, Peking
University IEEE EDS DL Talk, Peking, China
[39] H. Iwai, “Past and Future of Micro/Nano-Electronics”, IEEE EDS MINI-COLLOQUIUM on
“Nanoelectronics”, Gandhi Institute of Technology and Management, December 28, 2010,
Bhubaneshwar, Orissa, India
[40] H. Iwai, “Si Nanowire FET Modeling and Technology”, IEEE EDS MINI-COLLOQUIUM on
“Nanoelectronics”, National Institute of Science and Technology, December 30, 2010,
Berhampur, Orissa, India
[41] H. Iwai, “Short Presentation and Discussion for Future of Micro/Nano-Electronics”, January 8,
2011, SKP Engineering College, India
[42] H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”, April 9, 2011, IEEE EDS DL,
North Eastern Regional Institute of Science and Technology Nirjuli, (Itanagar), Arunachar
Pradesh, India
[43] H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”, April 14, 2011, IEEE EDS DL
64
Seminar , Nanocenter of Calcutta University, Calcutta, India
[44] H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”, April 7, 2011, One day National
Workshop on Electronic Devices, Mizoram University Aizawl, Mizoram, India
[45] H. Iwai, “Future of Si Nano-CMOS Technology”, IEEE EDS MINI-COLLOQUIUM:
WIMNACT 29, National Chiao Tung University, May 27, 2011, Taiwang
[46] H. Iwai, “Future of Nano CMOS Technology”, International Workshop on The Future of Nano
Electronics Research and Challenges Ahead, December 26, 2011, SKP Engineering College,
Tiruvannamalai, Tamilunadu, India
[47] H. Iwai, “Future of Nano CMOS Technology”,WINMACT 30, December 30, 2011, Sri Rama
Krishna Institute, India
[48] H. Iwai, “Future of Nano-CMOS Technology”, WIMNACT Workshop and IEEE EDS
Mini-colloquium on Nanometer CMOS Technology 31, January 30, 2012, Tokyo Institute of
Technology, Japan
[49] H. Iwai, “Nano CMOS and High-k Technology”, IEEE EDS MQ WIMNACT 32
C0-sponsored by EDS Japan Chapter and TIT, February 10, 2012, Tokyo Institute of
Technology, Japan
[50] H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”, IEEE EDS, April 28, 2012,
Institute of Engineering & Management, Kolkata, India
[51] H. Iwai, “Past and Future of Micro/Nano-Electronic Devices”, IEEE EDS, April 30, 2012, NIT
Manipur, Imphal, India
[52] H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm Generation”, Workshop and
IEEE EDS Mini-colloquim on Nanometer CMOS Technology(WIMNACT 35), November 29,
2012, Nanyang Technological University, Singapore
[53] H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm Generation”, Workshop and
IEEE EDS Mini-colloquim on Nanometer CMOS Technology(WIMNACT 36), November 30,
2012, Penang Skills and Development Center, Penang, Malaysia
[54] H. Iwai, “Past and Future of Micro/Nano Electronic Devices”, IEEE Mini Colloquium on The
Future of Nano Electronics, December 27, 2012, Dhanalakshmi Srinivasan Engineering
College, Tiruvannamalai, Tamil Nadu, India
[55] H. Iwai, “High-k/metal gate stack technologies with EOT less than 0.5nm”, IEEE AP/ED
Bombay Chapter, January 24, 2013, IIT Bombay, India
[56] H. Iwai, “CMOS Logic Technology”, IEEE AP/ED Bombay Chapter, January 24, 2013, IIT
Bombay, India
[57] H. Iwai, “Future of nano CMOS Technology”, IEEE EDS, January 9, 2013, VIT University,
Vellore, India
[58] H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS, June 21, 2013, Institute of Electron
Technology, Warsaw, Poland
[59] H. Iwai, “Future of Nano CMOS Technology”, EDS Mini Colloquim, September 9, 2013,
UNICAMP, Campinas, Brazil
[60] H. Iwai, “Future of Nano CMOS Technology”,IEEE EDS, September 24,2013, Institut
Polytechnique de GRENOBLE, France
[61] H. Iwai, “Future of Nano CMOS Technology”,IEEE EDS,October 8, 2013, Institute of
Microelectronics, Chinese Academy of Science (IMECAS), Beijing, China
[62] H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS, WIMNACT 38, December 27,
2013, Thiagarajar College of Engineering, Tamilnadu Madurai, India
[63] H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS, January 20, 2014, IIT Bombay,
Mumbai, India
[64] H. Iwai, “Future of Nano CMOS Technology”, IEEE EDS MQ, May 26, 2014, KTH, Kista,
Stockholm, Sweden
65
Seminar
[1] Distinguished Lecture: H. Iwai “Miniaturization of Semiconductor Devices for Integrated
Circuits” University of Chile, UTFSM., University of Bio Bio, Nov. 20-24 , 2006, Chile
[2] Distinguished Lecture: H. Iwai,
“
Past and future of Si integrated circuit technology” Jan. 9, 11
2007, Kashgar Pedagogical Institute , Kashgar & Hotan Pedagogical College, Hotan, China
[3] Distinguished Lecture: H. Iwai,
“ Past and future of Si integrated circuit technology” Jan.11
2007, Hotan Pedagogical College, Hotan, China
[4] Distinguished Lecture: H. Iwai,
“ Past and future of Si integrated circuit technology” Jan.16
2007,
Xinjian University, Urumuqi
, China
[5] Distinguished Lecture: H. Iwai, "Nano-CMOS Technology and Its Beyond" Feb. 5 , 2007 ,
National Chiao Tung University, Taiwang
[6] Distinguished Lecture: H. Iwai, "Nano-CMOS and High-k/metal Gate Technology" Feb.6,
2007, UMC, Taiwang
[7] Distinguished Lecture: H. Iwai, “High-k/Metal Gate Technology” Indian Institute of
Technology, Bombay , Jan. 9 , 2008, Bombay, India
[8] Distinguished Lecture: H.Iwai, Past and Future for Micro-and Nano-Electronics Focusing on
Si Integrated Circuits Technology ” Narula Institute of Technology , Feb. 29, 2008, Kolkata,
India
[9] Distinguished Lecture: H. Iwai, “Roadmap for 22nm Logic CMOS and Beyond” IIT Bombay,
Jan. 21, 2009, Bombay, India
[10] Distinguished Lecture: H. Iwai, “Roadmap for 22nm Logic CMOS and Beyond” Bengal
Engineering Science University, Mar. 5 , 2009, Bengal, India
[11] Distinguished Lecture: H. Iwai, “Downsizing of transistors towards its Limit” Bengal Institute of Technology&Management, Mar. 6 , 2009, Bengal, India
[12] Distinguished Lecture: H. Iwai, “Roadmap for 22nm Logic CMOS and Beyond” Heritage
Institute of Technology, Mar. 9 , 2009, Heritage, India
[13] Distinguished Lecture: H. Iwai, “Past and Future of Integrated Circuits Technology”
University of Manchester, May 5, 2009, Manchester, UK
[14] Distinguished Lecture: H. Iwai “Recent Our Activities in Si FET Research” IIT Madras,
November 3, 2009, Chennai, India
[15] Distinguished Lecture: H. Iwai “Si MOSFET Roadmap for 22nm and beyond", December 16,
2009, Jadavpur University, Kolkata, India
[16]
H. Iwai “Past and Future of Silicon Electronic Devices", Seminar, December 24, 2009, Xian
Jiaotong University, Xian, China
[17]
H. Iwai “Future nanoelectronic device technologies - high-k, nanowire and alternative channel",
Seminar, December 24, 2009, Xian Jiaotong University, Xian, China
[18]
H. Iwai “Past and Future of Silicon Electronic Devices", Seminar, December 29, 2009,
Northwestern Polytechnical University,Xian, China
[19]
H. Iwai, “Nano-CMOS Technology”, June 1, 2011, Lanzhou Jiaotong University, China
[20] H. Iwai, “Future of Micro/Nano Electronics”, August 12, 2011, University of Science and
Technology China, Hafei, China
[21] H. Iwai, “Future of Micro/Nano Electronics”, August 17, 2011,Xiamen University, Xiamen,
China
[22] Distinguished Lecture: H. Iwai, “Future of Micro/Nano Electronics”, September 19, 2011,
KTH, Kista, Sweden
[23] H. Iwai, “Past and Future of Micro/Nano Electronics”, October 28, 2011, Zijingang Campus,
Zhejiang University, Hangzhou, China
[24] H. Iwai, “Past and Future of Micro/Nano Electronics”, October 28, 2011, Yuquan Campus,
Zhejiang University, Hangzhou, China
[25] H. Iwai, “Past and Future of Micro/Nano Electronics”, October 31, 2011, Zhejiang Technology and Science University, Hangzhou, China
[26] H. Iwai, “Past and Future of Micro/Nano Electronics”, November 2, 2011, Ningbo Institute of
Material Technology and Engineering, Hangzhou, China
[27] H. Iwai, “Evolution of Si CMOS Technologies to Sub-10 nm Generation”, May 16, 2012,
Hangzhou University of Electronic Science and Technology, Hangzhou, China
[28]
H. Iwai, “Past and Future of Micro/Nano Electronic Devices”, July 16, 2012, Beifang
University of Nationality, Yinchuan, China
66
[29] H. Iwai, “Future of Nano CMOS Technology”, October 14, 2013, University of Science and
Technology of China, Hefei, China
[30] H. Iwai, “Future of Nano CMOS Technology”, October 17, 2013, Nanjing University, Nanjing,
China
[31] H. Iwai, “Problems and some solutions for future Nano CMOS Technology”, October 29, 2013,
Stanford University, USA
[32] H. Iwai, “Future of Nano CMOS Technology”, January 2, 2014, IISc Bangalore, India
[33] H. Iwai, “Future of Nano CMOS Technology”, January 3, 2014, IBM SRDC(Semiconductor
Research and Development Center),Bangalore, India
[34] H. Iwai, “Future of Nano-CMOS Technology”, January 20, 2014, URV(Universitat Rovira I
Virgili), Tarragona, Spain
[35] Distinguished Lecture: H. Iwai, “Future of Nano-CMOS Technology”, March 20, 2014,
Zhejiang University, Hangzhou, China
[36] H. Iwai, “Future of Nano-CMOS Technology”, April 7, 2014, INAOE, Puebla, Mexico
[37] H. Iwai, “Future of Nano-CMOS Technology”, April 8, 2014, CINVESTAV, Mexico City,
Mexico
[38] H. Iwai, “New Materials and Structures for Sub-10 nm CMOS Devices”, May 18, 2014, Fudan
[39]
University, Shanghai, China
Books:
[1] H. Iwai, "Hot carreir induced degradation mode in thin gate insulator dual gate MISFETs,”
Edited by W. Eccleston and M. Uren, "Insulating Films on Semiconductors 1991," Adam
Hilger, Bristol, Philadelphia and New York, pp.83-92, 1991
[2] Y.katsumata, T.Ohguro, K.Inoh, E.Morifuji, T.Yoshitomi, H.Kimijima, H.Nii, T.Morimoto,
H.S.Momose, K.Yoshikawa, H.Ishiuchi
and H.Iwai, "CMOS/BiCMOS Technology" in
The VLSI Handbook, Chapter 2, edited by Prof. Wai-Kai Chen, Univ. of Illinois, Chicago,
Illinois, 1999
[3] Y.Unno, H.Iwai, "Future Trend in Large-Scale Integrated Circuit Technologies from an
Industrial Perspective" edited by J.Xu et al. in "Future Trends in Microelectronics, The Road
Ahead", published by John Wiley & Sons, Inc., pg.196, 1999
[4] H. Iwai and S. Ohmi, “Trends and Projections for the Future of Scaling and Future Integration
Trends”, The Computer Engineering Handbook, pp1_1-1_29, February 2002
[5] H. Wong, K. Shiraishi, K. Kakushima, H. Iwai, “High-K Gate Dielectrics” Electronic Device
Architectures for the Nano-CMOS Era, pp.105-140, 2009
[6] H. Iwai, S.M. Sze, Y. Taur, H. Wong, “BASIC ELECTRON DEVICES – Chapter2
MOSFETs”,IEEE Guide to State-of-the-Art Electron Devices, pp.21-36, 2013
Panel Discussions:
[1] Panel Discussion: H.Iwai, M.Hiratani, M.Takayanagi, H.Kitajima, H.Kang, T.Horikawa,
K.Torii, Y.Tsunashima, J.Yugami, S.De Gendt, H.Niimi, M.Fischetti, and R.Chau,
“Development Strategy of Gate Dielectrics: Ultra-thin Oxynitride versus High-k materials”,
IWGI 2003, pp.194, November6-7,2003, Tokyo,
[2] Evening Panel Discussion: J.N.Burghartz, D.Harame, T.Stetzler, H.Iwai, M.Tiebout and
V.Ilderem, “When Will CMOS Replace HBTs for RF?”, p.593, SESSION25, IEDM2003, ,
December8-10,2003, Washington DC, USA,
[3] Evening Discussion Session ME2 : W.J. Dally, J. Emer, F. Fox, W-M. Hwu, H. Iwai, F.
Pollack, and F. Weber, “Where will proessor performance come from in the next ten years?” pp.118-119, Dig. Tech. ISSCC, 2000
[4] Panel Discussion: K.Shimohigashi, K.Kyuma, H.Iwai, K.Asada ,Innovation Japan2007
67
pp19,September12-14, Tokyo
[5] Panel Discussion: H. Iwai, S. Oda, S. Sze, G. Baccarani, N. Sano, T. Kanayama, K. Natori, S.
Deleonibus, T. Hiramoto, C. Claeys, S. Takagi, Y. Miyamoto, W. Milne, K. Banerjee, N.
Koshida, K.Uchida, S. Sugano, K. Kimura, K. Yamada, K. Shiraishi, D-L.,Kwong, S.
Sugawara, “Silicon nano-devices in 2030” , Global COE International Symposium, October 14,
2009, Tokyo
Short Course:
[1] H. Iwai, “Source Drain and Wells,” Short Course A: Sub-100NM CMOS, IEDM Short Course,
December, 1999
[2] H. Iwai, “Advanced Device Technologies,” Key Technology Challenges for sub-70nm VLSI,
Symp. on VLSI Tech., June, 2002
[3] H. Iwai, “High-k Dielectics,” Short Course 1) New process and device concepts, ESSDERC,
September, 2005
[4] H.Iwai,“Technology Scaling and Roadmap,” Short Course: 22nm CMOS Technology,IEDM
2008, December, 2008
[5] H. Iwai, B. de Salvo, “Scaling and Beyond for Logic and Memories. Which perspectives?”,
ISCDG 2012, Short Course, September 26, 2012
Others:
[1] H. Iwai “Transistor Level Modeling for Analog/RF IC Design” 2006 Springer
[2] H. Iwai and W. Maszara, “Advanced materials and IC process technologies,” Proc. of the
Ninth International Symposium on Silicon Material Science and Technology, Semiconductor
Silicon 2002, pp. 325-327
[3] H. Iwai “IEEE Division I Activities in R10” IEEE AdCom Meeting, May 29, 2011, Taiwan
[4] H. Iwai “Green by/on Nano CMOS Technology “ Ambassador’s Residence, Embassy of
Switzerland, Tokyo, February 15, 2012
68