EE 448
Final project report
Changwen Hsieh
USC ID : 8503883891
I. Table of Performance :
Parameter Description
Required
First design
simulation
First design
hand calculation
Final design
simulation
Final design
hand calculation
Power Supply (nVdd)
2.5 V
2.5 V
2.5 V
2.5 V
2.5 V
Transimpedance (dBΩ)
> 60 dB
60.2 dB
65 dB
60.2 dB
64.7 dB
Bandwidth (W-3dB):
> 2.5 GHz
2.68 GHz
273 MHz
2.54 GHz
1.6 ~ 6 GHz
Total Equivalent Input Noise
Current(from DC to 2.5 GHz)
< 1 uA
0.9 uA
1.98 uA
0.96 uA
0.584 uA
Total Power Dissipation
< 50 mW
28.5 mW
28.5 mW
13.1 mW
13.1 mW
Gain-bandwidth product
2.5*10^(12)
2.74*10^(12)
4.85*10^(11)
2.6*10^(12)
2.75*10^(12) ~
1.03*10^(13)
Total capacitor
<= 20 pF
II. Schematic :
First design :
20 pF
20 pF
2.5 pF
2.5 pF
Final design:
Introduction to the project:
Design a TIA ( Transimpedance Amplifier) using 0.25 um CMOS process technology
with following specifications and constraints:
III. TIA design and simulations of original design
a. design strategy & Hand Calculation:
The strategy of my original design has 3 stages. I use the structure connecting two
transistors together at first stage because I found out that this structure has zeros and I
could build a 55dB and W-3db= 2.7GHz stage by using this structure. For high gain
and wide bandwidth, transistor M1 should be larger and M2 should be smaller
because 1/(gm2+gmb2) is small and it can decrease time constant at the node of gate
of M1. However, there is no such advantage of Cgd2. If we choose large size of M2,
time constant at the node of drain of M2 would be large. Therefore, M2 should be
chosen as small size.
Schematic of first stage:
Simulation result of first stage (without feedback):
Gain = 58.8 dB, BW-3dB= 2.66 GHz
At second stage, I use a cascode with feedback to increase some gain and make sure
bandwidth is still large enough. It should be notice that the value of Rf is larger, gain
is larger but bandwidth would be smaller, vice versa.
Schematic of second stage:
However, gain is still not enough. Therefore, I use a simple common source amplifier
and followed by a common drain (buffer) as my last stage. For the common source
amplifier, I do not use cascade because the gain here is not large. If I use cascade,
total capacitor would be larger than simple common source.
Schematic of third stage:
b. A print-out of the HSPICE netlist. (Changwen_Hsieh.lib)
* Design Team Members: Changwen Hsieh
* Design Specifications: single-ended, AC-coupled
.SUBCKT
TIA nIin nVout
*1st stage
Cbig nIin s3 13pF
M1 d1 ng1 nGND
R1
nvdd
M2 d2
R2
d1
nVdd
nGND
d1
ng1
nvdd
nGND
CMOSN W=80u L=0.25u
1.9k
nGND
d2
CMOSN W=10u L=0.25u
1k
M3 ng1
g3
s3
nGND CMOSN W=70u L=0.25u
RB1
nvdd
g3
16k
RB2
g3
nGND
9k
C3 g3
nGND
3p
*bias
M41
g4
M42
*I4
R41
C4
s3
nvdd
nvdd
g4
g4
nGND
nGND
CMOSN
W=50u L=0.25u
g4
nGND nGND
g4 1m
g4
1.828k
nvdd
1p
CMOSN
W=63u L=0.25u
*2nd stage
M5
nvdd
R5
s5
d2
nGND
M6
R7
d6
nvdd
s5
d7
nGND
2k
M7
RB71
RB72
C7
d7
nvdd
g7
g7
g7
g7
nGnd
nGnd
d6
10k
15k
3p
s5
nGND
CMOSN W=25u L=0.25u
3k
nGND CMOSN
nGnd
W=30u L=0.25u
CMOSN W=8u
L=0.25u
*feedback
Rf
d7
d2
5k
*3rd stage
M8
d8
R8
nvdd
d7
d8
nGND
0.8k
M10 nvdd
R10
d8 nvout
nvout
nGND
nGND CMOSN
nGND 5k
.ENDS
c. A print-out of the HSPICE output file
CMOSN
W=32u
W=8u L=0.25u
L=0.25u
d. An HSPICE print-out of small-signal gain magnitude versus frequency.
BW-3db = 2.68GHz
e. An HSPICE print-out of the output and input transient analysis
(334-323)*10^(-3) / 10*10^(-6) = 1100
20 * Log(1100) = 60.8 dBΩ
Run more periods to make sure it’s stable
f. An HSPICE print-out of the noise analysis
1 ****** HSPICE --- Y-2006.09 32-BIT (Aug 25 2006) 15:51:45 11/30/2010
solari
******
* test bench for tia design
****** noise analysis
******
tnom= 25.000 temp=
25.000
frequency = 2.5119g
hz
**** resistor squared noise voltages (sq v/hz)
element
rs
1/f
0:rload
3.778e-19
0.
1:r1
3.3362a
0.
1:r2
17.7042a
0.
1:rb1
1.504e-20
0.
1:rb2
2.674e-20
0.
total
rx
3.778e-19
33.8723
3.3362a
620.4662
17.7042a
1.0369k
1.504e-20
120.8980
2.674e-20
120.8980
element
rs
1/f
total
rx
1:r41
7.851e-19
0.
.851e-19
295.2389
1:r5
2.1137a
0.
2.1137a
620.5859
1:rb71
8.902e-23
0.
8.902e-23
7.3528
1:rb72
5.934e-23
0.
5.934e-23
7.3528
1:r7
2.1291a
0.
2.1291a
508.5386
element
rs
1:rf
4.5995a
1:r8
5.913e-19
1:r10
3.778e-21
1/f
total
rx
0.
4.5995a
1.1818k
0.
5.913e-19
169.4922
0.
3.778e-21
33.8723
**** mosfet squared noise voltages (sq v/hz)
element
rd
rs
id
1:m1
0.
0.
35.0618a
1:m2
0.
0.
22.0276a
1:m3
0.
0.
92.3355a
1:m41
0.
0.
9.4684a
1:m42
0.
0.
77.3891a
rx
fn
total
620.4662
0.
35.0618a
775.9948
0.
22.0276a
854.8858
0.
92.3355a
295.2389
0.
9.4684a
808.6018
0.
77.3891a
element
rd
rs
id
rx
fn
1:m5
0.
0.
14.8348a
620.5859
0.
1:m6
0.
0.
11.2883a
397.3669
0.
1:m7
0.
0.
1.2665a
207.8621
0.
1:m8
0.
0.
9.084e-19
169.4922
0.
1:m10
0.
0.
1.563e-19
33.8723
0.
total
14.8348a
11.2883a
1.2665a
9.084e-19
1.563e-19
**** total output noise voltage
transfer function value:
v(nrl)/iin
equivalent input noise at iin
= 296.4193a
sq v/hz
= 17.2168n
v/rt hz
= 778.6537
= 22.1110p
/rt hz
**** the results of the sqrt of integral (v**2 / freq)
from fstart upto
2.5119g
hz. using more freq points
results in more accurate total noise values.
**** total output noise voltage
= 852.1204u
**** total equivalent input noise =
volts
906.2795n
IV. TIA design and simulations of final design
a. design strategy & Hand Calculation:
After presentation, I follow professor’s advice, fix my original design and redo the
hand calculation.
The strategy of my final design has 3 stages. In the first stage, I still use the same
structure as my original one because this structure has zeros and it could increase
bandwidth. I substitute the Ibias to a resister Rb and I reduce M1’s size because the
total capacitance at the node would decrease, and then it would decrease time constant
and increase bandwidth.
In hand calculation, there are three zeros, two are complex conjugate at 7.84*10^9 +
i*5.56*10^10 (rad/s) and one zeros is at 978MHz. And there are two poles at 800
MHz and 239 GHz.
Gain = 63 dB, BW-3dB= 2.9 GHz. Slope is -60dB/dec. There are 3
poles at 2.9GHz
I connect the output of the first stage to a buffer and then connect to the second stage.
I followed professor’s advice to take out the feedback. I use a common source with
degeneration and add a capacitor parallel with the degeneration resistor. I use this
structure because it would create two zeros through this structure and increase
bandwidth.
And then I connect the output of this stage to a buffer.
In hand calculation, there are two zeros at this topology. + 557 MHz.
And there are two complex conjugate poles at 6 GHz.
At last stage (3rd stage), I use the same topology as 2ns stage, and connect a buffer to
the output.
In hand calculation, there are two zeros at this topology. One is at 64 GHz and another
one is at 1.6GHz. And there are two poles at 414 MHz and 10 GHz.
b. A print-out of the HSPICE netlist. (Changwen_Hsieh.lib)
.SUBCKT
TIA nIin nVout
nVdd
nGND
*1st stage
M1
d1
R1
nvdd
M2
d2
R2
nvdd
Rb
nIin
nIin
d1
d1
d2
ngnd
nGND
2.5k
nIin
1.5k
1k
*buffer
M3
nvdd
d2
s3
R3
s3
nGND
2k
nGND
nGND
nGND
CMOSN W=20u L=0.25u
CMOSN W=10u L=0.25u
CMOSN W=10u L=0.25u
*2nd stage
M4
Rs4
C4
R4
d4
s4
s4
nvdd
*buffer
M5
nvdd
d4
R5
s5
nGND
*3rd stage
M6
d6
R6
nvdd
Rs6
s6
C6
s6
s3
nGND
nGND
d4
s5
d6
ngnd
nGND
s4
150
1.5p
1.2k
s5
nGND CMOSN
W=30u L=0.25u
nGND
CMOSN W=10u L=0.25u
nGND
CMOSN
W=30u
L=0.25u
nGND
CMOSN
W=34u
L=0.25u
2k
s6
0.6k
100
1p
*buffer
M7
R7
.ENDS
nvdd
nvout
d6
nvout
nGND
0.5k
c. A print-out of the HSPICE output file
d. An HSPICE print-out of small-signal gain magnitude versus frequency.
Gain = 60.2 dB, BW-3dB= 2.54 GHz. Slope is -100dB/dec. There are 5
poles at 2.9GHz
e. An HSPICE print-out of the output and input transient analysis
(-43.4)*10^(-6)+(10.1)*10^(-3) / 10*10^(-6) = 1005.66
20 * Log(1100) = 60.05 dBΩ
Run more periods to make sure it’s stable
f. An HSPICE print-out of the noise analysis
****** HSPICE --- Y-2006.09 32-BIT (Aug 25 2006) 22:43:55 12/05/2010
solari
******
* test bench for tia design
****** noise analysis
tnom= 25.000 temp= 25.000
******
frequency =
2.5119g
hz
**** resistor squared noise voltages (sq v/hz)
element
0:rload
rs 3.818e-19
1/f
0.
total 3.818e-19
rx
34.0486
element
1:rs4
rs 1.936e-19
1/f
0.
total 1.936e-19
rx
41.9942
1:r1
19.7231a
0.
19.7231a
1.7305k
1:r4
6.072e-19
0.
6.072e-19
210.3727
1:r2
4.2349a
0.
4.2349a
1:rb
9.2408a
0.
9.2408a
1:r3
8.739e-19
0.
8.739e-19
621.1321
749.1538
325.8104
1:r5
1.924e-19
0.
1.924e-19
152.8923
1:r6
2.146e-19
0.
2.146e-19
88.4218
1:rs6
1.428e-19
0.
1.428e-19
29.4541
element
1:r7
rs 3.818e-20
1/f
0.
total 3.818e-20
rx
34.0486
**** mosfet squared noise voltages (sq v/hz)
element
1:m1
rd
0.
rs
0.
id 127.1958a
1:m2
0.
0.
17.4385a
rx
1.7305k
fn
0.
total 127.1958a
736.0214
0.
17.4385a
element
1:m6
rd
0.
rs
0.
id 5.137e-19
rx
75.2066
fn
0.
total 5.137e-19
1:m7
0.
0.
1.159e-19
34.0486
0.
1.159e-19
**** total output noise voltage
transfer function value:
v(nrl)/iin
equivalent input noise at iin
1:m3
0.
0.
2.8980a
1:m4
1:m5
0.
0.
2.6586a
0.
0.
6.963e-19
325.8104
0.
2.8980a
206.8018
0.
2.6586a
152.8923
0.
6.963e-19
= 187.3603a
sq v/hz
= 13.6880n
v/rt hz
= 749.1538
= 18.2712p
/rt hz
**** the results of the sqrt of integral (v**2 / freq)
from fstart upto
2.5119g
hz. using more freq points
results in more accurate total noise values.
**** total output noise voltage
= 679.1134u
**** total equivalent input noise =
volts
584.0632n
V. Discussions
a. Agreement or discrepancy between hand analysis, and simulations of first
design
Comparison between hand calculation and simulation
The result between hand calculation and simulation has some discrepancy of
bandwidth and noise analysis.
In my hand calculation, bandwidth is 273 MHz. However, it’s 2.68 GHz in simulation.
The reason could be the pole in first stage because pole in first stage is major pole. In
the first stage there should be 2 zero eliminating effects of poles. Therefore, I could
get a 58.8 dB with BW = 2.66 GHz of the first stage in simulation. However, in hand
calculation, zeros are at 15.9 GHz and 97.3 GHz while poles are at 488 MHz and
10.4GHz.
For this original design, I believe that I do the wrong hand of bandwidth calculation of
stage 1 because I did not include Cin in the calculation. This is the main reason of
discrepancy of first design.
For gain part, the value in hand calculation is 65 dB and it’s 60.2 dB in simulation.
For noise part, the value of noise in hand calculation is 1.98 uA and it’s 0.9 uA in
simulation.
The reason for these two parts could be that I use approximation in my hand
calculation, that is, I ignore some second order effect in hand calculation. It affects
those results.
Result of only first stage: (without feedback)
Gain = 58.8 dB, BW-3dB = 2.68 GHz
b. Agreement or discrepancy between hand analysis, and simulations of final
design
Comparison between hand calculation and simulation
The result between hand calculation and simulation has some discrepancy of
bandwidth and noise analysis and little discrepancy of gain.
In my hand calculation, bandwidth is in the middle of 1.6 GHz to 6 GHz, and it’s 2.5
GHz in simulation. The reason could be that I ignore some parallel capacitance in
hand calculation.
For noise part, the value of noise in hand calculation is 0.96 uA and it’s 0.584 uA in
simulation. The reason could be that I ignore the ro and second order effect in hand
calculation.
More, for gain part, the value in hand calculation is 64.7 dB and it’s 60.2 dB in
simulation. The reason could be the same as the noise part; I ignore ro and second
order effect in hand calculation.