WYV55
A Low Power Fault Tolerant Reversible Decoder Using MOS
Transistor
Shamsujjoha,M.
VLSI Design and 2013 12th International Conference on Embedded Systems (VLSID), 2013
26th International Conference on
DOI:10.1109/VLSID.2013.216
Publication Year: 2013 Page(s):368 – 373
Project Title
Domain
: ALow power Fault Tolerant Reversible Decoder Using MOS Transistor
: VLSI
Reference
: IEEE
Publish Year
: 5-10 Jan. 2013 Page(s):368 – 373
D.O.I
: 10.1109/VLSID.2013.216
Software Tool
: XILINX
Language
Developed By
: Verilog HDL
: Wine Yard Technologies, Hyderabad
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WYV55
A Low Power Fault Tolerant Reversible Decoder Using MOS
Transistor
Abstract:
This paper demonstrates the reversible logic synthesis for the n-to-2ndecoder, where n is
the number of data bits. The circuits are designed using only reversible fault tolerant
Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault
tolerant. Algorithm for designing the generalized decoder has been presented. In addition,
several lower bounds on the number of constant inputs, garbage outputs and quantum cost
of the reversible fault tolerant decoder have been proposed. Transistor simulations of the
proposed decoder are shown using standard p-MOS 901 and n-MOS 902 model with delay
of 0.030 ns and 0.12 μm channel length, which proved the functional correctness of the
proposed circuits. The comparative results show that the proposed design is much better in
terms of quantum cost, delay, hardware complexity and has significantly better scalability
than the existing approach.
Index Terms—Decoder, Delay, Garbage Output, Low Power Design, Quantum Cost,
Reversible & Fault Tolerant Computing
Existing method:
The decoders like of 2:4 and 3:8 decoders are designed by using conventional gates like
and, not, xor etc. using the Boolean expressions.
Proposed method:
The development in the field of nanometer technology leads to minimize the power
consumption of logic circuits. Reversible logic design has been one of the promising
technologies gaining greater interest due to less dissipation of heat and low power
consumption. In the digital design, the decoder is a widely used process. So, the reversible
logic gates and reversible circuits for realizing decoders like of 2:4 reversible decoder using
reversible logic gates is proposed. The proposed design leads to the reduction of power
consumption compared with conventional logic circuits.
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WYV55
Applications:
1. Digital systems designing
2. Digital signal processing
3. Communication
4. Computer graphics
5. Cryptography applications
Advantageous:
1. Area Efficient circuits.
2. Low power Circuits
Conclusion:
we presented the design methodologies of an n-to-2n reversible fault tolerant decoder,
where n is the number of data bits. We proposed several lower bounds on the numbers of
garbage outputs, constant inputs and quantum cost and proved that the proposed circuit
has constructed with the optimum garbage outputs, constant inputs and quantum cost. In
addition, we presented the designs of the individual gates of the decoder using MOS
transistors in order to implement the circuit of the decoder with transistors. Simulations of
the transistor implementation of the decoder showed that the proposed fault tolerant
decoder works correctly. The comparative results proved that the proposed designs perform
better than its counterpart. We also proved the efficiency and supremacy of the proposed
scheme with several theoretical explanations. Proposed reversible fault tolerant decoders
can be used in parallel circuits, multiple-symbol differential detection , network components
and in digital signal processing etc.
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WYV55
Circuit Diagram:
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Screen shots:
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