MDA06-031
TITLE: Advanced Signal Processing Technologies for BMDS Radars
TECHNOLOGY AREAS: Information Systems, Ground/Sea Vehicles, Sensors, Electronics
ACQUISITION PROGRAM: AS(DV) / TE(DT) / AB(DFA) / GM(DFG) / MP(DFP)
OBJECTIVE: The MDA is seeking novel, innovative, and manufacturable high performance signal
processing components, algorithms, software, and sub-systems supporting advanced radar systems.
DESCRIPTION: The requirements of ballistic missile defense drive radar system design in terms of
sensitivity, bandwidth, polarization and time occupancy. Future systems are expected to achieve
significantly greater flexibility and capabilities in part through increasing levels of digitization. Future
systems are expected to support high time-bandwidth product pulse compression waveforms. In
combination, these techniques exceed the capabilities of existing processors. Technologies and concepts are
desired which support the high-throughput, lowpower signal processing in a cost-effective implementation.
The concepts must have well defined open interfaces that readily support scaling and upgrades. Digital
hardware, software, and photonic-based technologies are of equal interest. The threats envisioned for the
near- and farterm are a challenging mixture of countermeasures that will require novel approaches to the
discrimination problem. This topic is focused on technologies to defeat evolving threats (to include
advanced Electronic Counter Measures (ECM), while operating in a nuclear environment, by developing
technologies that support improved performance capability, supportability, reliability, availability, and
system survivability. Methods for mitigating in-band Electro-Magnetic Inference including detection and
pulse repair that reduce the impact on range and Doppler sidelobe levels are desired. The focus on the
advanced signal processing topic is postbeamformer up to, but not including, discrimination.
Technical areas of interest include, but are not limited to:
Advanced Signal Processor hardware technologies. The hardware needs to support wide instantaneous
bandwidth waveforms with any pulse coding, e.g., pseudorandom noise (PRN), polyphase, chaotic, nonlinear FM, etc. for all-range processing. The functions of the processor will include pulse compression,
EMI detection and mitigation, numerous range walks that include accelerating hypotheses, countering
advanced ECM, Doppler processing, CFAR detection and feature extraction. The goal of this focus is a
50% improvement in radar processing throughput and a 50% reduction in life-cycle costs for the Radar
backend electronics. Candidates for this hardware include, but are not limited to quantum processing,
optical processing, FPGAs, and consumer-off-the-shelf boards.
Advanced Signal Processing algorithms. Algorithms are desired that improve the performance of the signal
processor and are robust in severe EMI and ECM environments. The goals of these algorithms should be
very low sidelobe levels while maintaining high resolution, detection of boosting/accelerating missiles,
minimal losses through optimal processing, and minimal performance degradation in a severe in-band EMI
and ECM environments. Advanced algorithms may include time-frequency and STAP algorithms as
applied to above signal processing functions and feature extraction.
UHF Ionosphere Scintillation Mitigation Algorithms. Based on the collected radar data corrupted by the
ionosphere scintillations, develop practical techniques and algorithms to mitigate the scintillation-induced
adverse effects. Use advanced signal processing techniques to retrieve the uncorrupted backscattered radar
signal or remove the scintillation/multi-path undesirable components either in the time or frequency
domain. In addition, develop algorithms to generate simulated realistic scintillation data for performance
testing of deployed EWR/UEWR detection, tracking and object classification algorithms. Demonstrate the
effectiveness of the developed techniques and algorithms by processing and/or simulating the scintillated
radar data under various ionosphere scintillation levels.
PHASE I: Develop and demonstrate the feasibility of the proposed technology or sub-system that address
the specific needs identified in this topic. Demonstrations can be through hardware or models and
simulations.
PHASE II: Refine architecture or technology developed in Phase I. Evaluate/demonstrate the Phase I
technologies in a laboratory environment to show the enhanced capabilities resulting from the utilization of
these unique technologies.
PHASE III: Demonstrate the new radar product(s) via operation as part of a complete system or operation
in a system-level test bed. This demonstration should show near-term application to one or more MDA
element systems, subsystems, or components. Partnership with traditional DoD prime contractors will be
pursued since the Government applications will receive immediate benefit from a successful program.
PRIVATE SECTOR COMMERCIAL POTENTIAL: The commercial application of high throughput
signal processing components and systems will support medical imaging, oil exploration, and
communications systems.
REFERENCES:
1. Report of the American Physical Society Study Group on Boost-Phase Intercept Systems for National
Missile Defense: Scientific and Technical Issues (Washington, D.C.: American Physical Society, July
2003), available at www.aps.org/public_affairs/popa/reports/nmd03.cfm.
2. Alternatives for Boost-Phase Missile Defense, (Washington, D.C.: Congressional Budget Office, July
2004), available at http://www.cbo.gov/ftpdocs/56xx/doc5679/07-22-MissileDefense.pdf.
3. R. G. Seed, A.S. Fletcher, and F.C. Robey, “STRAAP: space-time-radiating array adaptive processing,”
Phased Array Systems and Technology, 2003. IEEE International Symposium on, 14-17 Oct. 2003 Pages:
136 - 141.
4. M. Skolnik, “Radar Handbook”, McGraw-Hill, 1990.
5. Andraka, R. and Berkun, A., “FPGAs Make a Radar Signal Processor on a Chip a Reality”, Proceedings
of the 33rd Asilomar Conference on Signals, Systems and Computers, October 24-27, 1999, Monterey, CA.
6. Walke, R.L.; Smith, R.W.M.; Lightbody, G., “Architectures for adaptive weight calculation on ASIC and
FPGA “, Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar
Conference, Volume: 2 , 1999, pp. 1375 -1380 vol. 2.
7. Chung-Yao Chang; Shiunn-Jang Chern, “Adaptive linearly constrained inverse QRD-RLS beamformer
for multiple jammers suppression”, Wireless Communications, 2001. (SPAWC '01).
2001 IEEE Third Workshop on Signal Processing Advances, 2001, pp. 294 –297.
8. Song, W.S.; Baranoski, E.J.; Martinez, “One trillion operations per second on-board VLSI signal
processor for Discoverer II space based radar”, D.R.,Aerospace Conference Proceedings, 2000 IEEE ,
Volume: 5 , 2000 Page(s): 213 -218 vol. 5.
9. Andraka, R. and Berkun, A., “FPGAs Make a Radar Signal Processor on a Chip a Reality”, Proceedings
of the 33rd Asilomar Conference on Signals, Systems and Computers, October 24-27, 1999, Monterey, CA.
KEYWORDS: STAP, Time-Frequency, spatio-temporal coding, phased array, open systems, signal
processing, adaptive processing, FPGA, optical processing, EMI, countermeasures, radar, algorithms,
scintillation