Charles M Zukowski II
7790 Fargo Drive,
Colorado Springs, Colorado 80920
(719) 213-4250
Zukowski Inc.
czmaskdesign@yahoo.com
PRINCIPLE IC MASK DESIGN ENGINEER
With over 26 years experience in microchip design, I’ve obtained the necessary expertise in methodologies and procedures to
insure successful project completions without delays. Efficient in Analog, RF and Mix Signal layout design techniques, I’ve
worked on the many different stages of chip design from initial floor planning, to bonding diagram design, to top level connection.
I pride myself in the quality of my work and insure proper communication not only between me and the design engineers but also
with other departments associated with the project. Please review this abbreviated resume to quickly familiarize yourself with my
career. Let me help your company achieve the goals you constantly strive for. (A more detailed resume is available upon request.)
EXPERIENCE (Contracts)
* 12/10 - Pres Aeroflex Inc. Colorado Springs, CO.
Mix Signal ASIC’s, TSMC CMOS 90nm/130nm DOD RAD Hard design standard cell library and ESD Pad design.
* 09/10 - 12/10 EM Micro Electronics:
Analog .35um 4 metal process, centroid matching, block floor plan, top level interconnect.
* 05/09 -07/10 Aeroflex Inc, Colorado Springs, CO.
Mix Signal ASIC’s, TSMC CMOS .13um DOD RAD Hard design standard cell library and ESD Custom Pad devices
using Cadence Virtuoso Assura DRC V2.a and Mentor’s Calibre DRC/LVS v9.3_1.1.
* 10/06 - 04/09 Agilent Inc., Colorado Springs, CO.
Mix Signal/Analog Design; 65nm CMOS, BICMOS9 SiGe-C Bipolar 0.3um HCM0S9, TSMC 0.25um Salicide,
TSMC 90g, BICMOS7RF, using Virtuoso 5.10.41 to 6.1.2, XL/ DRC/LVS/VCAR, Virtuoso Chip Assembly Router.
* 06/06 - 10/06 Hitite Inc, Colorado Springs, CO.
Mix Signal/Analog Design CMOS TSMC 0.25, Six Metal Mix Signal using Virtuoso XL/Assura DRC and LVS.
* 02/06 - 06/06 Agilent Inc., Colorado Springs, CO.
Analog Mask Design Bi-CMOS Analog Five Metal Mix Signal using Cadence Virtuoso XL/DRC and LVS.
* 09/05 - 02/06 DSP Group, Colorado Springs, CO.
Analog Design CMOS TSMC 0.18, Seven Metal Mix Signal using Virtuoso XL/Assura DRC and LVS.
Designed LNA's, PLL's, Op-Amps, Latch's, Dividers, Power Converters, and Routing Blocks.
* 07/05 - 09/05 Intel Inc., Colorado Springs, CO.
Mix Signal Design CMOS 60nm, Eight Metal Process using Virtuoso, building Custom ESD Bond Pads.
* 05/05 - 07/05 Solarflare Communications, Irvine, CA.
Analog Mask Design CMOS 0.13 micron, Eight Metal Process using Virtuoso XL with Calibre DRC and LVS.
Mix Signal/Semi Custom RF Design, Linear and Common Centroid Matching, Op Amps and Regulators.
* 11/04 - 05/05 Motorola, Ft Lauderdale, FL.
Mix Signal Mask Design CMOS 90nm, Six Metal Process using Virtuoso XL, Assura DRC/LVS, and Calibre DRC.
Analog Methodologies, Matching Bias Circuits, Mix Signal Amps and Base Band filters.
* 08/04 - 11/04 RF Micro Devices, BroomField, CO.
Analog Mask Design 0.13 Micron Six Layer Metal Salicide, Layouts using Cadence Virtuoso XL w/Assura.
Mix Signal Design 0.13 Micron 8 Metal Dual Voltage P-Sub, High Frequency Cell Matching.
* 03/04 - 07/04 Atmel Corporation, Colorado Springs, CO.
Analog/Mix Signal Mask Design 0.18 Micron Four Layer Metal, Mixers, Latches, Buffers for Test Chip.
Analog/Mix Signal Design 0.35 Micron Four Layer Metal SiGe HBT NPN Bipolar BiCMOS for Test Device.
* 08/03 - 03/04 Moonlight Silicon, Monarch Beach, CA.
(Part Time) IC Mask Design using PC MAGIC, 0.25 Three Layer Metal Mix Signal CMOS.
* 06/02 - 07/03 Atmel Corporation, Colorado Springs, CO.
Lead Mask Design Supervisor Coordinating Project Blocks and Cells to Layout Personnel.
Analog Layout, Mixed Signal Design, using Cadence DIVA, Dracula and Hercules Verifications.
0.18 Micron Four Layer Metal Double POLY Design, Experienced in ESD, Signal Match and Latch-up.
Charles M Zukowski II
7790 Fargo Drive,
Colorado Springs, Colorado 80920 (719) 213-4250
PRINCIPLE IC MASK DESIGN ENGINEER
EXPERIENCE (Salary Positions)
* 12/00 - 06/02 LSI Logic Corporation, Colorado Springs, CO., Physical Design Engineer
Lead Project Engineer for LSI Customer Base Products Cycling Through their Physical Design Division.
Back-end digital chip design with Avant! Tools, floor planning, power rail and power mesh designs.
Clock Tree Synthesis, Global and Detail Routing, DRC/LVS on Various Design Processes.
* 09/98 - 12/00 Atmel Corporation, Colorado Springs, CO., Senior Layout Design Engineer
Lead Project Layout Design on Multiple Atmel Products using multiple Design Processes.
Analog and Custom layout design using Cadence Tools, with Chip Floor Planning and Block Placements.
Power Rail Placement, Global and Detail Routing, and Various Types of Circuit Verifications.
* 05/96 - 09/98 Western Digital, Irvine CA., Senior Layout Design Engineer
Primary Layout Coordinator, Managed Project Status for all Layout Contractors within Engineering.
Analog Layout, Block Verifications using Cadence DIVA/DRACULA LVS, and DRC.
0.24 Micron Three Layer Metal Design, Experienced in ESD Layout, Signal Match and Latch-up.
* 04/95 - 05/96 New Media Corporation, Irvine, CA. (Closed), Engineering Manager
Manager of Document Control, Engineering Interface and Manufacturing Vendor Technical Support.
Responsible for Design and Control of all Engineering Product Documentation and PCB Design.
Structured Engineering Policies, Procedures, Archiving, and ISO 9000 Company Coordinator.
* 1992 - 04/95 Rockwell International, Newport Beach, CA., Senior Layout Design Engineer
Layout on Semi-Custom Designs using VTI Tools, Chip Shrinks, Scribes Designs, Various Verifications.
Project Administrator, COT’s, Track Manufacturing Designs and Sister Division Prototype Releases.
Project Manager for a Device Lead Frame Editor and IC Package Development System.
* 1984 – 1992 Rockwell International, Semiconductor Div., Newport Beach, CA., Layout Design Engineer
Custom and Standard Cell Layout Design, Gate Array Design, and Manufacturing support services.
Cell Design, Schematic Capture, Redesign Layouts for Die Size Optimization, and Performance Yield.
IC layout and Circuit Verification, Developed Cells for Standard Cell Library for VTI, (Compass)
EDUCATIONAL BACKGROUND
* Bachelor of Business Administration, National University, Irvine, CA.
* Achievement in Electronics Tech. Certification, Orange Coast College, Costa Mesa, CA.
* Certificate, Engineering Documentation Control Course – University of Milwaukee, Wisconsin
* Associate in Arts Degree, Orange Coast College, Costa Mesa, CA.
SOFTWARE EXPERIENCE
* Proficient with Cadence Virtuoso using Layout XL and Assura’s Physical Verification Tools.
* Experienced in Mentor’s Calibre DRC and LVs, VCAR, and knowledgeable with Dracula, and AutoCAD.
* Experienced in Multiple UNIX and PC based tools, HTML, as well as Word Processing Tools.
HIGHLIGHTS of ADVANCED TRAINING
* “VTI /VLSI Layout Design Training Courses” - VLSI Technologies Inc., San Jose, CA.
* “Cadence Virtuoso and PCell Training Courses” - Cadence Technologies, San Jose, CA.
* “Mentor's Calibre DRC/LVS Training Courses” - Austin, Texas
* “Cross Functional Leadership Training Course” - Pfeiffer & Company, Newport Beach, CA.
* “Business Communication Skills Speaking Course” - Barbara Rocha and Associates, CA.
* “Colorado POST Certified” “Confidential and Secret Security Clearance” - Expired