How To : Assura Verification with
UMC 0.18µ Design Kit
Stéphane Badel
Microelectronic Systems Laboratory
January 13, 2004
Step I
Configuring the Technology
You’ll have to do this only once. Make sure you have configured your cadence directory by running
umc setup -p logic18 -t cadence ic
Also, make sure you have set cadence assura in the tools section of your .cshrc file.
Step II
Activating and Configuring Assura
In the Layout Editor, select Tools→Assura from the menu. This will activate the Assura menu at
the right of the menu bar.
Next, select Technology. . . from the Assura menu. Enter ./assura tech.lib in the Technology File
field.
Step III
Running DRC
Select Run DRC. . . from the Assura menu. Fill the form :
Select your design here.
This field should be
automatically filled with
the current design.
Select a run directory
here, where all the
assura files for this
run will be created.
Select UMC18_LOGIC
technology and select
rule set.
Set switches here.
Some parameters can
be changed here.
1
Running DRC
If an error occurred and the DRC could not be completed, an error message will be displayed and
informations will be available from the CIW.
If the run is successful and there is no DRC errors, the message “No DRC Errors Found” appears.
Otherwise, Assura places error markers on the layout and the Error Layer Window will appear.
Use the ↑ and ↓ to step through the different error layers, then use ← and → to step through each
marker in the selected layer. This will automatically zoom to the markers.
Rule sets
default
for regular DRC, LVS and RCX
drc esd
for ESD rules verification (DRC only)
drc antenna
for antenna rules verification (DRC only)
Switches
Technology Switches
metal2 is top
Specifies 2-Metal Technology
metal3 is top
Specifies 3-Metal Technology
metal4 is top
Specifies 4-Metal Technology
metal5 is top
Specifies 5-Metal Technology
Chip-Level Switches
SR
Seal ring rules are checked
Run-Time Intensive Switches
check density
Metal coverage rules are checked
check slots
Slot rules are checked
Useful DRC avParameters
?ignoreCell
Defines the list of layout cells (and only layout cells)
that you do not want Assura to analyze, including
dependents of these cells
?joinPins
Specifies under what conditions virtual connections
can exist between labels with identical names
?flagNon45
Tells the input translators to check for non-45 degree
edges
?flagOffGrid
Writes any polygon or cell instance with one or more
vertices not on a specified grid to an error layer
named offGridShapeErrors and offGridInstErrors
2
Running LVS
Step IV
Running LVS
Select Run LVS. . . from the Assura menu. Fill the form :
Select your design here.
This field should be
automatically filled with
the current design.
Check these to skip
netlisting of shematic
and/or layout.
Select a run directory
here, where all the
assura files for this
run will be created.
Select UMC18_LOGIC
technology and select
default rule set.
Set switches here.
Some parameters can
be changed here.
After a successful run, a short message will either say “Layout and schematic match” or, if there
are any errors, a summary will be displayed. In any case, by pressing Yes you will enter the LVS
Debug Environment, which will help locate the errors.
If the run is unsuccessful, look in the log file to locate the errors.
Select a cell.
Select an error.
Double-click or click
'Open Tool...'
The error is
explained here
Erroneous components
are displayed in this
window
Probe and Zoom
allow to locate the
component in the
schematic as well
as in the layout.
Switches
Skip SoftConnect Checks
Setting this switch causes LVS to skip the reporting
of multStamp, floating, and multConnect errors.
3
Running LVS
Useful LVS avParameters
?blackBoxCell
Specifies individual cellnames or file containing the
cellnames to be treated as black boxes
?flagMalformed
Determines if all or no malformed device shapes
are flagged. Overrides any flagMalformed argument
specified in any device extraction function
?ignoreCell
Defines the list of layout cells (and only layout cells)
that you do not want Assura to analyze, including
dependents of these cells
?joinPins
Specifies under what conditions virtual connections
can exist between labels with identical names
?standardCell
For parasitic extraction, ?standardCell specifies
characterized standard cells in a timing library that
the software can process to create a Detailed Standard Parasitic Format (DSPF) file. For regular DRC
or LVS runs, all the specified cells will have all of
their internal hierarchy flattened
Cross Probing
Assura allows to visually cross-probe between the layout and the schematic, after a successful LVS
job has been run. To do this, select Probing. . . from the Assura menu. The probing window
appears :
Probing by Name :
Enter a device or net
name here, then click
Add Probe
Choose a layout window
here if you want to probe
by name
Probing visually :
Click Add Probe, then
select a device or net
from either the schematic
or the layout.
Choose the type of
object to probe here
Use to zoom on a
probe
Probing visually
To visually probe for nets or devices, first choose the type of object you want to probe (check Nets
or Devices). Then, click on Add Probe and select an object either in the schematic or in the layout
window. The selected object will be highlighted with the same color in both windows. The probe
is often difficult to see in the layout window. In this case, use Fit Last Probe to locate it.
Probing by name
To probe by name, first choose the type of object you want to probe (check Nets or Devices). Then,
type in the name of an object (for instance, IN for a net or C1 for a device) and click on Add Probe.
4
Extracting parasitics
Using probes to locate LVS errors
The two last probing options, Nets for Device and Devices for Net are useful for locating LVS errors.
Both option can apply to matched or to unmatched devices or nets. The first one will hilight all
matched or unmatched nets connected to the selected device, while the second one will highlight
all matched or unmatched devices connected to the selected net.
Notes on connectivity extraction
Because of the way connectivity informations are handled in this design kit, there are special layers
for creating pins. DFII pins, created with Create→Pin are not used for connectivity extraction,
and this will result in LVS errors if you have pins in your schematic, so do not use them. Instead,
use labels on POTXT, M1TXT, M2TXT, etc. . . layers. These labels will be used to generate layout
pins during LVS. Of course, the text layer must match the routing layer you want to label (POTXT
for POLY, M1TXT for MET1, . . . ). Nets can be labelled, without creating pins, by creating labels
on the routing layers (POLY, MET1, MET2, . . . ).
Step V
Extracting parasitics
Assura RCX can only be run after a successful LVS run. Select Run RCX. . . from the Assura
menu. Fill the form :
Check this to create
an extracted view
without parasitics
extraction
Select UMC18_LOGIC
technology and select
default rule set.
Type the LVS run
name here.
Type a value here to
extract distributed RC
networks.
Check to extract
parasitic resistance.
Parasitic resistances
smaller than minR are
discarded.
Check to extract
parasitic capacitance.
Check to separate via
resistance from
interconnect resistance.
Check to extract
parasitic inductance.
Allows to extract
parasitics for only part
of the circuit.
3-D parasitics
extraction.
Choose a name for the
extracted view.
av_extracted is the
default.
Choose the output
format (extracted view
or netlist).
Some parameters can
be changed here.
After a succesful RCX run, an extracted view is created with the extracted parasitics that can be
used for simulation. The results can also be used for probing parasitics on the layout, or can be
backannotated to the schematic.
5
Extracting parasitics
If the run is unsuccessful, look in the log file to locate the errors.
Note on capacitance extraction
Capacitances can be extracted in one of two modes : coupled or decoupled. Coupled extracts coupling
(fringing) capacitances between adjacent interconnects, while decoupled lumps these capacitances
to ground with a multiplying factor.
C
1.2 C
Decoupled caps using
1.2 Mult Factor
Coupling cap between
selected nets
Note on resistance extraction
The extraction of distributed RC networks is controlled via the max fracture setting. This setting
controls the length of extracted wire segments as explained below :
IN:2
IN:1
IN
IN
IN:1
IN:2
IN:3
IN:3
IN:1
IN
RCX Run Form Max Fracture Settings
IN
IN:1
Probing parasitics
Assura provides an interface to visually probe parasitics. To do this, select MSPS. . . from the
Assura menu, then click on Parasitic Probe. . . .
Three probing modes are proposed :
• Whole Net
Sums all the parasitics connected to the selected net.
6
Extracting parasitics
• Net to Net
Sums all the parasitics connected between two selected nets.
• Point to Point
Sums all the parasitics connected between to selected points (component pins).
Click on one of these, the schematic window will pop-up. then select one or two nets from either
windows, a summary will be displayed. The av extracted view can also be used for parasitics
probing.
av extracted view with parasitics
Backannotating parasitics to the schematic
Assura allow back-annotation to the schematic of the parasitics value. This is useful to have a clear
view of which nodes are critical.
To do this, select MSPS. . . from the Assura menu, then click on Backannotate. . . . In the Parasitics Backannotation window, click on Add Parasitics. The schematic will pop-up with parasitics
annotated on each net. Note that the displayed value is the total value, that is, the value you obtain
when probing with the Whole Net option.
With Remove Parasitics, you can remove the annotations from the schematic. There is also an
option Print All. . . that allow to dump all the parasitics to a file.
7
Extracting parasitics
schematic with backannotated parasitics
Building an av analog extracted view
Building an av analog extracted view allows you to simulate a circuit with the parasitics you choose
to include.
To do this, select MSPS. . . from the Assura menu, then click on Build Analog. . . . In the next
window, you can choose to add none, some (select from schematic) or all of the parasitics.
If you use the second option, you have to add special components to your schematic to specify which
parasitics to include. These special components are spresistor, spinductor, spcapacitor and
spcapacitor2 (used for net-to-net parasitics). They are availabe from the sbaLib library which
can be found in $CDSDIR/tools/dfII/etc/cdslib/artist/sbaLib.
Additional References
• Assura Physical Verification User Guide
/softs/cadence/assura/3.0 5.0/doc/assurauser/assurauser.pdf.
• Cadence Parasitic Simulation User Guide
/softs/cadence/ic/5.0.32/doc/parasim/parasim.pdf.
8