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Hardware for Real-time systems
 Von Neumann Architecture
 Address, data and control bus – parallel buses
 Bi-directional data bus transfer instructions and data
 Control bus is a collection of independent buses with power lines,
status, control and clock lines
 I/O registers are memory mapped and access the same way as
regular memory for real-time performance
 Computer Arithmetic Logic Unit, ALU
 Work and status registers
 PCR Program Control Register addresses external memory
 IR Instruction Register
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Interrupts
 Processors provide instructions for enabling and disabling mask-able
interrupts
 Enable Priority Interrupts
 Disable Priority Interrupts
 Atomic, should be used cautiously and sparingly only when absolutely
needed, could compromise real-time performance
 This capability should not be used by application programs, it is used
only for kernel and system level software
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Memory
 Volatile RAM, nonvolatile ROM
 The difference is not as clear as it used to be: EEPROM and Flash
ROM can be written to by in-system programs
 Erasing and writing for this class of ROM is still much slower than
RAM, writing to EEPROM can be over 100 times slower than
reading
 Typically each memory cell can be rewritten to for a limited number
of times due to the stress placed on the cells during rewriting
process
 Data can be safely stored for many years
 EEPROM is typically only used to store program or
parameter/configuration data
 Flash PROM is typically used to store programs or large data
 Not only is ROM very slow to re-write, it is also typically slower
than RAM to read
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 For real-time applications, it is often necessary to run programs from
faster RAM
 Slower but movable Flash ROM (UBS Flash) could be used as way to
load application programs to RAM for execution
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 RAM devices
 Static RAM
 Dynamic RAM
 Typically SRAMs require more space and are more expensive, but
faster to access
 DRAMs leak charge in their storage capacitors and must be
constantly refreshed
 At least 3-4 ms refresh circuitry is needed for DRAM
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Memory access
 Over the past few decades, memory access has been the primary
bottleneck in real-time system processing
 Cache Memory vs. Main Memory
 Caches are relatively small storage of fast memory where frequently used
instructions and data are stored
 Well written Procedural programs typically execute sequentially and
could have high memory locality of reference
 Object oriented programs may not allow locality of reference as well as
procedural programs, but could be made to follow sequentially for
computational intensive or critical real-time segments of the code
 DRAM can be used for fast block access for loading sequential
instruction code or sequential data from main memory to SRAM
(cache)
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Pipelined Instruction Processing
 Under ideal conditions with a continuously full pipeline an instruction
is executed every clock cycle
 Pipelining help sequential instruction processing
 Pipelining reduces effectiveness when faced with Branching
statements
 External interrupts have similar effect as branching
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Multi-Core Processors
 After pushing clock speed to what appears to be a high limit at this
time, high clock rates of less than 2-3 GHz are used with emphasis
placed on development of multi-core architectures
 Based on homogeneous parallel processor technology
 Each physical core processor usually has its own private cache
memory, these on-chip caches are interfaced to larger on-chip cache
memory that is common to all cores
 Special compiler and optimized libraries provided for each multi-core
architecture
 Software must be designed for parallel processing and concurrency,
otherwise the potential of multi-core processing will not be realized,
non-concurrent or single-CPU code will only utilize a small subset of
the cores available with other cores left un-used
 Hyper-threading
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 Load balancing
 Communications channel is again the bottle neck for this architecture
as well
 Some non-deterministic behavior that we need to be aware of
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Complex Instruction Set Computers (CISC) vs. Reduced
Instruction Set Computers (RISC)
 Pipelining, caching and response time for CISC and RISC processors
 Dividing line between CISC and RISC processors are blurred
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 Interrupt Driven Input/Output (I/O)
 Priority Interrupt Controller (PIC)
 Interrupt Request, Interrupt Acknowledge, Interrupt Vector
 Privilege to interrupt should be given to time-critical I/O events only
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 Direct Memory Access (DMA)
 Analog and Digital I/O
 Nyquist-Shannon sampling theorem
 Does not account for Non-linear effects
 Over-Sampling
 Aliasing
 Low-pass filtering delay
 One additional bit of quantization resolution corresponds to
approximately 6 dB increase in the signal-to-noise (SNR) of the
digitized signal
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 Distributed real-time architectures
 Field bus Networks
 Can be used in high Electro Magnetic Interference, high EMI environments
 Controller Area Network, CAN
 Implemented in variety of topologies or physical structures such as bus, ring,
and tree
 Industrial Ethernet
 Borderline between office and industrial field bus is becoming blurred
 Use of high speed fiber optic medium for Ethernet may prevent impacts of
EMI, however the new issue is light loss, cable bend radius, dirt, etc.
 Node to node communications delays and time synchronization poses a
challenge for highly distributed complex real-time networks
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 Open System Interconnect (OSI) seven layer communications protocol
 Physical (bits) – bit stream across the network
 Data Link (frames) – builds data packets & synchronizes traffic
 Network (packets) – routes data to the proper destination
 Transport (segments) – Error checking and delivery verification
 Session (data) – Opens, coordinates and closes session
 Presentation (data) – Converts data from one format to another
 Application (data)
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 Time-Triggered Architectures (i.e. Time-Triggered Protocol)
 Synchronous communications with a common clock
 More limitations with physical distance of nodes
 Fault tolerance and Fail-over responsibilities
 Uses Time Division Multiple Access (TDMA) and broadcast communication
 Latency of all messages on the channel are known and we can guarantee
hard real-time message delivery
 Messages are sent only at pre-determined times
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