Coupling of channel conductance and gate-to-channel capacitance in electric
double layer transistors
Feilong Liu1, Wei Xie2, Sha Shi1, C. Daniel Frisbie2, and P. Paul Ruden1
1
Department of Electrical and Computer Engineering, University of Minnesota, 200 Union St. SE, Minneapolis, MN,
55455
2
Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave. SE,
Minneapolis, MN, 55455
SUPPLEMENTARY MATERIAL
Experimental Details
Crystal Growth: Source materials of rubrene were purchased from Sigma-Aldrich (sublimed
grade) (Milwaukee, US). Rubrene crystals were grown from horizontal physical vapor transport. S1 Thick
crystals (> 10 μm in thickness) were selected for subsequent device fabrication.
Device Fabrication: Air-gap PDMS (Sylgard 184, Ellsworth Adhesives) substrates with prepatterned souce/drain/gate contacts were fabricated using previously establish procedures. S2 The metal
contacts were 3/20 nm Cr/Au (evaporation rate 0.1 nm/s) done by a CHA e-beam evaporator. The depth
of the air-gap was 5 μm, measured by a KLA-Tencor P-16 surface profiler. Crystals were laminated
across the source and drain contacts forming so-called air-gap transistors at first, and the EDLTs were
fabricated by injecting a drop of ionic liquid high purity grade 99.9%, purchased from EMD Chemicals,
USA) into the channel and filling up the entire air-gap through capillarity. The liquids were dried before
use in a vacuum oven at 70 oC for three days and were kept in a N2-filled glovebox afterwards to
minimize the water contamination.
1
Electrical Measurement: Rubrene EDLTs were characterized in a Desert Cryogenics (Lakeshore,
Inc) vacuum probe station in a N2-filled glovebox with Keithley 236 and 6517 electrometers using
homemade LabVIEW programs. AC admittance measurements were performed by a HP 4192A LF
Impedance Analyzer. Low temperature measurement employed a Lakeshore 331 temperature controller.
All measurements were carried out in dark and in vacuum at pressure <10-6 Torr.
Discussion of the Equivalent Circuit Model
The discussions in the main text are based on the equivalent circuit model in FIG. 2. With source
and drain terminals connected, the full expression for the admittance between gate and source/drain can
be written as:

1
Y   Z ES  RE 
jC ME

1

  jC geo

(S1)
One might ask whether this model is valid or how well it can represent the real device. In this
section, a qualitative explanation is given based on the idea of lumped vs. distributed circuit elements.
An equivalent circuit model is essentially a combination of ideal circuit elements that
approximates the real device. For the model in FIG. 2, the double-layer charge interface is modeled as a
single capacitor at the gate/electrolyte interface (lumped element), and as a capacitor/resistor network at
the electrolyte/semiconductor interface (distributed element). The bulk electrolyte is represented by a
single resistor (lumped element). Obviously, this is not the only choice. For example, FIG. S1 shows an
alternative equivalent circuit model that expresses all circuit elements as distributed. The calculated gateto-channel equivalent capacitance and the phase of admittance for both models are shown in FIG. S2.
They coincide at low frequency but deviate at high frequency.
2
Both equivalent circuit models share some degree of inaccuracy when representing the real
device.
For the model in FIG. 2, it is assumed that beyond the first monolayers of ions at the
electrolyte/semiconductor interface, the electrostatic potential is equal everywhere. For the model in FIG.
S1, the constraint of equal potential is eliminated, but at the same time it prohibits current flow in the
electrolyte in the direction parallel to the interface. Neither of the models fully describes the physics of
the system. In principle one can introduce additional distributed circuit elements to improve accuracy.
However, this implies additional parameters, and for the discussions of EDLTs as explored in this work,
the model in FIG. 2 is found to be adequate.
FIG. S1. (Color Online) An alternative equivalent circuit model for EDLTs, with all circuit elements in a
distributed type.
3
FIG. S2. (Color Online) The calculated equivalent gate-to-channel capacitance (left) and the phase of
admittance (right) as a function of frequency at 235 K. The black solid lines are from the equivalent
circuit model in FIG. 2 of the main text. The red dashed lines are from the model in FIG. S1 with the
same parameters.
Frequency Window for Conductance-Capacitance Coupling
In the main text, a characteristic frequency fC is estimated. For f > fC, the capacitance-voltage plot
follows a similar behavior as the conductance-voltage plot. In other words, fC is the minimum frequency
limit for the coupling effect. In this section, we show that there also exists a maximum frequency, fmax,
beyond which the coupling effect vanishes. Therefore, the conductance-capacitance coupling can be
observed only in the frequency window fC < f < fmax, where fC and fmax are determined by device
parameters.
Based on the discussion of ZES in the main text, the device admittance in equation (S1) for f > fC
can be simplified to:
4
1
Y 
2

1
RS
1
 RE 
jC ES
jC ME

  jC geo


(S2)
As the frequency increases, the first and third terms in the bracket decrease and eventually (f >
fmax) Y is reduced to 1/RE + jωCgeo. The gate-to-channel equivalent capacitance is then the geometric
capacitance, and the coupling to the channel conductance disappears.
A rough estimation of fmax is (2πRECgeo)-1. In our device fmax is approximately 106 Hz. The
measured gate-to-channel capacitance is shown in FIG. S3. The 104 Hz curve is the same as that in FIG.
5(d). It is observed that, as the frequency increases, the capacitance approaches Cgeo, which is consistent
with the results in FIG. 4(c). The difference between the maximum and minimum of the capacitance
(which implies a voltage-dependent conductance) decreases greatly with increasing frequency.
The minimum frequency, fC, is determined by the semiconductor channel conductance and the
electrolyte/semiconductor interface capacitance, while the maximum frequency, fmax, is determined by the
electrolyte conductance and the geometric capacitance. Therefore, in order to observe the capacitanceconductance coupling effect, the device must be designed to ensure fC < fmax.
5
FIG. S3. (Color Online) Equivalent gate-to-channel capacitance-voltage characteristics of EDLTs at 235K
in the high frequency regime. The squares, circles and triangles are experimental data for the same device
as FIG. 5 in the main text. The dashed line is the geometric capacitance of the device.
S1
R. A. Laudise, C. Kloc, P. G. Simpkins, and T. Siegrist, J. Cryst. Growth 187, 449 (1998).
S2
E. Menard, V. Podzorov, S. H. Hur, A. Gaur, M. E. Gershenson, and J. A. Rogers, Adv. Mater. 16,
2097 (2004).
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