CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
OCTOBER15
ASSESSMENT_CODE BC0036_OCTOBER15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33678
QUESTION_TEXT
a.
b.
Explain NAND and NOR gate as universal gates.
Write a note on k-MAP.
i. Not or inversion logic realization using NAND
ii. AND realization using NAND
iii. OR realization using NAND
iv. NOR realization of NAND
SCHEME OF EVALUATION v. NOT or inversion logic realization using NOR.
vi. AND realization using NOR
vii. OR realization using NOR
viii. NAND realization of NOR (1 mark each=8 marks)
K-MAP.
(2 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33680
QUESTION_TEXT
Explain IC 7493-4 bit binary counter.
SCHEME OF EVALUATION
Explanation.
(6 marks, with explanation)
Explanation of Logic diagram.
(4 marks,)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33682
QUESTION_TEXT
Explain the various methods used for decimal to Octal conversion
with an example for each.
SCHEME OF
EVALUATION
Sum of weight method: Explanation with example- 4M
Repeated division method- Explanation with example- 3M
Repeated multiplication- Explanation with example- 3M
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73537
QUESTION_TEXT
SCHEME OF
EVALUATION
Prove that a+bc = (a+b)•(a+c). Use the Boolean algebra function to
specify the logic function and realize the given function and minimized
function using discrete gates: f = ab + a( b +c ) +b( b + c ).
Prove that a+bc = (a+b)•(a+c).
a + bc = a • 1 + bc
= a ( 1 + b ) + bc
= a•1 + ab + ac
= a•( 1 + c ) + ab + bc
= a•1 + a•c + a•b + b•c
= a•a + a•c + a•b + b•c
= a•( a + c ) + b ( a + c)
= ( a + c ) ( a + b ) (5 marks)
f = ab + a( b +c ) +b( b + c )
= ab + ab + ac + bb + bc
= ab + ac + b + bc
= ab + ac + b
= b + ac (5 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73538
QUESTION_TEXT
i. Write the procedure for the minimization of a logic expression with
Quine McClusky method.
ii.
SCHEME OF
EVALUATION
Mention different techniques of ADC.
The procedure for the minimization of a logic expression is done as follows:
1. Arrange all minterms in groups of the same number of 1s in their
binary representations…..
2. Now compare each term of the lowest index group with every term in
the succeeding group….
3. Place a tick mark next to the every term used while combining.
4. Perform the combining operation till last group to complete the first
iteration.
5. Compare the terms generated with same procedure with dashed line
mapping the dashed line in two terms under comparison.
6. Continue the process till no further combinations are possible.
7. The terms which are not ticked constitute the prime implicants.
(1 mark each)
Different techniques of ADC:
1. Flash type ADC
2. Staircase Ramp or Digital Ramp type ADC
3. Successive approximation method
4. Slope integrator type ADC
Single slope integrator
Dual slope integrator
(3 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73540
QUESTION_TEXT
Describe the operations performed by the following arithmetic circuits
along with truth table for each.
a. Half adder
b. Full adder
c. Half subtractor
d. Full Subtractor
SCHEME OF
EVALUATION
Half adder: (With explanation -1.5M)
Addition of two single bits results into single bit
Addition of two 1s resulted into two bits.
These operations were carried by a logic circuit called half adder which
takes two binary digits as input and produces two binary digits on the
output terminal known as sum and carry bit.
Truth able- 1M
Full adder: Accepts three one bit inputs and generates a Sum and a
Carry output. (With explanation-1.5M)
Truth table: 1M
Half subtractor: Subtracts one bit from another. It is used to subtract
LSB of the subtrahend from the LSB of the minuend when a binary
number is to be subtracted from other.
Explanation -1.5M
Truth table -1M
Half subtractor: Performs subtraction of two bits with borrow
generated if any, during previous LSB subtraction.
Explanation -1.5M
Truth table -1M
Explain different types of Slope ADC circuit. (Unit 10, Page 191-193)
Ans: (Each with explanation 5M each)
Single Slope integrating ADC
Dual Slop Integrating ADC