CUSTOMER_CODE
SMUDE
DIVISION_CODE
SMUDE
EVENT_CODE
OCTOBER15
ASSESSMENT_CODE BC0036_OCTOBER15
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33679
QUESTION_TEXT
a.
b.
Explain parallel binary adders.
Write a note on demultiplexers and SR latch.
Parallel binary adders.(3 marks, with explanation)
SCHEME OF EVALUATION Demultiplexes
(3 marks, with explanation)
S-R latch
(4 marks, with explanation)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33680
QUESTION_TEXT
Explain IC 7493-4 bit binary counter.
SCHEME OF EVALUATION
Explanation.
(6 marks, with explanation)
Explanation of Logic diagram.
(4 marks,)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
33681
QUESTION_TEXT
Write a short note on Prime implicants and Prime implicant Chart.
SCHEME OF
EVALUATION
Prime implicant: Solution of logical expression with Ouine McClusky
method involves in the computation of prime implicants from which
minimal sum should be selected. The procedure for the minimization of
a logic expression is done as follows: (each point 1 mark)
Arrange all minterms in groups of the same number of 1s in their binary
representation.
Compare each term of the lowest index group with every term in the
succeeding group. Whenever two terms differ by one bit position, the
two terms were combined with – used in the place of differing position.
Place a tick mark next to the every term used while combining.
Perform the combining operation till last group to complete the first
iteration.
Compare the terms generated
Continue till no further combinations are possible.
The terms which are not ticked constitute the prime implicants.
Prime implicant chart: Is a representation giving the relationship
between the prime implicants and minterms constituting the logic
expression. (With detailed explanation 3M)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73538
QUESTION_TEXT
i. Write the procedure for the minimization of a logic expression with
Quine McClusky method.
ii.
SCHEME OF
EVALUATION
Mention different techniques of ADC.
The procedure for the minimization of a logic expression is done as follows:
1. Arrange all minterms in groups of the same number of 1s in their
binary representations…..
2. Now compare each term of the lowest index group with every term in
the succeeding group….
3. Place a tick mark next to the every term used while combining.
4. Perform the combining operation till last group to complete the first
iteration.
5. Compare the terms generated with same procedure with dashed line
mapping the dashed line in two terms under comparison.
6. Continue the process till no further combinations are possible.
7. The terms which are not ticked constitute the prime implicants.
(1 mark each)
Different techniques of ADC:
1. Flash type ADC
2. Staircase Ramp or Digital Ramp type ADC
3. Successive approximation method
4. Slope integrator type ADC
Single slope integrator
Dual slope integrator
(3 marks)
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
73540
QUESTION_TEXT
Describe the operations performed by the following arithmetic circuits
along with truth table for each.
a. Half adder
b. Full adder
c. Half subtractor
d. Full Subtractor
SCHEME OF
EVALUATION
Half adder: (With explanation -1.5M)
Addition of two single bits results into single bit
Addition of two 1s resulted into two bits.
These operations were carried by a logic circuit called half adder which
takes two binary digits as input and produces two binary digits on the
output terminal known as sum and carry bit.
Truth able- 1M
Full adder: Accepts three one bit inputs and generates a Sum and a
Carry output. (With explanation-1.5M)
Truth table: 1M
Half subtractor: Subtracts one bit from another. It is used to subtract
LSB of the subtrahend from the LSB of the minuend when a binary
number is to be subtracted from other.
Explanation -1.5M
Truth table -1M
Half subtractor: Performs subtraction of two bits with borrow
generated if any, during previous LSB subtraction.
Explanation -1.5M
Truth table -1M
Explain different types of Slope ADC circuit. (Unit 10, Page 191-193)
Ans: (Each with explanation 5M each)
Single Slope integrating ADC
Dual Slop Integrating ADC
QUESTION_TYPE
DESCRIPTIVE_QUESTION
QUESTION_ID
106595
QUESTION_TEXT
Explain the procedure to design an asynchronous mode-M counter
where M is not a power of 2.
SCHEME OF
EVALUATION
To design an asynchronous counter to count till M or mod-M counter
where M is not a power of 2, following procedure is used.
●
Find the number of flip-flops required. Calculated value is not an
integer value if the M ≠ 2n then select n by rounding to the next
integer value.
●
First write the sequence of counting till M either in ascending or
in descending way.
●
Tabulate the value to reset the flip-flops in a mod-M count.
●
Find the flip-flop outputs which are to reset from the tabulated
value.
●
Tap the output from these flip-flops and feed it to an NAND gate
whose output is connected to the clear pin.
(Each step carry 2 marks)