(a) (b) (c) (d) Monolithic 3D Chip: 3D circuits often are made by

Monolithic 3D Chip: 3D circuits often are made by stacking separate chips and connecting them electrically with through-silicon vias (TSVs), but TSVs have
significant disadvantages including relatively narrow I/O bandwidth. Monolithic 3D ICs with no TSVs—where the devices in adjacent layers are directly
connected—have been demonstrated, but transistor damage from thermal annealing can arise. That’s because each layer in a 3D device must be annealed to
remove stresses in its crystalline silicon structure, and to activate the dopants which have been implanted in it. The high heat involved with annealing (>1,000°C)
can damage devices already built in the lower layers. A team led by Taiwan’s National Nano Device Laboratories addressed this issue by using a CO2 far-infrared
laser at 400°C to selectively pulse-anneal specific areas of the silicon (the source-drain regions). They used this technique to build a sub-40nm monolithic IC
containing a variety of heterogeneous functions—logic, SRAM, RRAM, sense and analog amplifiers, and gas sensors. No device degradation was reported. The
researchers say the technique is suitable for making low-power, low-cost, small-footprint and heterogeneously integrated devices needed for the Internet of Things.
Image (a) is a conceptual illustration of the device showing its heterogeneous functions; (b) outlines the process steps needed to fabricate it; (c) is a
schematic of the CO2 far-infrared laser activation damage test on interconnect metallization (BEOL) and circuit functions (FEOL); (d) is a photograph of
a stackable 6T-SRAM array.
(Paper 25.4, Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things; Tsung-Ta Wu et al,
National Nano Device Laboratories/National Tsing Hua University)