International Journal of Engineering Trends and Technology- Volume3Issue3- 2012
A Study of 3D IC’s Integration and Formation
using TSV
Hitesh Joshi1, Rajeev Mathur2
#1
#2
M.Tech Scholar, ECE Dept. Mewar University, Chittorgarh (Rajasthan) -312001, India
Professor, ECE Dept., Geetanjali Institute of Technical Studies, Udaipur (Rajasthan) -313001, India
Abstract - In today’s era the demand of Very Large
Scale Integrated Circuit (VLSI) is increase due to the
growth of the Electronics industry. VLSI has high
performance and high functionality at minimum cost
and power dissipation. Continuously scaling of VLSI
circuits is reducing gate delays but rapidly increasing
interconnects delays. The higher power consummation
is due to long wiring networks and clock distribution
also by the interconnect delays. 3D IC is typically
designed by multiple design teams, in multiple
geographies, using a variety of design tools. This paper
discusses the design of a 3D IC by the formation of
integrated circuit; Through-silicon-vias (TSV) based
integration modeling techniques, challenges of 3D IC’s
integration & packaging and future aspect of 3D IC.
Keyword - VLSI, 3D IC, TSV, GeOI, SoC
I. Introduction
The three dimensional (3-D) chip design strategy
exploits the vertical dimension to alleviate the
interconnect related problems and to facilitate
heterogeneous integration of technologies to realize
system on a chip (SoC) design. By simply dividing a
planar chip into separate blocks, each occupying a
separate physical level interconnected by short and
vertical interlayer interconnects (VILICs), significant
improvement in performance and reduction in wirelimited chip area can be achieved. In the 3-Ddesign
architecture, an entire chip is divided into a number
Fig.1 3D IC using TSVs and 6 die.[1]
of blocks, and each block is placed on a separate
layer of Si that is stacked on top of each other
II. Formation of 3D Integrated Circuits
There are several types of 3D-ICs differentiated
primarily by the degree of vertical interconnectivity.
These include 1) package level stacking and
connections such as cell-phone memories (limited to
peripheral connections), 2) wafer to wafer or die to
wafer bonding with through-via holes, and finally 3)
monolithic 3D-ICs, which exhibit a bottom-up
manufacturing of 3D layers, giving highest (gatelevel) vertical interconnectivity potential.
Although monolithic 3D-ICs possess maximum
benefits with aspects to speed, power, alignment
between layers and yield [2], their fabrication is a
challenging feat. It requires low temperature
processes preferably under 400 ºC in order to
preserve underlying layers. These layers consist of 1)
interconnect stacks composed of metals, fragile and
porous low dielectric constant (k) materials, and 2)
device layers, whose parameters such as junction
depths are tightly controlled for performance by
limiting the thermal budget. In light of this problem,
utilization of Germanium (Ge) as an ideal substrate
for 3D-ICs is being considering as a solution because
of its lower melting point than Si, which makes low
temperature CMOS processing more feasible.
Fig.2 Monolithic 3D-ICs [3]
III. Channel Formation
Several techniques are being pursued to obtain
germanium on insulator (GeOI), necessary for
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International Journal of Engineering Trends and Technology- Volume3Issue3- 2012
monolithic 3D-ICs. The most important point, here,
is that Ge with imperfect crystal, e.g., polycrystalline
structure, degrades transistor performance by 1)
reducing the on-current, 2) adversely impacting the
subthreshold slope, and 3) increasing leakage current
and power dissipation. The adverse impact of grain
boundaries on Ge is more severe than Si because of
its higher mobility and lower band-gap. Thus, it is
imperative to obtain a device-suited single crystalline
Ge on silicon dioxide (SiO2), at a sufficiently low
temperature for high performance 3D-ICs. The single
crystalline GeOI growth techniques include: rapid
melt growth (RMG) [5] with a continuous
wavelength (CW) laser scanning technique [6],
fusion bonding process utilizing Smart CutTM [7]
and chemical mechanical polishing (CMP) methods
[8], and metal-induced lateral crystallization (MILC)
[9].
General RMG method employs liquid phase epitaxy
(LPE) mechanism and defect blocking technique to
make a high quality and ~ 20 µm long single
crystalline GeOI structure as shown in Fig. 3 and 4.
In this technique amorphous Ge is deposited on the
insulator with a seed window on a Si substrate. The
Ge is patterned into stripes and then covered by lowtemperature oxide (LTO). The temperature of the
wafer is raised up to 940 ºC by rapid thermal
annealing (RTA) (melting temperature of Ge : 937
ºC), and the LTO serves as a micro-crucible to hold
the liquid Ge. Upon cooling down, liquid phase
epitaxy takes place at the a-Ge/c-Si interface and then
propagates along the Ge stripe. The defects due to
lattice mismatch are necked down near the seed
window, and thus the rest of the Ge is high-quality
and single-crystalline. This process is compatible
with Si-based fabrication with an advantage that the
Ge film orientation can be controlled by the Si
substrate.
Fig 3 (a) Top view and (b) side view Ge RMG
process [5]
Fig 4 Cross sectional TEM images formed by the
RMG technique [6]
However, the RMG method requires high process
temperature close to 940 ºC, which is much higher
than acceptable for monolithic 3D-ICs application.
Therefore, Jia Feng et al. [10] replaced the RTA step
by a CW laser scanning technique to keep the
temperature of bottom interconnect and device layers
to below 400 ºC. After annealing by the scanning CW
laser anneal system (frequency-doubled Nd:YAG
laser, wavelength = 532 nm, output power = 6 W,
beam diameter = 30 um, and scan speed = 20
um/sec), melt growth is guided by the laser over a
long distance up to 6 µm and high-quality single
crystalline GeOI stripes are obtained. This modified
RMG process can be utilized to form Ge channel
region of the second layer of devices for monolithic
3D-ICs because the temperature of bottom device and
interconnect layers does not exceed 400 ºC while
making this GeOI structure.
[[
Another technique used to obtain high quality single
crystalline GeOI at below 400 ºC is wafer bonding
using CMP and Smart CutTM methods. Ge is
heteroepitaxially grown on Si. This donor wafer is
then bonded to another Si wafer having a layer of
silicon dioxide (SiO2) on it. Grinding or CMP and
etching methods can be then applied to form the
GeOI structure. In such a case, however, one of the
two wafers (donor) is completely lost. Ge films with
improved quality can be obtained by using
Czochralski-grown bulk Ge wafers with zero
dislocations instead of heteroepitaxially grown Ge
[11]. A more efficient way is offered by combining
CMP and Smart CutTM technology [8]. The basic
process flow includes epitaxial Ge growth on donor
Si wafer implanted with hydrogen ion (H+) which is
bonded to acceptor wafer (SiO2 on Si wafer). After
bonding the donor wafer is peeled off at the region
where hydrogen was implanted, followed by a CMP
step, as shown in Figure 5. The final CMP step is
necessary to reduce surface roughness occurred near
the H+ implantation layer.
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These germanide/Ge Schottky MS junctions can
serve as S/D of the 2nd layer Ge MOSFETs [14].
Fig 5 Bonding process flow [11]
Because this wafer-level GeOI process is performed
at around 400 ºC, this technique can be used for
monolithic 3D-ICs fabrication.
IV. Source/drain Formation
Another component that we need to consider to
realize Ge MOSFETs in monolithic 3D-ICs is low
temperature source/drain (S/D) formation. S/D
thermal annealing is a strenuous issue in Ge CMOS
fabrication for monolithic 3D-ICs because minimum
temperatures required for S/D activation are ~ 500 ºC
for n+ and ~ 400 ºC for p+ S/D [12]. Thus, it is
difficult to achieve well-activated S/D below 400 ºC
in Ge CMOS fabrication, for it will only result in
fractional dopant activation, which degrades the
junction quality. This issue is more severe when
fabricating the Nchannel Ge MOSFET. Up to date
reported low temperature S/D formation methods
which are acceptable for monolithic 3D-ICs
fabrication can be divided into three approaches; (1)
dopant activation by laser annealing process [13], (2)
Schottky metal-semiconductor (MS) junction
formation, and (3) metal induced dopant activation
(MIDA) [14].
Very low resistivity has been reported in pulsed laser
annealed (PLA) S/D, as compared with S/D activated
by RTA process. As it is already well known, laser
beam works by melting S/D regions locally,
regrowing damaged crystals, and finally activating
dopants. Because other device regions except S/D are
not heated up in this process, this is one of the
possible S/D formation techniques that can be used in
fabricating monolithic 3D-ICs.
Another candidate to be able to form S/D at below
400 ºC is Schottky MS junction formation technique.
As shown in Figure 3.9, because various metals react
with Ge at below 400 ºC (Pd at ~170 ºC, Cu at ~220
ºC, Ni at ~220 ºC, Pt at ~310 ºC and Co at 400 ºC)
thereby forming germanides with very low resistivity.
A RTA at 400 ºC for 2 minutes is sufficient to form
NiGe that provides a suitable Schottky MS junction
for S/D of P-channel Ge MOSFETs. Due to its low
process temperature (400 ºC), it can be applied for
monolithic 3D-ICs fabrication. However, the NiGe
obtained at 400 ºC forms an ohmic contact to p-type
Ge substrate whereas excellent Schottky MS junction
is observed in n-type Ge. It is widely known that the
work function of NiGe is much closer to the valence
band than to the conduction band in Ge because of
the Fermi level pinning effect. Other metals like Ti
and Co show a similar behavior in p-type Ge, making
it difficult to fabricate S/D junctions for N-channel
Ge MOSFETs. Inserting ultra thin GeOx layer
between metal and Ge, the Fermi level pinning
problem can be relieved due to the suppression of
electron wave function penetration from metal to Ge.
This metal insulator semiconductor (MIS) technique
provides Schottky junction in ptype Ge substrate for
S/D of N-channel Ge MOSFETs, but a near ohmic
contact is again formed in n-type Ge as the
previously described germanide/Ge MS junctions.
Therefore, it seems difficult to be applied for CMOS
compatible process.
Finally, low temperature MIDA technique featuring
metal induced crystallization (MIC) process, to
activate S/D at below 400 ºC [14]. Boron and
phosphorus atoms in α -Ge film are rearranged and
activated at low temperatures (≤ 360 ºC) during MIC
process, similar to dopant activation mechanism by
thermal annealing process. Because the MIDA
technique successfully activates both n- and p-type
dopant atoms at below 400 ºC, it can be used for
fabricating Ge CMOS for monolithic 3D-ICs.
Additionally, with this MIDA technique, high
performance n+/p & p+/n junctions and N- & Pchannel Ge MOSFETs are demonstrated at below
360 ºC, satisfying the thermal requirement of
monolithic 3DICs fabrication.
V. Gate Formation
A high-k dielectric can be easily deposited at below
400 ºC, but direct deposition of the high-k dielectric
on Ge has exhibited poor electrical characteristics
because of high interface trap density (Dit). Several
high-k materials (HfO2, ZrO2, Al2O3, and LaAlO3)
have been researched for the MOS gate dielectric on
Ge, but the carrier mobility in the MOSFETs was
degraded. In order to obtain better carrier mobility,
usage of an interlayerthe Ge surface for improving
the passivation before depositing a high-k dielectric
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International Journal of Engineering Trends and Technology- Volume3Issue3- 2012
is necessary.Low temperature (≤ 400 ºC) surface
passivation techniques include (1) ozen and (2)
plasma oxidation methods that achieve desirable Ge
surface passivation, leading to better CMOS
performance.
VI. Gate Electrode Formation
High-K/metal gate stack is a good low temperature
combination for a gate dielectric/electrode formation
in monolithic 3D-ICs fabrication. The metal gate
electrode can be replaced by a highly doped
polycrystalline Ge gate electrode deposited with a
diborane treatment method [15] at ≤ 310 ºC.
Conventionally, low pressure chemical vapor
deposition (LPCVD) is used to deposit a thin layer of
Si at 500 ºC as a seed for the growth of Ge on SiO2.
Because of the high process temperature required for
the Si seed, Ge gate electrode could not be utilized in
fabricating monolithic 3D-ICs. By replacing the Si by
a boron seed layer deposited by LPCVD from a
diborane (B2H6) source, the process temperature can
be reduced down to 310 ºC [15]. The mechanism
behind this is that lower B-H bond energy of B2H6
(35kJ/mol) compared to the Si-H bonds of SiH4 (323
kJ/mol) promotes attachment of boron atoms on the
SiO2.
After depositing the boron seed layer, Ge film can be
in-situ doped during the growth with boron and
phosphorus using B2H6 and PH3, respectively. Very
low resistivity (~1mΩ-cm) is observed in p-type Ge
gate electrode formed at 310 ºC. This poly-Ge gate
electrode fabrication satisfies the thermal requirement
(≤ 400 ºC) for monolithic 3D-ICs. In contrast,
phosphorus is not sufficiently activated at 310 ºC due
to poor crystallization [15].
VII.
electrically insulated from the substrate by a
dielectric layer (usually SiO2) and interconnects the
metal wires of the stacked dies. The geometry of the
TSV conductor may vary depending on the 3D
stacking technology. The area crossed by current may
have different shapes (squared, rectangular, circular,
elliptical, and polygonal). Also, the lateral surface of
the conductor can be cylindrical or conical.
The TSV interconnection of metal wires in adjacent
dies within a 3D stack can follow different schemes
[16]. For example, TSVs can connect a Metal 1 (M1)
wire of the top die with the topmost MN wire of the
bottom die when the latter features N-level wire
hierarchy, as shown in Fig. 7. Another scheme may
foresee the connection of both the topmost MN layers
of two adjacent stacked dies. The electrical link
established by a TSV between dies can be utilized for
any of the typical functions supported by standard 2D
interconnect: signal (analog and/or digital), clock,
and power supply/ground links. In general, the
geometry and the materials used in all the TSVs
crossing a die are the same and this simplifies the
optimization of the 3D technology process.
Once the TSV technology is fixed, the only degree of
freedom in achieving different design requirements in
the electrical characteristics of TSV links is to
employ more TSVs in parallel in the same link. For
example, this can be utilized in power supply
distribution networks, where high DC current
capability
is
required
and
low-resistance
interconnects is desirable. Connecting multiple TSVs
in parallel can decrease the resistance of
power/ground links among the stacked dies. In
addition, an increase in the parasitic TSV capacitance
due to multiple parallel TSVs can also contribute to
compensating dI/dt effects, similar to the effect of
inserting large decoupling capacitors.
Modeling
All 3D IC fabrication process comprise three basic
steps, namely wafer thinning, TSV etching and
filling, and tier bonding (Fig. 6). Depending on the
sequence of these steps we can distinguish between
different approaches. A process is described as “TSV
first” or “TSV last” if the TSVs are fabricated before
or after tier bonding, respectively, and the order in
which TSVs are fabricated within a 3D IC process is
an important process decision to be made before
developing a 3D IC technology.
The through-silicon via (TSV) is composed of a
conductor, also named “nail” or “plug,” crossing the
Si substrate of the stacked dies [16], as shown in Fig.
6. The conductor [common material choices include
copper (Cu), tungsten (W), and polysilicon] is
Fig. 6 3D IC stacked die [16]
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International Journal of Engineering Trends and Technology- Volume3Issue3- 2012
Fig. 7 Cross-section of a TSV [16]
VIII.
Conclusions
3D integration technology is currently under active
research by many organizations and more study and
investigation is needed especially in the design trade
off between its advantages and drawbacks. This
paper summarized in general about 3D integration
covering how 3D overcome scaling issues and what
are the issues and challenges related to it. We also
described several 3D chips implemented using
different process with different purposes. The
purpose is to give general but detail analysis that
includes all aspects of 3D IC design
3D ICs with TSVs represent a major new trend in the
semiconductor industry. They offer compelling
power, performance, and form factor advantages in
many application spaces, and they may curb the
escalating costs of SoC development. Because
designers can stack die from different process nodes,
it is no longer necessary to move all system
components, including analog and RF, to a single
process node.
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