In situ testing of CCD and NIR detector controllers
Roger Smith, Peter H. Mao, David Hale and Stephen Kaye
California Institute of Technology
ABSTRACT
As channel counts increase in both CCD and NIR detector controllers, it becomes
increasingly attractive to be able to run automated diagnostics while in service.
Automated in situ measurement of ADC differential non-linearity is described in
detail, since this is one of the subtlest problems and thus often goes undetected.
We outline signal path reliability and noise tests, which can be done without
controller modification. Bias and clock noise measurements described do require
a simple loopback connector in place of the detector, and thus some level of
human intervention for most detector controllers, but no special test equipment.
INTRODUCTION
It can often be very time consuming to determine whether a fault in a detector
system lies in the detector itself, the controller or the wiring between the two,
particularly when high channel counts are involved and/or the fault is
intermittent. Automation of diagnostics not only saves effort (in the long run)
but also provides consistency in the data collection, analysis and presentation,
which is essential for rigorous comparison of performance over time or different
system configurations. This becomes particularly important when problems are
subtle or intermittent. Ideally, any test automation software will also record
what system components are present, voltages and configuration settings, timing
waveforms (a file name?) and environmental conditions.
1.
Figure 1: Simplified schematic of typical detector controller.
We present “self test” methods, a subset of automated diagnostics, which can be
performed without connecting additional measurement instruments or test
signal generators. As a result these tests can be performed when the detector
controller is in service, in many instances without disconnecting the detector.
These tests focus in verifying signal path integrity and the key data quality
metrics: noise and ADC differential non-linearity.
2.
DETECTOR CONTROLLER AS ITS OWN OSCILLOSCOPE
Self test is not only convenient, but, for measuring noise and voltage drifts, is
usually superior to connecting external test equipment such as oscilloscopes or
spectrum analyzers. CCD read noise is typically ~15µV rms at the CCD output.
Input referred video chain noise should be significantly lower than this (<5µV rms
if total noise is to be degraded by <5%). The noise floor of an oscilloscope is at
least one and typically two order of magnitude higher than this. The
oscilloscope’s noise performance can be improved with the addition of active
differential input probes or by interposing a low-noise differential-input
preamplifier with bandpass limiting, however, there is a still the problem of pixel
synchronous interference (originating in the timing generator in the controller).
The detector controller relies on the following methods to achieve lower noise
than is seen in typical high quality test equipment:
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Pixel-synchronous interference is invisible. Provided that it reproduces from
frame to frame we can subtract it out and thus do not count it as noise. A
digital oscilloscope or spectrum analyzer sees this as a moving pattern and
thus “noise”.
The CCD signal path employs some form of Correlated Double Sampling to
limit the noise bandwidth to that where the signal power resides.
The CCD preamplifier is selected for the lowest noise when connected to
CCD output impedance, without needing to provide the bandwidth and input
voltage range normally supported by an oscilloscope.
When measuring the noise at some test point (e.g. a bias voltage) it is only
possible to judge its impact on system performance when all these methods are
employed. The obvious way to do so is to use the normal signal path to digitize
the signal of interest. Confidence in the results is predicated on the belief that
the signal path itself is working correctly and that the gain is known. We will
outline methods for building that confidence.
Figure 2: Video output for 100kHz pixel rate. Digital Oscilloscope Mode for STA's Archon
sampling (top trace, blue) exhibits lower noise than the real Digital Oscilloscope, Tektronix
MSO4054 (bottom trace, red). Both are sampling the same CCD output at 100MHz.
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Detector controllers employing Digital Correlated Double Sampling (DCDS)
coadd/subtract the samples in the controller to avoid increasing the data link
rate required when oversampling the video. Many DCDS systems can also be
configured to transmit the raw samples as a diagnostic (perhaps on only one
channel at a time). This “digital oscilloscope mode” provides a way to inspect
the video waveform directly, which is of course very useful as a diagnostic. It also
provides an illustration of the lower noise that is achieved through optimal
component selection, the absence of ground differentials and good supply
filtering. For example, Figure 2 compares the CCD output captured concurrently
using an “Archon” CCD controller (made by Semiconductor Technology
Associates) with a high quality Digital Oscilloscope equipped with an active
differential input probe to minimize ground differentials. The controller noise is
lower than the oscilloscopes even when both are sampled at the same rate. As
the controller noise bandwidth is reduced either by digital or analog CDS
processing the noise advantage of the controller will increase due to the reduced
noise bandwidth.
SIGNAL PATH TESTS
The following series of tests can be used to build confidence in the signal path.
We discuss tests of the output first, and work back to the input, as one might do
when commissioning a new controller. The reverse order might be preferred for
validating that a controller remains fully functional. A binary search may be
adopted in the event of a new fault.
3.
3.1
Artificial Data
Data links from the detector controller to host can exhibit a wide range of faults
which can be hard to detect such as rare and intermittent data corruption,
dropped bytes or even duplication. Data buffer management faults can result in
relocation or duplication of whole segments of an image. Rare and subtle faults
can be difficult to detect due to noise in the signal.
It is extremely useful for the controller (preferably the video board) to send a
predictable fixed pattern in place of the AD converter output. This can be as
simple a pixel counter. Having a means to embed a CCD channel identifier in the
data stream can be useful when debugging software.
With the use of programmable logic to interface ADCs to data links it should be
relatively simple to have a host selectable data mode where the individual
channels can be selected to generate fixed data patterns, with the host writing
the identifying code to each ADC interface so that it responds uniquely when
required.
The importance of these simple features should not be underestimated. The artificial data generator should exercise as much of the data path
as possible using the same control signals and timing.
3.2
ADC Differential Non-Linearity
The transfer function of an Analog to Digital Converter (ADC) is a staircase with
voltage plotted on the X-axis and the corresponding output code on the Y-axis.
The output codes on the Y–axis are uniformly spaced (by definition) while the
voltages at which transitions occur can suffer from systematic errors and noise.
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This variation in voltage-change required to increment the ADC output by one
count is known as differential non-linearity (DNL). The fractional variation in the
voltage-range is often referred to as “code width”, and described as a fraction of
a data number (DN) but of course, the actual data numbers are always integers
and it is the corresponding input voltage-range represented by a given data
number which is varying.
In extreme cases a converter may skip an entire code. The more common and
subtle failure mode is for the variation in the voltage range for successive codes
to be larger than expected. This can be viewed as an increase in quantization
noise if the read noise is many DN. If not, the read noise will appear to fluctuate
as the mean value changes. As excessively wide or narrow codes are
encountered so the local slope of the transfer function departs radically from the
global slope.
AD converter transfer function errors are more common than widely recognized,
probably because their measurement is not routinely performed. While the ADC
itself can be at fault, DNL problems are often caused by transients on supplies or
grounds, which occur at the same time during each conversion. Noise or
excessive source impedance on the reference voltage is another cause of DNL
problems. These subtle problems can surface when a bypass capacitor fails or
the wrong value is installed. Good DNL can be dependent on a strong connection
between analog and digital grounds. If this ground star point is not very close to
the ADC but occurs on the backplane, then DNL performance might change over
time due to changes in contact performance or other factors that affect ground
return currents or power supply filtering.
Figure 3: Code width errors for a poorly behaved ADC (AD ????). Input histogram
normalized by a boxcar filter (solid line) to remove slight shape due to input signal. One
subtracted. Odd and even codes are plotted in red and blue.
Direct measurement of the voltage range for each code is time consuming due to
the time needed to average out noise, and error prone due to the extreme
precision required. Fortunately a statistical test is available which can be
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automated and requires neither accurate voltage control nor low noise at the
input. All that is required is a time varying input signal sweeping though the ADC
input range, which has a smooth and moderately flat histogram. Provided that
the input signal is not synchronized to the pixels, the probability of generating
any given output code is fairly uniform and slowly varying.
Figure 4: Histograms for 24 ADCs generated from many raw dark frames from a Teledyne
H2RG CMOS multiplexor. Input offset is incremented for successive frames to synthesize a
flat input histogram from the one shown in Figure 7.
Figure 5: Histograms of DNL errors shown in Figure 4.
A sufficient number of samples is acquired so that the random fluctuation in the
number of occurrences in each output code is an acceptably small percentage of
the number of occurrence. Assuming Poisson statistics, a signal spanning all 2 16
output codes will achieve 1% rms error, when a histogram is made from a data
set containing 655 megapixels per channel. A perfect ADC will produce a smooth
histogram with only large-scale structure, due to the input signal shape.
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Most real ADCs exhibit high spatial frequencies in their histogram. For successive
approximation converters, which match the input signal to a set of binary
weights whose relative values are never perfect, DNL errors tend to occur with
periodicities that are powers of two. Figure 3 shows the distribution of DNL
errors for an ADC with marginal DNL, with some very narrow (but not entirely
missing) codes. As is common, narrow codes are largely compensated by the
next code being correspondingly wider so that the cumulative deviation of the
transfer function may not be large. A NIR detector was used to generate the
nearly uniform distribution of input signals as described in section 3.2.2.
Figure 4 shows histograms for all 24 channels measured concurrently. Each
histogram has been divided by a heavily smoothed version of itself to remove the
shape due to the input signal and integral non-linearity of the ADC. These occur
on much longer scales than DNL. Subtracting one from the normalized histogram
leaves the fractional variation from nominal code width. A histogram of these
code-width errors (yes, a histogram of a histogram) is useful to summarize
performance as illustrated in Figure 5. Clearly, ADC performance varies
considerably in this controller (from Astronomical Research Cameras Inc.).
Several ADCs behave marginally, yet others nearby have remarkably low errors.
All data acquisition and analysis was automated. Analysis scripts are provided in
the appendices.
Figure 6: DNL errors in raster format for a 16 bit ADC’s with mid range performance.
The plot in Figure 3 has 216 X-axis values, since DNL histograms must be made
with a bin width of one. 216 data points cannot be displayed without making data
points almost invisibly small or the page very large. A simple work-around is to
format the data as a 256 column by 256 row raster as shown in Figure 6. For
successive approximation converters, the errors tend to align along rows and
columns in a pattern that is characteristic of the converter architecture. Only
when the data were presented in this format did we find localized features,
which reproduced between converters.
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3.2.1 Generating flat histograms without a detector
There are a many ways to generate signals with fairly flat histograms. One could
inject a free running triangle wave into the signal path, setting the frequency of
the triangle wave so that at least 100 cycles occur during the data acquisition
period to keep the errors below 1% where a partial cycle is recorded.
When injecting a triangle wave into a CDS processor, it is necessary to alternate
between zero and the triangle wave values (e.g. with an analog switch), to
provide a simple emulation of the reset level (zero in this case) and signal. The
switch needs to be driven by an appropriate pixel synchronous clock. Other
options exist which utilize the (dual slope) integrator with a small offset and no
reset to make a long ramp. Details will be system specific so we focus instead on
techniques that can be employed in the field for any detector system.
3.2.2 Generating flat histograms with a CMOS detector
Raw frames from CMOS multiplexors exhibit a broad pixel-to-pixel variation in
offset voltages due to the variation in thresholds of the MOSFETs that buffer
each photodiode. Normally this fixed pattern is removed by the CDS arithmetic.
Figure 7 shows the histogram for a raw frame from a Teledyne H2RG multiplexor.
Adjusting the input offset voltage shifts the histogram horizontally. For
conversion gain near 1 e-/ADU, FWHM is approximately 3000 ADU. The
parabolic shape in the semi-log plot down to about 1% of peak is characteristic of
a normal distribution, for which a shift smaller than the FWHM produces a flattopped histogram in the combined data set. In practice, DNL error in the DAC
used for generating the offsets produces small variations in the shifts, which in
turn creates low amplitude ripples in the input histogram. These are readily
recognized since their periodicity is the DAC offset. They can be normalized out
without impacting DNL measurements, since these histogram ripples vary much
more slowly with signal amplitude than the ADC DNL errors.
Figure 7: Left: raw frame from a CMOS 3T mux (Teledyne H2R)G showing the fixed a
pattern due to buffer MOSFET threshold variations. Right: histogram. FWHM ~3000 ADU.
3.2.3 Generating flat histograms with a CCD
Illuminating a CCD while reading out produces a linear signal ramp provided that
the CCD was erased prior to the start of the readout. The combination of flux
and line rate must be adjusted to reach the maximum ADC value (or blooming) at
the end of the readout. For a typical well capacity (150 ke-) and number of lines
(eg. 4096) the mean charge accumulated per line will be 36 e-. Shot noise in first
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line will be only 6 e-. For the histogram to be flat we require the change in mean
from line to line to be less than the FWHM of the histogram of individual lines
(2.35 times the shot noise added in quadrature with read noise). In this example,
this condition is reached after ~7 lines. However, DNL needs to be tested at low
signals where the single ramp leaves gaps in the histogram since this is the
portion of the ADC transfer function used by faint signals. One solution to this
problem is to adjust the video output offset (usually set by a DAC) between
successive frames. Six frames should be sufficient to fill in the gaps. Multiple
frames are usually needed anyway to build up the required statistical accuracy.
Another solution is to disable the integration of the post reset level and only
integrate on the signal. The noise will increase by at least √𝑘𝑇𝐶 where k is
Boltzmann’s constant, T is CCD temperature and C is CCD sense node capacitance
(~15 to 50 fF). For 8µV/e- output node sensitivity, √𝑘𝑇𝐶 equals 42 e- which will
easily flatten the histogram. In practice, Correlated Double Sampling also rejects
low frequency components of bias voltage and preamp input noise. These noise
sources will reappear and provide additional smoothing of the histogram.
3.3
Output noise and offset
The DNL measurements above did not require low noise input signals. If using a
dual slope integrator the combined noise of the integrator, post-amp and ADC
can be measured by reading out with normal timing but never closing the
“integrate” switches (see Figure 1). The time delay where the integration
normally occurs is still executed so that the pixel timing remains unchanged.
Integrator reset may be pulsed as usual or be held closed. This test provides a
simple way to isolate noise in the outputs from noise in the preamp or that
coming from the CCD. The output offset/drift can also be checked by this test
without the influence of the preamp.
We have used the same test for the version of the video board sold by ARC Inc.
for use with NIR detectors. It employs a single-slope integrator to sample the
video and limit the noise bandwidth.
3.4
Input noise
CCD systems employing black level clamps can test the noise from the clamp
onwards by holding the clamping switch closed through the entire readout. If
this is not available, then human intervention is needed to disconnect the
detector and replace it by a loopback of ground or other signals as described
below. The SIDECAR ASIC (used by some to control NIR detectors) has a
multiplexor at the input that allows a shorted input test to be performed.
LOOPBACK TESTS
These require that the controller be disconnected from the detector. Readers
are cautioned that exposed pins on the connector to the detector place it at risk
and that full ESD precautions should be observed.
4.
4.1
Shorted inputs
It is convenient to have pre-wired connectors available to short video to ground
(both signal and reference inputs, if differential) right at the video card, or as
close as possible. A second connector for the end of the cable (if any) can be
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used to determine whether the noise changes depending on cable length,
shielding or other wiring faults. We use the word “noise” rather loosely here to
cover random noise, fixed patterns, and moving patterns. The latter are more
accurately described as “interference” since they can be traced to some emitter.
These shorted input tests will not reveal current-noise at the preamp input. A
more rigorous test would be to use a resistance to ground which matches the
expected output resistance of the detector, typically 100-300 ohms for FET
buffered CCD outputs, or much as 7 kilohms for some unbuffered CCD outputs.
4.2
Other ground loopbacks
The shorted input test generally uses a ground from the video board to feed back
into the video preamplifier. Especially in larger systems, noise can originate
from differentials between points in the system, which are all nominally
“ground”.
Differentials between bias voltage ground and video ground are
likely to be problematic. In looking for ground differentials it can be useful to
loop back multiple grounds such as those used for biases, high voltage backside
bias (often on a different card), clock ground, digital ground, shield potential, or
the video ground on a neighboring card. If multiple signals are connected to
different channels on the same card, it can be possible to find correlations.
4.3
Bias loopback
Since CDS subtraction for NIR detectors is performed on the timescale of frames
not pixels, the video outputs are DC coupled and employ a programmable offset.
Bias voltages are generally of similar magnitude to the video offset, which will
need to be re-adjusted when each new bias is looped back to the video. Most
CCD controllers use AC coupling which allows any static voltage (biases, clocks, or
even power supplies) to be looped back to the video without overdriving the
video input.
The extent to which biases couple through the detector determines how stable
they need to be. Bias loopback tests offer the opportunity to measure the
transfer function of the detector (gain versus frequency): biases can be
modulated while the video is digitized. CCD’s attenuate biases voltage
fluctuations, with the exception of Reset Drain but Correlated Double Sampling
suppresses this variation. The Teledyne H2RG has stronger bias couplings
(DSUB=1, VDDA=0.4, BIASGATE and BIASPOWER=1.4). One can estimate the
impact on total noise by subtracting the shorted input noise in quadrature from
the bias loopback noise then scaling by the coupling measured at the pixel rate.
The response of the detector to bias modulation is typically flat up to some
corner frequency so measurement at a few frequencies is sufficient. For CCDs
where bias coupling is weaker, it is often sufficient to compare current loopback
noise with a reference measurement from a working system to simply show that
the bias noise is “normal”.
4.4
Clock loopback
A clock loopback test can be employed to check the noise on clocks, provided
that the particular clock is “stopped” while being looped back. Most clock drivers
employ different DACs to generate high and low clock levels so it is necessary to
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repeat the loopback test for both levels.
The clock coupling to the video can be derived by measuring the feedthrough
pulses on the video with an oscilloscope, or by using the oscilloscope mode for a
Digital CDS system. If neither is available applying a square wave to the clock in
question with transitions at the times where CCD_Reset and charge dump would
normally occur will produce a “signal” from the CDS processor which is due to the
clock feedthrough. (Be careful to subtract the value produced when the clock is
stable).
Clock feedthrough is typically small, with Reset Gate (RG) and Summing Well
being the most prominent. For example, RG feedthrough begins as it crosses the
reset FET’s switching threshold. One typically sees about 200mV feedthrough
when RG_low is ~0 V and reset switch threshold is ~5V. Then RG feedthrough
would be 0.04. RG is held low throughout the CDS process so only the low level
needs to be looped back. As long as noise during the RG_low loopback test is
only a few times the shorted-input noise, then RG contribution will be only a few
percent. Most clock and bias noise contributions need to be this low since there
are many such sources, which can become significant when combined.
4.5
Power supply loopback
Power supply loopback can be used to measure noise falling with the CDS
passband. To assess the impact on read noise, the Power Supply Rejection Ratio
must also be measured. This will be strongly dependent on frequency and thus
needs to be measured at the pixel rate. Modulation of the power supply can
generally be achieved by switching an additional load current, to produce a few
hundred millivolts of supply voltage change synchronized to the pixel: the
additional load is switched on when charge dump would normally occur and
switched off when CCD Reset would normally occur. The magnitude of the
supply modulation can then be inferred from the change in signal seen during
power supply loopback, and the magnitude of the response can be inferred from
the CDS signal with shorted input (i.e. taking the difference between the cases
where supply is modulated and not modulated.)
The test described above is applicable to power supply noise that couples directly
into the video chain. To measure supply coupling via bias or clock voltages one
simply compares the response with and without power supply modulation using
the bias loopback instead of shorted video input.
5.
CONCLUSIONS
Video chain noise can be measured automatically with the detector in place and
DNL can be measured by using the detector as the test signal generator. Noise
contributions from clocks and biases require replacing the detector with direct
loopback wiring but no other test equipment. Only when checking the bias and
clock levels, and clock timing is external test equipment required.
ACKNOWLEDGEMENTS
We thank Greg Bredthauer at Semiconductor Technology Associates for
supplying the data in Figure 2.
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