Oregon Institute of Technology
Embedded Systems Engineering Technology
CST 407
Lab4 A
Design with SOPC
By Tim Endicott
Adding PIO interface using Quartus II System Schematic
Objectives:
1) Use SOPC builder to add PIO ports to system 0
2) Add interface signal to VHDL/Verilog Module
3) Link block diagram between SOPC system and VHDL/Verilog Module
The purpose of this lab is to familiarize the student with connecting
a SOPC system to a VHDL Verliog module
The second part of the LAB will focus on writing characters to An LCD screen
Procedures:
1) Open the BASE system 0 design project (LAB0)
2) Click on the SOPC builder icon.
3) Click on microcontroller peripherals and select PIO
4) Select type output and choose 6 bit data width. Select finish
5) Right click on the new PIO and rename it to CHARADD
6) Create another PIO output, make it 8 bits this time. Name it LCDDAT
7) Click on Generate
8) Close SOPC builder
9) Add the newly created LCDDAT and CHARADD .VHD files to the Quartus
project.
10) Open the system0 block diagram. Right click and update system block.
Choose selected symbols or blocks
11) Delete all previously connected pin assignments
12) Right clock on system0 and select generate pins for symbol ports
13) Right clock on the schematic file name and choose set as top module.
14) Compile Design, close project.
15) Open the DE2_LCM_test Terasic LCD project.
16) Create two inputs in the top module
Input CHAR_ADDRESS [5:0]
Input LCD_DATA_IN[8:0]
17) Make necessary changes to interface the new LCD_DATA_IN. HINT: This input
will replace the previous LCM_DATA somewhere in the Terasic LCD top
module (Note to Ralph.., solution will be added in Part B of this LAB)
18) Right click on the top module file and select create symbols for current file
19) Save and close the Quartus Project
20) Re-Open the LAB4 project and open the system0 block diagram
21) Copy all verilog files from the Terasic example program directory and put them
into the lab4 folder. Also copy the schematic .bsf file from the LCD project
directory
22) Add DE2_LCM_Test.v to the project
23) Open the schematic for system 0. Add the Generated block diagram from the
Terasic LCD project to the System 0 schematic page.
24) Right clock on LCD system block file and select generate pins for design.
25) Connect wires to the LCD_DATA_IN and CHARADDRESS signals to the
LCD_DAT and CHARADDR between the two blocks
26) Compile the Design
27) Check the RTL to make sure that both modules are synthesized
28) If finished early start on the second Part of the LAB for adding software
interface to the Terasic LCD screen