VLSI & Optical fiber LAB
Exparement No.: 1
Object: Design & stimulate Bridge Rectifier with & withought filter.
Theory:
A bridge rectifier makes use of four diodes in a bridge arrangement to achieve fullwave rectification .A diode bridge is an arrangement of four (or more) diodes in a
bridge configuration that provides the same polarity of output for either polarity of
input . When used in its most common application, for conversion of an alternating
current (AC) input into direct current a (DC) output, it is known as a bridge
rectifier. A bridge rectifier provides full-wave rectification from a two-wire AC
input.
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Bridge Rectifier Without Filter
Output Waveform
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Bridge Rectifier With Filter
Waveform
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Result:
The full-wave bridge serves to convert an AC input into a pulsating DC output.
The capacitor is used to remove ripple from DC output thus capacitor works as a
filter.
VLSI & Optical fiber LAB
Exparement No.: 2
Object: Design & stimulate RC coupled amplifier with & without feedback.
Theory:
In RC coupled amplifier resistors & capacitors are use with transistor for
amplification.
Voltage Gain (G) = Vo/Vi
Where
Vo = Output voltage
Vi = Input voltage
Bandwidth of the amplifier = f2 - f1 KHz
Where
f1 = lower cut-off frequency
f2 = upper cut-off frequency
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RC Coupled Amplifier Without Feedbak
Output Waveform
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Frequency Response curve
Phase response curve
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RC Amplifier with Feedback
Output Waveform
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Frequency Response curve
Phase response curve
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Result:
In RC coupled amplifier the gain of the amplifier with feedback is less than the
gain of amplifier without feedback & the output is out of phase with respect to
input.
VLSI & Optical fiber LAB
Exparement No.: 3
Object: Design & stimulate inverting & no inverting amplifier in closed loop
configuration (close loop gain 10) using OpAmp.
Theory:
Inverting Amplifier:
In inverting amplifier input is applied to the inverting terminal. Inverting amplifier
uses negative feedback to invert and amplify a voltage. The R1, R2 resistor
network allows some of the output signal to be returned to the input. Since the
output is 180° out of phase, this amount is effectively subtracted from the input,
thereby reducing the input into the operational amplifier.
Open loop gain:
A= - (R2/R1)
Noninverting Amplifier:
In noninverting amplifier input is applied to the noninverting terminal.
Open loop gain:
A= [1+ (R2/R1)]
VLSI & Optical fiber LAB
Inverting Amplifier
Output Waveform
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Non inverting Amplifier
Output Waveform
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Result:
In inverting amplifier output is out of phase by 180 with respect to input voltage.
In non inverting amplifier output & input voltage are in same phase.
VLSI & Optical fiber LAB
Exparement No.: 4
Object: Design & stimulate Astable mulivibrator using 555 timer IC.
Theory:
In astable mode, the 555 timer puts out a continuous stream of rectangular pulses
having a specified frequency. Resistor R1 is connected between VCC and the
discharge pin (pin 7) and another resistor (R2) is connected between the discharge
pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common
node. Hence the capacitor is charged through R1 and R2, and discharged only
through R2, since pin 7 has low impedance to ground during output low intervals of
the cycle, therefore discharging the capacitor.
Charging time of capacitor: Tc =0.639(R1+R2)C
Discharging time of capacitor: Td =0.639(R2)C
Total time period: T=0.693(R1+2R2)C
Frequency of oscillation: f=1.44/(R1+2R2)C
Duty Cycle: D= [(R1+R2)/(R1+2R2)]*100%
VLSI & Optical fiber LAB
Astable Multivibrator Using 555 Timer
Waveform
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Result:
Thus astable multivibrator provides rectangular pulses having a specified
frequency.
Comments:
Astable multivibrator with 50% duty cycle is known as square wave oscillator.
Practical astable multivibrator with 50% duty cycle can be made using a diode in
parallel to resistor R2.
VLSI & Optical fiber LAB
Experiment No.:5
Object: Design & stimulate triangular wave generator.
Theory:
Triangular wave generator can be designed with help of square wave generator &
integrator.On intigrating square wave we get triangular wave.The frequency of
triangular wave is similar to the frequency of square wave.
Frequency of triangular wave is f0=(R1/4R2.R4.C1)
Triangular wave generator Circuit & Output Waveform
Result: Thus triangular wave can be generated using square wave generator.
VLSI & Optical fiber LAB
Experiment No.:6
Object: Design & stimulate 4:1 multiplexer.
Theory: A multiplexer or mux is a device that selects one of several analog or
digital input signals and forwards the selected input into a single line.
A multiplexer of 2n inputs has n select lines, which are used to select which input
line to send to the output.4:1 multiplexer has 2 select lines 4 input lines & 1out put
line.
Truth Table:
S1
0
0
1
1
S0
0
1
0
1
output
A
B
C
D
The Boolean equation for a 4-to-1 multiplexer is:
Circuit diagram of 4:1 Multiplexer
VLSI & Optical fiber LAB
Output Wave Form:
Result: Thus 4:1 mux is a device that selects one of input from 4 inputs and
forwards the selected input into a single line.
VLSI & Optical fiber LAB
Experiment No.:7
Object: Design & stimulate 2 bit magnitude comparator.
Theory: A 2 magnitude comparator is electronic device that takes two numbers as
input in binary form and determines whether one number is greater than, less than
or equal to the other number.
Truth Table:
A
0
0
1
1
B
0
1
0
1
A>B
0
0
1
0
A=B
1
0
0
1
A<B
0
1
0
0
Circuit Diagram & Output Waveform
Result: Magnitude comparator compares the input & determines whether one
number is greater than, less than or equal to the other number.
VLSI & Optical fiber LAB
Experiment No.:8
Object: Design & stimulate Binary to Gray code converter.
Theory: The binary numeral system, or base-2 number system, represents
numeric values using two symbols, 0 and 1. The reflected binary code, also known
as Gray code is a binary numeral system where two successive values differ in
only one bit. Binary to Gray code converter converts binary code into gray code.
Circuit diagram & output waveform
Result: MSB of Gray & Binary code is same. Binary to Gray code converter
converts binary code into gray code.
VLSI & Optical fiber LAB
Experiment No.:9
Object: Design & stimulate Gray to Binary code converter.
Theory: The reflected binary code, also known as Gray code is a binary numeral
system where two successive values differ in only one bit. The binary numeral
system, or base-2 number system, represents numeric values using two symbols, 0
and 1. Gray to Binary code converter converts gray code into binary code.
Circuit diagram & output waveform
Result:MSB of Gray & Binary code is same. Gray to Binary code converter
converts gray code into binary code.
VLSI & Optical fiber LAB
Experiment: 10
Object:Write VSDL code for Basic gates, Universal gates, ex-gates & simulate using XILINX
ies.
Theory:
1. Code: AND Gate
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ravi;
architecture Behavioral of ravi is
begin
c <= a and b;
end Behavioral;
VLSI & Optical fiber LAB
Output waveform
2.Code for OR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
VLSI & Optical fiber LAB
end ravi;
architecture Behavioral of ravi is
begin
c <= a or b;
end Behavioral;
Output Waveform
3.code for XOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
VLSI & Optical fiber LAB
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ravi;
architecture Behavioral of ravi is
begin
c <= a xor b;
end Behavioral;
Output Waveform
4.code for NAND gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
VLSI & Optical fiber LAB
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ravi;
architecture Behavioral of ravi is
begin
c <= a nand b;
end Behavioral;
VLSI & Optical fiber LAB
Output Waveform
5.Code for NOR gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ravi;
VLSI & Optical fiber LAB
architecture Behavioral of ravi is
begin
c <= a nor b;
end Behavioral;
Output Waveform
6.Code for XNOR:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
VLSI & Optical fiber LAB
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end ravi;
architecture Behavioral of ravi is
begin
c <= a xnor b;
end Behavioral;
Output Waveform
VLSI & Optical fiber LAB
7.code for NOT gate:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ravi is
Port ( a : in STD_LOGIC;
b : out STD_LOGIC);
end ravi;
architecture Behavioral of ravi is
begin
b <=not(a);
end Behavioral;
VLSI & Optical fiber LAB
Output Waveform
Result: We have design & simulate different logic gates using XILINX ies.