CPSC 3300 Fall 2014 -- Exam 1
Name: __________________
No calculators or other aids.
1. Give the power of 10 associated with these prefixes. (1 pt. each)
giga
2.
________
kilo
________
mega
________
micro ________
milli ________
nano
________
pico
________
tera
________
Matching -- technology/performance terms. Write the correct term from the
list into each blank. (1.5 pts. each)
embedded computer
desktop computer
server
supercomputer
a. _________________
datapath
transistor
wafer
yield
throughput
CPU time
CPI
workload
arithmetic mean
harmonic mean
geometric mean
speedup
Linpack
Whetstone
Dhrystone
SPEC
c. _________________
a computer that provides computation, file storage,
and/or printing to multiple users across a network
a computer that is used inside another device and that
runs one or more predetermined applications
a semiconductor device that acts as an on/off switch
d. _________________
work done per unit time
e. _________________
used to summarize a set of normalized performance values
f. _________________
a synthetic systems (i.e., integer rather than flt. pt.)
benchmark from the 1980s, which is still in use today
b. _________________
3. Give the CPU time equation and define the terms you use. (5 pts.)
4. Find the execution time for a program that executes 6 billion instructions on
a processor with an average CPI of 2 and a clock frequency of 3 GHz. (5 pts.)
5. For the following workload and cycle values, find the average CPI. (3 pts.)
type
| freq cycles
-------+-------------alu
| 0.2
1
ld/st | 0.3
2
branch | 0.5
4
CPI = _____________________________
6. If a process shrink for the computer design in question 5 could increase the
clock frequency from 2GHz to 3 GHz and a new compiler could reduce the number of
instructions to 2/3 of the original total and alter the instruction frequencies
in the following manner, what would be the total speedup? (9 pts.)
type
| freq cycles
-------+-------------alu
| 0.5
1
ld/st | 0.2
2
branch | 0.3
4
7. Consider enhancing a scalar machine by providing a vector mode, which is 6 times
faster than the normal mode of operation. If the percentage of vectorization is
40%, what is the overall speedup using Amdahl’s Law? (9 pts.)
Extra credit. What would the percent of vectorization need to be to attain an
overall speedup of 3 if the vector mode is 6 times faster than the normal mode?
(4 pts.)
8. Matching -- logic terms. Write the correct term into each blank. (1.5 pts. each)
minterm
sum of products
don't care
glitch
race condition
circuit depth
fan-in
fan-out
half adder
full adder
decoder
multiplexer
ALU
PLA
latch
flip-flop
register
shift register
RS latch
JK flip-flop
a. _________________
unused value that can be arbitrarily assigned 0 or 1
b. _________________
undesired signal lasting only a short time
c. _________________
a form of logical representation that employs a
logical OR of product terms
where the output of a circuit depends on small
differences in signal timing
the number of gates in a circuit that form the longest
path from any input to any output
a circuit in which n select values route one of 2**n
input values to the single output
a memory element in which the stored state can only
change once per clock cycle
a circuit that connects several flip-flops into a linear
structure where the output of each flip-flop can be
the input to either of its neighbors
d. _________________
e. _________________
f. _________________
g. _________________
h. _________________
9. Simplify the following Karnaugh maps of function F. (3 pts. each)
\ BC
A \ 00
01
11
10
+----+----+----+----+
0 | 1 | 0 | 0 | 1 |
+----+----+----+----+
1 | 1 | 1 | 0 | 0 |
+----+----+----+----+
\ CD
AB \ 00
01
11
10
+----+----+----+----+
00 | 0 | 1 | 0 | 0 |
+----+----+----+----+
01 | 0 | 1 | 1 | 0 |
+----+----+----+----+
11 | x | x | x | x |
+----+----+----+----+
10 | 0 | 1 | 0 | 0 |
+----+----+----+----+
F = fn(A,B,C) = _________________________
F = fn(A,B,C,D) = _______________________
10. Consider A*(B+C) = A*B + A*C. Show by truth table that this is true. (8 pts.)
A
B
C
| B+C | A*(B+C) | A*B | A*C | A*B + A*C
--------------+-------+---------+-------+-------+-------------
11. Give a circuit implementation for an XOR circuit using AND, OR, and NOT gates.
(8 pts.)
a b | XOR
-------+------0 0 |
0
0 1 |
1
1 0 |
1
1 1 |
0
Extra Credit. Give the implementation of an XOR circuit using only NAND gates.
(3 pts.)
12. Consider a state machine that outputs a 1 whenever it recognizes a third 1 in
its binary input stream. That is, the state machine behaves like this:
input (I):
output (S):
0 1 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1
0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1
(For this trace, the state machine starts in a state which records no prior 1s.)
(a) Give the state diagram. (6 pts.)
(b) Give the state transition table with input I, current state, next state,
and output S. (6 pts.)
(c) Give the simplified logic expressions for next state values and S. (6 pts.)
Extra credit. Draw the circuit diagram for the state machine in question 12.
(3 pts.)