CEC 222 Digital Electronics Lab Spring 2015 Lab 4: Arithmetic Logic Circuits Learning Objectives: Review simple arithmetic logic circuits. Introduce the concept of modularity in digital logic design. Reinforce 2’s complement addition (and subtraction). Lab Overview: A half-adder adds two 1-bit numbers to provide a 2-bit result. A full-adder includes a third input to the halfadder, namely a carry-in, and also provides a 2-bit result. Experiment 1 builds a full-adder and experiment 2 encapsulates this full-adder module to realize a 4-bit 2’s complement adder. A separate circuit for overflow is also constructed. The extra credit experiment develops overflow detection. YOUR NAME(S) Lab 04 Page 1 of 8 CEC 222 Digital Electronics Lab Spring 2015 Pre-Lab (10%) A 1-bit full-adder adds three 1-bit numbers, say, A, B, and Cin to produce a 2-bit result (Cout, Sum). Task 1. A + B + Cin Cout Sum Considering the 1-bit full-adder shown in Figure 1, wherein A, B, and Cin are inputs and Cout and Sum the outputs, fill in Sum Figure 1 A 1-bit full adder the Predicted Output columns of Table 1. Task 2. Develop “simplified” (e.g., SOP, POS, XOR, …) Boolean expressions for both Cout and Sum (below) and fill in the Predicted Outputs columns of Table 1. Cout = _____________________ Sum = _____________________ By cascading four 1-bit adders, we can construct a 4-bit adder, as illustrated in Figure 2, which adds a 4-bit number A (= A3A2 A1A0 ) to another 4-bit number B (= B3B2 B1B0 ) to realize a 4-bit sum S (= S3S2S1S0 ). A3 B3 Cout3 1-bit Full Adder S3 A2 B2 Cin3 Cout2 1-bit Full Adder A1 B1 Cin2 Cout1 S2 1-bit Full Adder A0 B0 Cin1 Cout0 S1 1-bit Full Adder Cin0 S0 Figure 2 A 4-bit adder. We could think of these 4-bit binary patterns as representing unsigned decimal numbers, thus allowing both A and B to vary from 0 (=0000) to 15 (=1111). Alternatively, if we interpret the 4-bit binary patterns as 2’s complement numbers both A and B could vary from -8 (=1000) to +7 (=0111). Task 3. Considering A and B to be 2’s complement numbers fill in ALL of the missing elements in the Inputs and Predicted Outputs columns of Table 2. YOUR NAME(S) Lab 04 Page 2 of 8 CEC 222 Digital Electronics Lab Spring 2015 Experiments (90%) EXPERIMENT 1. DEVELOPING A 1-BIT FULL ADDER In this first experiment you will be implementing, within your FPGA, the Boolean expressions for the 1-bit full adder that you designed in the pre-lab. It is a good idea to start each lab in a new folder (e.g., Lab_4). Step 1.a: Create the schematic of a 1-bit full adder Open ISE and create a New Project named “Full_Adder” (see Lab 3 for details on creating a new project) of Top-Level source type “Schematic.” Add to your project, a “New Source” of Type “Schematic” with a file name of “One_Bit_Adder” Build your circuit(s) to realize the Boolean expressions for both Cout and Sum, which you designed in the pre-lab. Label your input ports as A, B, and Cin and the output ports as Cout and Sum. As before, add a title (which includes your name(s)) and label signals where appropriate. Task 4. Take a screen shot of your schematic and insert it into Figure 3. Figure 3 Schematic of a 1-bit adder circuit. Step 1.b: Route the signals (A, B, Cin, Sum, and Cout) to appropriate pins on the FPGA. Create a new Constraints file named “adder,” with the following connectivity (copy text below): # Inputs: NET "A" NET "B" NET "Cin" Input “A” to SW2 = FPGA pin K3, Input “B” to SW1 = FPGA pin L3, Input “Cin” to SW0 = FPGA pin P11, YOUR NAME(S) LOC = "K3"; # SW2 LOC = "L3"; # SW1 LOC = "P11"; # SW0 # Outputs: NET "Cout" LOC = "M11"; # LED1 NET "Sum" LOC = "M5"; # LED0 Lab 04 Page 3 of 8 CEC 222 Digital Electronics Lab Spring 2015 Output “Cout” to LED1 = FPGA pin M11, and Output “Sum” to LED0 = FPGA pin M5. Step 1.c: Generate the bit file and program the FPGA. Select the In the pane below double-click on “Synthesize,” then “Implement Design” and finally “Generate tab and click on “One_Bit_Adder.” Programming File.” Turn on your BASYS 2 FPGA board and start the Adept software Browse to the “One_Bit_Adder.bit,” which you just created and load it into the PROM. Turn the power to your FPGA board OFF and back ON in order to load the new design. Task 5. Vary the switches SW2 (=A), SW1 (=B), and SW0 (=Cin) to enter every possible combination of inputs and record the values for Cout and Sum values in the Measured Output columns of Table 1. (SW2) A 0 0 0 0 1 1 1 1 EXPERIMENT 2. Inputs (SW1) B 0 0 1 1 0 0 1 1 Table 1 Truth Table for a 1-bit Adder Measured Output Predicted Output (SW0) (LED1) (LED0) Cout Sum Cin Cout Sum 0 1 0 0 1 1 0 1 0 1 BUILDING A 4-BIT ADDER FROM FOUR 1-BIT ADDERS As engineers, we often face a large problem, which hopefully can be decomposed into multiple smaller problems. It is always a good idea to build and test smaller/simpler pieces as you proceed rather than building it all at once and hoping for the best. Herein, we will “modularize” the 1-bit adder and use it as a building block to realize a 4-bit adder. Step 2.a: Create a 1-bit Adder Symbol Return to ISE and select Tools -> Symbol Wizard from the main menu toolbar. YOUR NAME(S) Lab 04 Page 4 of 8 CEC 222 Digital Electronics Lab Spring 2015 In “Pin name source,” select “Using Schematic” and choose “One_Bit_Adder,” and then click on “Next” In the “Pin Page” that appears next, change the three inputs to be on the Right Side and the two outputs to the Left Side and then click on “Next.” Do not change anything on the “Layout Page” or “Preview Page” that follows. Save and then close the “One_Bit_Adder.sym” window, which will open after you finish with the “Preview Page.” Step 2.b: Create a 4-bit adder (see Figure 2). Close the One_Bit_Adder.sch window. Right-click on the project “Full_Adder” and add to your project, a “New Source” of Type “Schematic” with a file name of “Four_Bit_Adder” Select the Symbols tab and enter “One_Bit_Adder” in the “Symbol Name Filter” field Select the One_Bit_Adder which should appear in the Symbols pane and add it to your schematic four times. The leftmost adder corresponds to your most significant bit (MSB) and the rightmost to your LSB. Add input ports and output ports to replicate, as best you can, the presentation of Figure 2. One difference => Ground Cin0 Task 6. Capture a screenshot of your completed 4-bit Adder schematic and insert it into Figure 4. Figure 4 A schematic of the 4-bit adder. YOUR NAME(S) Lab 04 Page 5 of 8 CEC 222 Digital Electronics Lab Spring 2015 Step 2.c: Route the signals (A, B, Cin, Sum, and Cout) to appropriate pins on the FPGA. Update the Constraints file “adder.ucf” (previously created) to provide the following connectivity (link to new version of “adder.ucf”): Input “A3 to A0” to SW7 to SW4, Input “B3 to B0” to SW3 to SW0, Output “Cout3” to LED7, and Output “S3 to S0” to LED03 to LED0. Step 2.d: Program the FPGA with the file “Four_Bit_Adder.bit” Follow the steps described in Step 1.c: to Synthesize, Implement, and Generate a Programming File. Turn on your BASYS 2 FPGA board and start the Adept software Browse to the “Four_Bit_Adder.bit,” which you just created and load it into the PROM. Turn the power to your FPGA board OFF and back ON in order to load the new design. Task 7. Vary the switches SW7 to SW4 (=A) and SW3 to SW0 (=B) to enter the combinations of inputs given in Table 2 and record the corresponding output values in the Measured Output columns. Cout A3 A2 A1 A0 S3 S2 S1 S0 B3 B2 B1 B0 Figure 5 Connectivity for the 4-bit adder. YOUR NAME(S) Lab 04 Page 6 of 8 CEC 222 Digital Electronics Lab Spring 2015 Report Requirements Truth table to be completed - Last column is optional. Table 2 Truth Table fora 4-bit adder Predicted Output S Inputs B A Binary Decimal Binary Decimal 0000 0101 1011 1011 0101 0011 1000 1001 0 1111 0010 0010 1110 0110 1101 0111 0001 -1 -8 Cout3 +7 0 Binary Decimal 1111 -1 Overflow Cout3 Measured Output Overflow S (Extra Binary Decimal Credit) Question 1. Define (in words) the concept of overflow, with respect to 2’s complement addition? ________________________??? Question 2. Is overflow the same as MSB carry out? YES or NO Question 3. Considering the values of A and B given in Table 2, for which cases (i.e., row) do you expect overflow to occur? ___________________??? Optional Exercise(s) (+10% Extra Credit) EXPERIMENT 3. DEVELOP OVERFLOW CIRCUITRY Overflow is a crucial concept when performing 2’s complement arithmetic. In this section of the lab you will develop the additional circuitry necessary to detect when overflow has occurred in your 4-bit adder. Question 4. In the case of our 4-bit adder, what is the Boolean expression for overflow? Overflow = ???? Step 3.a: Add an Overflow output bit to your the existing “Four_Bit_Adder.” Add the necessary logic to implement the expression for overflow, from your answer to Question 4. Use the name “Overflow” for the new output port Task 8. YOUR NAME(S) Capture a screenshot of your updated schematic and insert it into Figure 6. Lab 04 Page 7 of 8 CEC 222 Digital Electronics Lab Spring 2015 Figure 6 Schematic of the 4-bit adder with overflow detection Included. Update the Constraints file, “adder.ucf,” to connect the “Overflow” signal to LED6 (pin P4). Re-build, implement, and test (reload the new bit file) your updated 4-bit Adder. Task 9. Vary the switches SW7 to SW4 (=A) and SW3 to SW0 (=B) to enter the combinations of inputs of given in Table 2 and record the corresponding overflow values in the Overflow Output column. Reference Material APPENDIX A: XILINX ISE DESIGN SUITE INFORMATION [1] ISE Design Suite 14: Release Notes, Installation, and Licensing [2] General ISE Help [3] Xilinx ISE WebPACK Schematic Capture Tutorial YOUR NAME(S) Lab 04 Page 8 of 8