Carry Lookahead Homework
•
You are required to calculate the performance
of a 16-bit Carry lookahead adder similar to
the one discussed in class. The design has 2
options
1. assuming ripple carry is used inside each 4-bit
cell
2. Carry lookahead is used inside each 4-bit cell
•
•
9/12
Both cases use carry lookahead at predicting
4-bit boundary carries [c4, c8, c12]
Draw a table showing the delay of each adder
bit i.e. Sum0 - Sum 15; for each case
a0
b0
a1
b1
a2
b2
S0
3
S1
3
S2
3
S3
a3
b3
a7
b7
9/12
c4= G0 + c0 P0
S4
a4
b4
a6
b6
G0
2nd level
carry
lookahead
P0
4 units of delay
a5
b5
8-bit carry lookahead
adder (4-bit block is also CLA)
6
6
6
5
c5= g4 + c4.p4
Delays 1
4 1
S5
S6
S7
6
G1
P1
8-bit CLA – uses ripple carry inside 4-bit
0
block
a0
Result0 2
b0
a1
b1
a2
b2
a3
b3
2
a5
b5
a6
b6
a7
b7
9/12
3
Result2
5
Result3
7
4
6
4
a4
b4
Result1
c4
Result4
5
Result5
7
Result6
9
Result7
11
6
8
10
2nd level
carry
lookahead
Array Multiply HW
Refer to slide 31 in your ALU slides – Array multiply
• Using the cell, Draw the architecture of an 8 x 8 array
multiplier showing all connections
• Calculate all the delays for the multiplier, assume Ripple
add architecture. Each adder delay is 2 units, carry in to
carry out is 2 and AND gate is 1 unit delay. You need to show
the delays throughout the multiplier on your diagram. Give
any assumptions made and explain your answer..i.e .how
you arrived at the delays (delays are similar to adder delays)