METROLOGY CONSIDERATIONS FOR THROUGH SILICON VIA
MANUFACTURING
Ke Xiao, Sanjeev Singh, Holly Edmundson, John Allgair, Timothy Johnson
Nanometrics, Inc.
Hillsboro, OR, USA
kxiao@nanometrics.com
Daniel Smith, Yudesh Ramnath
GLOBALFOUNDRIES US INC.
Malta, NY, USA
daniel.smith@globalfoundries.com
ABSTRACT
In the past few years, interest in Through Silicon Via (TSV)
processing has grown significantly due to its crucial role in
enabling 2.5D and 3D IC advanced packaging integration.
TSV quality impacts the electrical performance of the final
packaged device. Key TSV process integration and
metrology challenges include: (1) Developed critical
dimension (DCD), in which the lithography CD of the
designed TSV must be measured precisely at a high
throughput; (2) Post-etch characterization after via
formation (3) After Cu-fill process to monitor for problems
such as underfill and voids; (4) Post Chemical-mechanical
planarization (CMP) topography due to the large size of the
TSV which can impact subsequent layers; (5) Subsequent
BEOL processing on a via-middle TSV can induce
additional thermal expansion of the TSV upwards into the
metal line stack as ‘pumping’. Development of simulated
mechanical and thermal stresses of the BEOL for large,
inline data collection of pumping reduction experiments is
needed to reduce this reliability risk [3]; (6) TSV reveal, in
which the backside silicon is removed to expose TSV
contacts (Cu) and accurate step height control is required to
ensure co-planarity.
This paper will discuss the above potential reliability risks
and metrology challenges in TSV process development, and
will focus on characterization of TSVs at various process
steps utilizing Scanning White Light Interferometry (SWLI)
metrology, which is a reliable, advanced solution for
multiple TSV metrology applications.
Key words: 3D Packaging, Interferometry, TSV,
Metrology.
INTRODUCTION
3D IC device packaging utilizing TSV is growing rapidly
due to its various advantages such as increasing the chip
density and decreasing the power consumption, as well as
meeting the demands of a growing market for faster, lighter,
smaller, and less expensive electronic products. The
characterization of TSVs is critical to ensure the reliability
of the subsequent processing steps and thereby the device
performance and lifetime. Via-middle TSV is emerging as
the integration scheme of choice for 3D stacking
applications as described in Figure 1.
Figure 1. Via-middle 3D TSV packaging process flow.
In the Via-middle TSV process, TSVs are created between
the FEOL and BEOL by a standard via formation process
that consists of lithography, etching, copper plating, and
CMP steps. After BEOL, thinning and TSV reveal are
performed on the backside of the silicon, which prepares the
TSV contacts for subsequent 3D or fan-out advanced wafer
level packaging. The main metrology requirements in the
Via-middle process are: the CD for the DCD stage, TSV
depth and top-CD for the etching stage, Cu fill of the via for
the plating stage, dishing and erosion for the CMP stage,
Cu-pumping for TSV BEOL reliability, and the Cu pillar
height for the reveal stage.
In the current industry, there are a variety of metrology
techniques used during processing for TSV packaging,
including but not limited to: Optical CD metrology by
optical microscope, film thickness metrology by
spectroscopic reflectometer (SR) and spectroscopic
ellipsometer (SE), CD metrology by CD-SEM and Crosssection SEM, topography metrology by profilometry and
AFM. However, there are some limitations in metrology
associated with those techniques, such as constraint of field
of view, inefficient throughput, destructive behavior, and
limited capability for single applications.
An alternative method is white-light interferometry
metrology. A single, scanning white-light interferometer
measurement will simultaneously capture not only the
optical information of the whole field of view but also the
topography information, enabling complete 3D metrology at
high precision and throughput.
SWLI METROLOGY FOR TSV PROCESS STEPS
1. Developed Critical Dimension (DCD)
In this step of the TSV process, a photoresist layer is applied
onto the wafer surface for standard photolithography
patterning by the conventional spin-coating method. The
photoresist layer is subsequently backed, exposed to UV
light and developed to form the desired patterns. The spincoat process may result in insufficient coating uniformity
and conformity and un-sharp or non-vertical edges due to
spin dynamics and rheology of resist solvent. The thickness
of coated photoresist layer could vary across wafer which
can lead to variation in developed CD. The exposure
conditions such as N.A., alignment, and focus can also
affect the patterning. The developed CD of the photoresist
can be measured by CD-SEM conventionally. Figure 2 is an
example image of a 6um developed CD from a CD-SEM.
Figure 2. An example image of 6um DCD from CD-SEM.
The typical throughput and precision for the CD-SEM is
about 24 wafers/hour and 1.2 nm. However, when the
photoresist side wall is not straight, it can be hard to
distinguish the accurate edge of the CD based on the TSV
image from CD-SEM.
Because the size of the CDs is large relative to the
wavelength of visible light, conventional optical imaging
can be used to measure these CDs as an alternative.
In Figure 3, the CD of a Focus Exposure Matrix (FEM)
wafer was measured using the optical image data from a
scanning white-light imaging interferometer which allows
us to measure the resist thickness simultaneously. The
typical precision and throughput of a scanning white-light
interferometer is up to 30 wafers/hour with a CD precision
of 5 nm and a height precision of 7 nm.
A FEM wafer is made by varying the depth of focus along
one axis and varying exposure dose along the other axis, and
for this test, there are two regions of interest printed in each
die: a dense TSV region and an isolated TSV region. The
CD data for both regions are presented in Figure 3.
Figure 3. FEM maps of developed CD from a scanning
white-light interferometer: the left map is from dense TSV
region and the right is from isolated TSV region. (Color
scheme represents the CD magnitude)
The white-light interferometer is also capable of capturing
the resist thickness simultaneously with the CD at each site,
providing additional process control information.
2. Etching
2.1
Standard TSV Measurements
The small CDs and high aspect ratios of through-silicon vias
make the characterization and process control crucial for the
reliability of wafer-level 3D packaging. After the pattern is
developed in the lithography step, the TSVs are formed
using a rapid alternating process (RAP) [6] with aspect
ratios typically 1:10 to 1:12. The most critical metrology
information is the depth of the TSVs. While the etch process
is fairly stable, there can be variability between different
chambers on the same tool. Unexpected variation in depth
can create problems during the TSV reveal process. Crosssection SEM can be used to monitor the etch process but it
is slow and destructive. Figure 4 shows the SEM cross
section image of a via with nominal depth of 55um and CD
of 6um.
Figure 4. (a) SEM cross-section image of a via with
nominal depth of 55um and CD of 6um. (b) The 10X
magnified SEM image near the top of the via. (c) The 10X
magnified SEM image near the bottom of the via.
A non-destructive alternative to X-SEM metrology is whitelight interferometry. Interferometry has the advantages of
being fast, accurate, and stable, and is therefore suitable for
use as an inline monitor. A scanning white-light
interferometer can be used to capture depth and CD in a
single measurement for the etch process, as in the DCD
measurement. Typical precision and throughput for 5 to
10um vias is better than 20 nm for depth and 20 nm for CD
at 23 wafers/hour.
Figure 5 shows a process control chart for CD and depth of
6X55um TSVs.
Figure 5. Control chart data of 6X55um TSV measurements
collected from a scanning white-light interferometry tool:
(a) Depth data of TSV. (b) Top CD data of TSV.
2.2
High Aspect-ratio TSV of size 3X50 um
TSVs with smaller CDs and higher aspect ratios are
currently being developed by the industry to reduce the
footprint of the vias on devices (especially important for
mobile devices), to reduce their impact on the later
processing steps (because Cu volume is directly related to
the extent of Cu pumping), and allow new bonding
strategies (face-to-face wafer bonding stacking method
allows thinner TSV wafer since wafers are heterogeneous
bonded to each other and can allow similar BEOL routing
and better thermal dissipation for bottom die). These smaller
vias, however, have their own process concerns. The higher
aspect-ratio causes difficulties in achieving continuous TSV
metallization and void free bottom-up filling, and they can
be more challenging to etch. Figure 6 shows an example
measurement of 3X50um vias using white-light
interferometry.
Figure 6. Examples of the results for 3X50um TSV. In this
figure, we have separated the image into two surfaces by
height to make the images more clear. (a) Measured
topography of vias bottom surface. (b) Measured
topography of vias top surface.
We summarize measurements from two 3X50um TSV
wafers in Table 1. Both wafers show similar results. The
range of depth across the wafer is approximately 0.5um and
the standard deviation of the measurements is approximately
40nm for both wafers.
3X50 um TSV
Samples
Mean Depth data of 13 Sites (µm)
Depth Std
Depth Range
1
0.036
0.508
2
0.041
0.488
Table 1. Measured Depth data for two wafer samples, 13
sites per wafer, 5 repeats.
2.3
TSV Inspection
In addition to providing high-resolution TSV metrology, a
scanning white-light interferometer can be configured for
3D TSV inspection. This allows the full wafer to be scanned
for blocked vias or vias with incomplete etch. The challenge
for 2D inspection of TSVs is that in a bright-field
measurement, an incompletely etched via looks the same as
a via etched to depth. Figure 7 (a) shows an image of part of
a shot that has been inspected for TSV etch. The dots are
TSVs that have been etched to the correct depth. Because
they are a little difficult to resolve, in Figure 7 (b) we show
the zoomed-in image of the region of interest indicated by
the red box in (a). You can see both dense and isolated via
patterning.
Figure 9. Tracking data of the height of filled TSVs as an
in-line monitor of wafer underfill problem. Two excursion
events associated with bath concentrations are evident.
Another important risk in the Cu-fill process is the creation
of voids. Some of the main causes of voiding include
instability of ECD bath (suppressor too high, inorganics too
low, etc), poor sidewall coverage of either barrier or seed
films (generally too thin), or extreme sidewall roughness
from either etch or oxide liner. Figure 8 shows a schematic
of a void in a via. Figure 10 is an SEM cross section of vias
containing voids [5].
Figure 7. (a) Inspection results for TSV etch showing a
portion of a full shot; (b) The zoomed-in region of interest
represented by the red box in (a).
By comparing this inspected TSV bottom surface map to the
desired TSV layout map, the incompletely etched vias can
be found and reported.
3. Cu-Fill
After the TSVs are etched in silicon wafers, the TSV barrier
and liner layers are deposited. The barrier and liner layers
impede the diffusion of Cu into the Si substrate, and provide
a wetting surface. When the TSVs are filled with copper
during electroplating fill process, several potential problems
might be introduced that are critical impacts to BEOL
reliability.
Figure 10 . SEM cross session of Cu filled TSVs that
showing voids that have formed near the via bottom.
One way to monitor the creation of voids during the plating
process is to interrupt the process when the vias are partially
filled to look for non-uniformity of the depth. After
incomplete plating of the same volume of copper in the
TSVs, vias containing voids will appear shallower than vias
without voids. See Figure 11. After depth metrology the
wafer can be returned and Cu-fill can be completed.
Figure 8. Schematic of Underfill and void problems in Cufill.
One possible problem is the underfill of the TSVs, as shown
in Figure 8. This may be caused by Cu plating control,
variation in etched TSV volume or aspect ratio, or the
inhomogeneity
of
barrier
thickness.
White-light
interferometry provides high precision measurements of the
post-plate surface that can be used to detect underfill vias.
Figure 9 shows the in-line Cu-underfill monitor data
acquired from a scanning white-light interferometry tool.
The data shows several excursion events which have been
determined to be related to issues within plating process
(such as bath chemical concentration, etc.).
Figure 11. Partially filled vias containing voids appear
shallower than vias without voids.
4. CMP-Erosion
Following the Cu deposition, Chemical Mechanical
Planarization (CMP) is used to remove the excess copper.
Maintaining a planar surface is critical to prevent problems
in subsequent layers during the metallization and during the
bonding process, and to maintain device performance.
Because of differences in polish rates and because of the
size of the vias, there can be erosion of the via or dishing of
the surrounding dielectric. Additionally, because the Cufilled TSV patterns are generally distributed unevenly on the
wafer, the polishing rate in regions of low pattern density
(low density of vias) can be different from regions of high
pattern density. Figure 12 shows the erosion of the dielectric
near a Cu-filled via. In order to avoid over-polishing and
minimize the erosion and dishing effects, the polishing time
may vary from region to region, making the CMP process
more difficult to control. Such process challenges require an
advanced metrology tool that can precisely and accurately
monitor the surface topography.
An example of erosion
presented in Figure 14.
topography which can
wafer, if the erosion is
tungsten contacts.
data collected with this method is
In addition to creating non-uniform
impact subsequent layers on the
sufficiently great, it can affect the
Figure 14. Erosion monitor show variation within wafer
and over time.
(a)
(b)
Figure 12. (a) SEM cross section of oxide layer
approximately 5 um away from TSV. (b) SEM cross section
of oxide layer adjacent to TSV. There is approximately 4nm
of erosion at the TSV.
To measure the erosion of the dielectric, which is on the
order of few nanometers, a high sensitivity surface
measurement tool, like an AFM or an interferometer, is
required. Figure 13 is an example of the wafer surface in the
vicinity of a via as measured by a white-light interferometer.
Using a white-light interferometer has throughput
advantages over slower profiling techniques, like AFM, as it
captures a full field of view in one measurement without the
need to raster.
5. TSV Cu-Pumping
When Cu-filled TSVs are exposed to high temperatures
during the BEOL anneal processing after polishing, high
compressive stresses arise in the Copper TSVs due to the
change in the grain structure of the copper in the via. This
can lead to plastic deformation of the Cu and protrusion of
Cu grains from the surface, and effect known as “Cupumping”. Figure 15 (a) is an example of TSV Cu pumping
cross-sections for a typical full-flow TSV wafer. This
extrusion of the Cu is an important reliability risk for the
BEOL process and cause yield losses or reduced device
lifetime.
(a)
(b)
Figure 15. (a) SEM cross section of Cu filled TSV from
typical full-flow wafer. (b) SEM image of TSV in the short
loop test wafer.
We show data from a series of TSV short-loop test wafers
that were used for a Cu-pumping study. Figure 15 (b) is the
SEM cross-section for the short-loop test wafer. The
extruded Cu heights were measured relative to the open
field area with a scanning white-light interferometer as
shown in Figure 16. Measurements were made on both
6X55um TSVs and 5X55um TSVs on short loop wafers
under different processing conditions.
Figure 13. An example of the wafer surface following
CMP in the vicinity of a TSV measured by white-light
interferometry.
Figure 16. Topography image of the post CMP TSV area
showing Cu pumping of roughly 70nm with a distinct
extruded Cu grain shape present.
It was determined that the layout (dense vs iso structures)
did not affect the Cu-pumping data. However, the smaller
CD vias have significantly lower Cu pumping following the
same anneal process. The mean pumping height decreased
roughly 40% in the 5um TSVs compared to the 6um TSVs.
However, as the few TSVs with the highest pumping value
(the extreme of the height distribution) are the most
significant reliability risk, it is crucial to take the entire data
distribution into consideration. In this case, we found the
maximum pumping value was nearly the same in both cases,
and is fairly high.
Figure 17 presents the Cu pumping distributions for anneal
conditions ranging from 250 to 430 deg. C, and 20 to 120
minutes for a 6X55um via. This data shows that at
temperatures of 430 deg C, we observed a significant
reduction in the pumping. A further reduction in the
pumping effect is achieved using longer anneal times.
6. TSV Reveal
As shown in the Via-Middle 3D TSV process flow of Figure
1, in the final step before packaging, the Cu filled TSV is
revealed on the wafer backside. This exposes the Cu for 3D
vertical interconnection. To perform TSV reveal, the device
wafer with filled TSVs is bonded with a temporary adhesive
to a carrier wafer. In order to avoid copper contamination,
the silicon of the device wafer is ground and polished to a
point several microns above the nails of the Cu-filled TSVs.
The same Si surface is then subjected to a silicon dry etch
process that exposes the copper TSV. The TSV is then
coated in CVD films, and finally bottom copper is exposed
by CMP. Figure 18 (a) is a SEM image of revealed TSV
Cu post-CMP and Figure 18 (b) is the SEM image of the
revealed TSV pillar post-etch. The diameter and step height
of the exposed copper pillars are then measured and
monitored inline for controlling those processes, and to look
for any defects due to bottom voided TSVs. Measurements
with a scanning white-light interferometer allow
measurements of 30 WPH or more with precision better
than 7 nm for the revealed Cu pillars.
(a)
(b)
Figure 18. (a) SEM image of revealed TSV copper, postCMP; (b) SEM image of the revealed pillar post-etch.
CONCLUSIONS
The introduction of through-silicon vias has enabled new
strategies for packaging and for increasing device density.
But as with any new technology, TSVs also bring their own
process and metrology challenges. While some of these
metrology challenges can be managed by conventional
means, like CD-SEM for the lithography, others may
require the adoption of new tools, like scanning white-light
interferometers.
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a second CMP process resulted in a 40% reduction in Cu
pumping for both mean and maximum values.
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