Integration of Electrografted Layers for the
Metallization of Deep TSVs
Claudio Truzzi, Ph.D.
Alchimer
International Wafer-Level Packaging Conference, October 11-14, 2010
Outline
• Introduction: The Drivers for TSVs
• Limitations of Traditional Dry-Process Approaches
• Electrografting Nanotechnology for TSV Applications
– Isolation/Barrier/Fill
– Isolation and Barrier Film Properties
– New Generation TSV Cu Fill
• Cost of Ownership
• 300-mm Wafer Wet-Process TSV Metallization Existing Infrastructure
• Conclusion
Main 3D-IC Driver
• Mobile systems vendors need TSV interconnects to support
the bandwidth needed for new data services, which include
point-to-point video, a market set to accelerate over the
next five years
– High-definition video encoding requires about 12.8 GB/s of
bandwidth between the processor and DRAM memory
– The only way to do that in a mobile system is with TSV-connected
logic-memory solution, such as an ARM-based processor stacked
with 400 MHz DDR3 memory chips
Source: chipdesignmag.com, June 26, 2010
What Type of TSV?
TSV Area Penalty as a function of AR
• The most strategic question
from the design perspective is 9,0%
Assumptions
450 USD
8,0%
about aspect ratio
die
10 x 10 mm
7,0%
# TSVs
10000
• The ability to decrease TSV
6,0%
TSV depth
50
µm
312 USD
diameter without affecting
Total Wafer Cost 6359 USD
5,0%
wafer thickness has huge
implications for how much die 4,0%
153 USD
3,0%
space is available for working
78 USD
2,0%
circuitry, and for the overall
28 USD
1,0%
cost impact of TSV adoption
0,0%
• At any given wafer thickness,
4:1
5:1
7:1
10:1
20:1
12µm
10µm
7µm
5µm
3µm
3DIC designers need TSVs that
Nominal TSV Diameter
can be scaled down
If AR < 10:1 then:
area penalty > 1%
cost >100 USD/wafer
Current TSV Solutions Based on Dry Process + ECD
Isolation
Barrier
Cu Seed
Cu Fill
Process Step
Deposition
Methods
and
Related Issues
CVD
iPVD/CVD
(i)PVD
ECD
High Temp>400C
Not compatible with
memory
applications
Smooth walls
needed -> low
etch rate
Discontinuous Film
AR<10
Inefficient plasma
cleaning for AR>5
Poor step coverage
AR<10
Discontinuous film
Large overburden:
thick film on wafer
flat to have thin
layer on TSV
bottom
AR<10
Low UPH
Size>5µm
Strongly acidic
Many additives
Expensive
membrane cells
Therm-Oxide
Very high temp
ALD
High Temp>400 C
Extremely low UPH
High Resistance
Dry-Process 300-mm TSV wafer CoO is too high
1. TSV
Manufacturing
3. Backside RDL
Backside Insulation
Deposition
Backside Barrier layer
Deposition
Cu Seed Deposition
Litho
Soft or Hard Mask
Etch/Drill Via (DRIE)
Post-Etch Clean
Insulation Layer
Deposition 4.
Barrier Layer Deposition
Litho
Solder Plate
PR Strip
Cu-TSV Fill
UBM etch
Post CMP Clean
2. Wafer Thinning
Equip. Depr. Cost @ 10 kw/m:
120 USD/wafer
Bumping
Seed Deposition
CMP
Minimum CapEx (1 tool/step):
70 MUSD
5. Bonding
Wafer Dicing
Die to Wafer Pick&Place
Carrier Bonding
Thermal Cure/attach
Thinning
Sequential
Thinning/stress Relief
Stacked Wafer Dicing
Consumables
Maintenance
Hookup costs
Utilities
Operator shifts
Overhead
Footprint ratio
Assumptions
Reference
3% of tool price
10% of tool price
Yole
Sematech
3
Yole
2.5
Yole
Total CoO @ 10 kw/m:
253 USD/wafer
The Way Forward: Scalable Wet-Process TSVs
• Current wet processing can
easily deliver AR>20 at a
significantly reduced cost:
– Wet Isolation: Polymer-based
– Wet Barrier: NiB-based
– Cu Fill: directly plated on
barrier
• Wet Process Properties:
– Highly conformal
– Strong Adhesion
– High Step Coverage
• Film properties match or
exceed those of dry-processed
films
Wet Isolation and Barrier Films
10:1 AR
11:1 AR
15:1 AR
18:1 AR
13x133 µm
9x120 µm
5x75 µm
4x72 µm
Isolation = 160 nm
Barrier = 71 nm
Isolation = 130 nm
Barrier = 65 nm
Isolation = 110 nm
Barrier = 48 nm
Step coverage :
Isolation : 68 %
Barrier : 67 %
Wet Isolation - Film properties
• CTE falls well within
accepted range
• Wet Isolation electrical
properties match or
exceed those of Si02
• Elasticity Modulus and
stress values enable the
Wet Isolation to play a
stress buffer role between
Si and Cu
Parameter
Value
Unit
CTE
Dielectric
constant
Breakdown
Voltage
Capacitance
Density
30
ppm/ºC
Leakage current
Surface Finish
Substrate
compatibility
3
SiO2 = 4.2
28
MV/cm
0.13
fF/µm2
15
1.6
nA/cm2
nm
< 200
Young Modulus
3.4
Stress
10
Notes
SiO2 = 10
SiO2 = 10-20
SiO2 = 2nm
Silicon
Ohm.cm substrate
resistivity
GPa
SiO2 = 107
MPa
SiO2 = 100
Wet NiB Barrier - Film properties
• Resistivity is much lower than industry reference
• Barrier properties are equivalent to TiN
• Cu diffusion rates equivalent to TaN/Ta
• Hardness value is half that
of TiN
• This is indicative of a
less brittle material
Parameter
Value
Unit
Notes
Resistivity
25
µOhm.cm
TiN = 100-250
Rs uniformity
5
%
Barrier property
Equivalent to TiN after 400 ºC 2 hours
Cu penetration after 2
hrs 400°C
Hardness
14.3
% barrier
thickness
GPa
Stress
200
MPa
42
TaN/Ta = 54%
TiN = 25
TaN = 1500
Ta = 350
High purity Cu fill for narrow, high AR TSVs
• Small-diameter high-AR plating
capability
• High-purity chemistry
• Direct plating on Barrier
• No chemical degradation of
underlying layer
• No need for “hot entry”
• Seamless integration of complete
wet-process TSV Metallization
module
Cu-fill TSV
2.5X25µm
Contaminants in copper bulk deposited with new fill vs.
Baseline ECD chemistry
Anneal 250°C
100000
100000
100000
10000
10000
10000
C
100
C
10
Cl
1000
C Aquivia Fill
C Enthone
^63Cu
Intensity (counts)
1000
Intensity (counts)
Intensity (counts)
Cu bulk
100
Cl
10
0
50
100
150
Depth (nm)
200
250
300
Cl Aquivia Fill
Cl Enthone
^63Cu
S Aquivia Fill
S Enthone
^63Cu
S
Baseline
100
S
10
New fill
1
1
1
1000
0
50
100
150
200
Depth (nm)
• C: 10X less for new fill chemistry
• Cl: 100X less for new fill chemistry
• S: comparable values
250
300
0
50
100
150
Depth (nm)
200
250
300
Grain size post anneal 400°C under forming gas
Commercially Available
New fill Chemistry
Much higher grain size uniformity
Higher grain mean value
Wet Process TSV- Reliability
• Successfully passed industry standard reliability tests
Wet-Processed TSVs after 1000 temp cycles
Moisture Sensitivity
Levels
High Temperature
Storage
Temperature cycle
Thermal shock
Solder Heat
Resistance
(IPC/JEDEC J-STD-20 Level 1)
Pass
(Mil Std 883 Method 1008 Condition C)
Pass
Pass
Pass
Pass
(Mil Std 883 Method 1010 Condition B, 1000 cycles)
(Mil Std 883 Method 1011 Condition B)
(JEDEC J-STD-020)
Cost of Ownership Model
• via size: 3x30 μ, AR=10
•
Assumptions:
NEW equipment for etching, deposition (dry, wet), filling
VIA DIMENSIONS
(µm)
ETCH + ISOLATION, BARRIER,
SEED + FILLING + CMP (1)
$89
3 x 30
Dry
$52
ISOLATION, BARRIER, SEED (2)
$43
$18
•150 kwspy
•300 mm wafer size
•95% process yield
•License included
•3 shifts per day
•Clean room class: 100
•CR surface ratio: 2,5
•Equipment Depreciation
time: 5 years
•Maintenance : 3%
•CR fully depreciated
1. eG insensitivity to scalloping allows for up to 40µm/min etch rate, contributing to
CoO reduction
2. Average savings with Electrografting: 60%
Source: Yole Développement
Wet-Process TSV Metallization - 300-mm Wafer
Existing Infrastructure
INFRASTRUCTURE
• 100m2 class 10K clean room
• SEMI complaint consumables
and waste treatment
TOOLS
• Manual wet benches
• ECD cell
• SRDs
Wet-Process TSV Metallization - Results
Liner
Barrier
Liner and barrier on Si/SiO2 stack
Full stack non-uniformity < 10%
Seed
Conclusion
• Expensive dry-process tools developed for dual
damascene applications are not at home in the TSV
world
• Integrated, streamlined wet-process solutions are
available today delivering higher performance at a
significantly reduced cost